Simulation of Nano Si and Al Wires Growth on Si(1O0) Surface

Growth of nano Si and Al wires on the Si(100) surfaces is investigated by computer simulation, including the anisotropic diffusion and the anisotropic sticking. The diffusion rates along and across the substrate dimer rows are different, so are the sticking probabilities of an adatom, at the end sites of existing islands or the side sites. Both one-dimensional wires of Si and Al are perpendicular to the dimer rows of the substrate, though the diffusion of Si adatoms is contrary to that of Al adatoms, i.e. Si adatoms diffuse faster along the dimer rows while Al adatoms faster across the dimer rows. The simulation results also show that the shape anisotropy of islands is due to the sticking anisotropy rather than the diffusion anisotropy,which is in agreement with the experiments.     

Time-resolved photoluminescence from self-assembled Ge(Si) islands in multilayer SiGe/Si and SiGe/SOI structures

The results of a study of the spectral and temporal characteristics of the photoluminescence (PL) from multilayer structures with self-assembled Ge(Si) islands grown on silicon and “silicon-on-insulator” substrates in relation to temperature and the excitation-light wavelength are presented. A substantial increase in island-related PL intensity is observed for structures with Ge(Si) islands grown on silicon substrates upon an increase in temperature from 4 to 70 K. This increase is due to the diffusion of nonequilibrium carriers from the silicon substrate into the active layer with the islands. In this case, a slow component with a characteristic time of ～100 ns appears in the PL rise kinetics. At the same time, no slow component in the PL rise kinetics and no rise in the PL intensity with increasing temperature are observed for structures grown on “silicon-on-insulator” substrates, in which the active layer with the islands is insulated from the silicon substrate. It is found that absorption of the excitation light in the islands and SiGe wetting layers mainly contributes to the excitation of the PL signal from the islands under sub-bandgap optical pump conditions.     

Metalorganic Chemical Vapor Deposition of CdTe(133) Epilayers on Si(211) Substrates

Single-crystalline CdTe(133) films have been grown by metalorganic chemical vapor deposition on Si(211) substrates. We studied the effect of various growth parameters on the surface morphology and structural quality of CdTe films. Proper oxide removal from the Si substrate is considered to be the principal factor that influences both the morphology and epitaxial quality of the CdTe films. In order to obtain single-crystalline CdTe(133) films, a two-stage growth method was used, i.e., a low-temperature buffer layer step and a high- temperature growth step. Even when the low-temperature buffer layer shows polycrystalline structure, the overgrown layer shows single-crystalline structure. During the subsequent high-temperature growth, two-dimensional crystallites grow faster than other, randomly distributed crystallites in the buffer layer. This is because the capturing of adatoms by steps occurs more easily due to increased adatom mobility. From the viewpoint of crystallographic orientation, it is assumed that the surface structure of Si(211) consists of (111) terrace and (100) step planes with an interplanar angle of 54.8°. This surface structure may provide many preferable nucleation sites for adatoms compared with nominally flat Si(100) or (111) surfaces. The surface morphology of the resulting films shows macroscopic rectangular-shaped terrace—step structures that are considered to be a (111) terrace with two {112} step planes directed toward 〈110〉.     

Fabrication method for IC-oriented Si single-electron transistors

A new fabrication method for Si single-electron transistors (SETs) is proposed. The method applies thermal oxidation to a Si wire with a fine trench across it on a silicon-on-insulator substrate. During the oxidation, the Si wire with the fine trench is converted, in a self-organized manner, into a twin SET structure with two single-electron islands, one along each edge of the trench, due to position-dependent oxidation-rate modulation caused by stress accumulation. Test devices demonstrated, at 40 K, that the twin SET structure can operate as two individual SET's. Since the present method produces two SET's at the same time in a tiny area, it is suitable for integrating logic circuits based on pass-transistor type logic and CMOS-type logic, which promises to lead to the fabrication of single-electron logic LSIs     

Self-ordered nanostructures grown by organometallic chemical vapor deposition on V-grooved substrates: experiments and Monte-Carlo simulations

The growth the GaAs/GaAlAs quantum wires by organometallic chemical vapor deposition on V-grooved substrates relies on the formation of a self-limiting AlGaAs surface profile and the thickness modulation in the form of a crescent of the GaAs layer. In order to gain understanding on the growth process at the atomic level, we developed a two-dimensional Monte-Carlo simulation based on the solid-on-solid model. In good agreement with experimental results, our kinetic model shows that the self-limited profile results from the competition between the growth rate anisotropy on the different facets of the groove and the surface diffusion of adatoms. The predictions of the growth modeling are experimentally employed to control at the nanometer scale the shape of quantum wires using successive changes in the growth conditions. This understanding of the growth mechanisms opens the way to an accurate control of the quantum confinement in quantum wires.     

Study on ta diffusion barrier in Al/Si system

The property of Ta as a diffusion barrier is studied for Al/Ta/Si structure. Interfacial reactions of Al(180 nm)/Ta(130 nm)/Si and Al(180 nm)/Ta(24 nm)/Si, in the temperature range 450∼600°C for 30 min, have been investigated. In Al/Ta(130 nm)/Si system, which is Ta-excess case, Al₃Ta is formed at 500°C. At 575°C, TaSi₂ is formed at the interface of Ta Si. At 600°C, after Al₃Ta decomposes at the interface of Al₃Ta TaSi₂, free Ta is bonded to TaSi₂ with the supply of Si from Si substrate and free Al diffuses through TaSi₂, resulting in Al spiking. In Al/Ta(24 nm)/Si system, which is Al-excess case, Al₃Ta is formed at 500°C. At the same temperature of 500°C, after Al₃Ta decomposes at the interface of Al₃Ta/Si, free Ta reacts with Si to form TaSi₂ and free Al diffuses to Si substrate, resulting in Al spiking. The results of interfacial reactions can be understood from the calculated Al-Si-Ta ternary phase diagram. It can be concluded that the reaction at Al/Ta should be suppressed to improve the performance of Ta diffusion barrier in Al/Si system.     

Critical conditions for SiGe island formation during Ge deposition on Si(100) at high temperatures

The strain relaxation during the Ge growth on Si(100) occurs vikia surface diffusion and Si-Ge intermixing at temperatures below 800 °C. The Ge diffusion into the Si substrate is an additional process at higher temperatures. We found that, if its rate is higher than the Ge deposition rate, the island formation is not realized. We determined the critical Ge deposition rate as a function of the temperature in the range of 840–960 °C, at which the dynamic equilibrium between the growth of islands and their decay through the diffusion takes place. The islands grown in the conditions close to the dynamic equilibrium are ordered with a distance between them of about 1 µm and they form a smoothed surface morphology. These are indicative of the surface layer strain uniformity. The islands have a SiGe composition which, in the direction parallel to the sample surface, is more uniform in comparison with the islands grown at lower temperatures. The results show that the use of high temperatures essentially improves the conditions for the heterostructure self-organization.     

Selective Zn diffusion in n-GaAs with a sputtered Si mask at 650°C

Zinc has been selectively diffused into n-GaAs substrates with a mask of Si deposited by magnetron sputtering at room temperature. No lateral enhanced diffusion along the substrate/mask interface is observed. At the diffusion temperature of 650°C studied here, no appreciable Si diffusion into the substrate is observed.     

Effect of silicon spacer thickness on the electroluminescence of multilayer structures with self-assembled Ge(Si)/Si(001) islands

The results of investigation of the electroluminescence of multilayer p-i-n structures with Ge(Si)/Si(001) self-assembled islands are presented. The nonmonotonic dependence of the room-temperature intensity of the electroluminescence signal from islands on the Si spacer thickness is revealed. The highest electroluminescence signal intensity is observed for structures with a Si spacer thickness of 15?C20 nm. The significant decrease detected in the electroluminescence signal from the islands in structures with thick Si spacers (>20 nm) is explained by the formation of defect regions in them. The observed decrease in the electroluminescence signal in structures with thin Si layers is associated with a decrease in the Ge fraction in the islands in these structures, which is caused by enhanced Si diffusion into islands with increasing elastic strains in the structure.     

Effect of parameters of Ge(Si)/Si(001) self-assembled islands on their electroluminescence at room temperature

The electroluminescence (EL) of multilayered p-i-n structures with the self-assembled Ge(Si)/Si(001) islands are investigated. It is found that the structures with islands grown at 600°C have the highest intensity of the electroluminescence signal at room temperature in the wavelength range of 1.3–1.55 μm. The annealing of structures with the Ge(Si) islands leads to an increase in the EL-signal intensity at low temperatures and hampers the temperature stability of this signal, which is related to the additional Si diffusion into islands during annealing. The found considerable increase in the electroluminescence-signal intensity with the thickness of the separating Si layer is associated with a decrease in the elastic stresses in the structure with an increase in this layer’s thickness. The highest EL quantum efficiency in the wavelength range of 1.3–1.55 μm obtained in investigated structures amounted to 0.01% at room temperature.     

On the Mechanisms Governing Aluminum-Mediated Solid-Phase Epitaxy of Silicon

Mechanisms governing the aluminum-mediated solid-phase epitaxy of Si on patterned crystalline Si substrates have been identified by studying the deposited material as a function of growth conditions when varying parameters such as temperature, growth time, and layer-stack properties. Early growth stages can be discerned as first formation of “free” Si at the Al/α-Si interface, then diffusion of Si along the Al grain boundaries, nucleation at the Si substrate surface, nuclei rearrangement, and finally crystal growth. The acquired understanding is applied to control the selectivity and completeness of single-crystal growth in various sizes of contact windows to the Si substrate.     

原位XPS分析Al2O3作为势垒层的Er2O3/Si结构

在超高真空条件下,通过脉冲激光沉积(PLD)技术制作了Er2O3/Al2O3/Si多层薄膜结构,原位条件下利用X射线光电子能谱(XPS)研究了Al2O3作为势垒层的Er2O3与Si界面的电子结构.XPS结果表明,Al2O3中Al的2p芯能级峰在低、高温退火前后没有变化;Er的4d芯能级峰来自于硅酸铒中的铒,并非全是本征氧化铒薄膜中的铒;衬底硅的芯能级峰在沉积Al2O 3时没有变化,说明Al2O3薄膜从沉积到退火不参与任何反应,与Si界面很稳定;在沉积Er2O3薄膜和退火过程中,有硅化物生成,表明Er2O3与Si的界面不太稳定,但随着Al2O3薄膜厚度的增加,其硅化物中硅的峰强减弱,含量减少,说明势垒层很好地起到了阻挡扩散的作用.     

Behaviors of surfactant atoms on Si(001) surface

The behaviors of surfactant atoms for thin film growth on the Si(001) surface formed by molecular beam epitaxy were observed. At first, heterointerfaces on Si/Ge and Ge/Si without surfactant effect were investigated and are discussed on the basis of thermodynamics of surfaces and surface diffusion. The mechanism of island formation as a later stage of Stranski-Krastanov growth mode is also discussed. Surfactant effects of Bi atoms on the heteroepitaxial structures were investigated experimentally. Behavior of Sb as a surfactant was also observed and compared with the results of Bi. Mechanisms for improvements in the abruptness at heterointerfaces of Si/Ge/Si as well as suppression of island formation are discussed. The formation of atomic-scale wires of Bi was observed. The structure of Bi wires at high temperatures is described.     

Mechanisms determining three-dimensional SiGe lsland density on Si(001)

Thin, coherently strained, films of SiGe were deposited on Si(001) in the Stranski-Krastanow (SK) growth mode to form small, faceted, dislocation-free-three-dimensional (3D) islands. The number density of these islands was determined as functions of SiGe alloy composition, growth rate, and substrate temperature during growth. From these experiments, the classical model of 3D island nucleation and growth yields an approximate activation energy for diffusion of Ge dimers on a Ge covered Si(001) surface of 0.70 eV. The dependence of the 3D-island number density on growth rate cannot be understood without modifying the classical model to account for the wetting layer present in SK systems. Heteroepitaxial strain is not included in the classical model of island nucleation and growth. A simple linear elastic model that fits the data is developed that predicts the island number density is proportional to the inverse square of the Ge mole fraction in the alloy plus a constant.     

Self-assembling Ge(Si)/Si(100) quantum dots

The morphological evolution of self-assembled epitaxial quantum dots on Si(100) is reviewed. This intensely investigated material system continues to provide fundamental insight guiding the growth of nanostructured electronic materials. Self-assembled quantum dots are faceted, three-dimensional islands which grow atop a planar wetting layer. Pure Ge growth at higher substrate temperatures results in narrower island size distributions but activates additional strain-relief mechanisms which will alter the optical and electronic properties of the dots. Optical and electrical characterization has shown that electrons and holes are confined to different regions of the dot. This results in a spatially indirect, type II recombination mechanism. Emerging device applications which exploit properties of these nanoscale Ge islands are discussed.     

Interaction of self-assembled Ge islands and adjacent Si layers grown on unpatterned and patterned Si(001) substrates

For use in electronic devices, self-assembled Ge islands formed on Si(001) must be covered with an additional Si layer. Chemically vapor deposited Si layers initially grow very rapidly over Ge islands because of the catalytic effect of Ge on the reaction of the Si-containing gas. The edges of the Si features covering Ge “pyramids” are rotated by 45° with respect to the edges of the Ge pyramids because of the different mechanisms orienting the Ge islands and the Si features. When multiple layers of islands are formed, the in-plane ordering of the Ge islands depends on the thickness of the Si interlayer separating the island layers. When selective Si is grown on a patterned Si wafer to form the underlying structure for the Ge islands, the position of the islands is influenced by the detailed shape of the Si near the edges, which in turn depends on the thickness of the selectively deposited Si, the pattern size, and the amount of surrounding oxide.     

CaF_2/Si(111)界面的电子结构和化学键(英文)

CaF_2/Si(111) interfaces formed at 700℃ as well as at room temperature have been studied with XPS, UPS and LEED. The experimental results show that the substrate temperature has a significant influence on the interface in respect of ifs electronic structure and chemical bond. When the substrate temperature was at 700℃, the interface is found to be consisted of predominate Si-Ca bonds which correspond to an interface state located at 1.2eV below Fermi level. There is depletion of fluorine atoms due to the dissociation of the CaF2 molecule at the interface. When the substrate was at room temperature, there are no chemical bonds between substrate and adatoms nor depletion of fluorine atoms at the interface. Annealing of this interface at 700℃ results in preferential evaporation of F, and the surface undergoes a number of reconstructions until a 3×1 reconstruction is obtained. The bonding at this interface is similar to that of CaF2/Si(111) interface when the substrate temperature was at 700℃.     

Special features of the formation of Ge(Si) islands on the relaxed Si1−xGex/Si(001) buffer layers

The results of studying the growth of self-assembled Ge(Si) islands on relaxed Si_1?xGe_x/Si(001) buffer layers (x≈25%), with a low surface roughness are reported. It is shown that the growth of self-assembled islands on the buffer SiGe layers is qualitatively similar to the growth of islands on the Si (001) surface. It is found that a variation in the surface morphology (the transition from dome-to hut-shaped islands) in the case of island growth on the relaxed SiGe buffer layers occurs at a higher temperature than for the Ge(Si)/Si(001) islands. This effect can be caused by both a lesser mismatch between the crystal lattices of an island and the buffer layer and a somewhat higher surface density of islands, when they are grown on an SiGe buffer layer.     

10%TMAH硅湿法腐蚀技术的研究

研究了浓度为10%的四甲基氢氧化铵(TMAH)溶液,在不同量的Si粉掺杂下,对铝膜及硅衬底的腐蚀及其pH值的变化。测试了在满足铝膜极低的腐蚀速率(<1nm/min)时,不同温度下该腐蚀液对硅(100)、(111)和(110)晶面及SiO2介质膜的腐蚀速率。还介绍了添加剂—过硫酸铵(APODS)和吡嗪的加入对腐蚀表面形貌及腐蚀速率的影响。研究结果表明,存在着一个临界的硅粉添加量,超过此量后铝膜的腐蚀速率急剧降低。90℃时,在10%TMAH溶液中加入1 5mol/L硅粉、3 0g/LAPODS和2g/L吡嗪可以实现铝膜不被腐蚀,同时硅(100)面约有1μm/min的腐蚀速率,腐蚀表面平整。腐蚀后的铝膜表面同硅铝丝键合良好,实现了腐蚀工艺同CMOS工艺的完全兼容。     

Photoluminescence line width of self-assembled Ge(Si) islands arranged between strained Si layers

The effect of variations in the strained Si layer thicknesses, measurement temperature, and optical excitation power on the width of the photoluminescence line produced by self-assembled Ge(Si) nanoislands, which are grown on relaxed SiGe/Si(001) buffer layers and arranged between strained Si layers, is studied. It is shown that the width of the photoluminescence line related to the Ge(Si) islands can be decreased or increased by varying the thickness of strained Si layers lying above and under the islands. A decrease in the width of the photoluminescence line of the Ge(Si) islands to widths comparable with the width of the photoluminescence line of quantum dot (QD) structures based on direct-gap InAs/GaAs semiconductors is attained with consideration of diffusive smearing of the strained Si layer lying above the islands.