射频电路PCB板电磁兼容设计方法与技巧

本文介绍了射频电路PCB板电磁兼容性设计原则,电源、地线设计方法,并介绍了射频电路PCB板分区布局布线的经验与技巧.     

印制板中地线正确连接原则的讨论

印制板的接地方式非常重要,如果地线布线不合理,就可能引起不可接受的测量误差。本文通过一个典型的热电偶数字测温系统的地线连接的分析,来说明PCB中地线正确连接的重要性和接地原则。文章说明了在模拟和数字信号混合系统中连接PCB地线时,应该防止有较大的地电流,特别是应防止数字电路中大的脉冲地电流流入模拟电路的地线中,尤其不应流入小信号模拟电路的地线中。     

数模混合电路PCB的电磁兼容设计

数模混合信号电路PCB的设计很复杂,元器件的布局、布线以及电源和地线的处理将直接影响到电路性能和电磁兼容性能。本文系统地介绍了数模混合信号电路设计时的注意事项及在实际应用中所采取的优化电路性能的措施。     

PCB布线设计(之二)

工程领域中的数字设计人员和数字电路板设计专家在不断增加,这反映了行业的发展趋势。尽管对数字设计的重视带来了电子产品的重大发展,但仍然存在,而且还会一直存在一部分与模拟或现实环境接口的电路设计。模拟和数字领域的布线策略有一些类似之处,但要获得更好的结果时,由于其布线策略不同,简单电路布线设计就不再是最优方案了。本文就旁路电容、电源、地线设计、电压误差和由PCB布线引起的电磁干扰(EMI)等几个方面,讨论模拟和数字布线的基本相似之处及差别。模拟和数字布线策略的相似之处旁路或去耦电容在布线时,模拟器件和数字器件都…     

印制电路板的接地技术与地线干扰分析

印制电路板(PCB)是电子产品中电子元件的支撑件.印制板的接地方式非常重要,如果地线布线不合理,就可能引起不可接受的测量误差.本文分析了几种接地方式,探讨了地线带来的干扰,并通过对一个典型的运算放大电路地线连接的分析,来说明PCB中地线正确连接的重要性和接地原则.     

PCB板的地线布线技术

本文针对PCB板地线的电磁兼容问题进行分析，并对PCB板布线中的几种地线布线方法进行分类，给出了每种布线方法的使用范围及布线规则。     

音响器材PCB业余制作经验谈（下）——PCB布局布线技巧

有了一定的低频模拟电路的PCB布局布线技巧和高速数字电路的PCB布局布线技巧,那么可以考虑着手数模混合电路的布局布线了,但复杂混合电路的布局布线往往更难。数字音频设备基本上都是混合电路,发烧友常做的比较复杂的混合电路当属DAC解码器了。     

印制电路板电磁兼容设计浅析

文中介绍了印制电路板上电磁干扰辐射产生的主要原因,并对其产生的机理进行了详细的研究和分析,得出了能够减少电磁干扰的几种方法。在印刷电路板设计中,对单面板的线路板迹线的阻抗和PCB布线的分析以及对双层PCB板的设计分析,基本保证了印电路板的质量与可靠性,并减小了电肱干扰的影响。最后,通过对地线网络、地线面、输入输出地的结构、地线布线规则等几种接地方式进行较为详细的研究与分析,得出了进一步减小电磁干扰的方法。     

射频电路PCB设计

介绍了采用PROTEL99SE进行射频电路PCB设计的设计流程。为了保证电路的性能，在进行射频电路PCB设计时应考虑电磁兼容性。因而重点讨论了元器件的布局与布线原则来达到电磁兼容的目的。     

关于模拟布局和数字布局技术的要领与应用

本文对旁路电容、电源、地线设计、电压误差和由PCB布线引起的电磁干扰（EMI）等几个方面问题，以及和模拟和数字布线的基本准则进行讨论与分析，并以12位传感系统为例对布局窍门的应用作说明。     

TMS320C5402芯片基本硬件设计

讨论了TMS320C5402芯片的时钟电路、电源电路、复位电路等基本硬件电路的设计方法，并给出了接线图。     

数字超声无损探伤系统中模拟电路的设计实现

在超声波无损探伤原理的基础上,介绍了A型数字超声探伤系统中模拟部分的设计与实现。模拟电路部分包括：激励超声波探头的宽带窄脉冲发射电路,隔离发射和接收的限幅电路,可控增益放大电路以及滤波等信号调理电路。在模拟电路的设计实现中,以STM32和FPGA为控制核心,实现对超声波发射和接收的控制。这些电路采用模块化的设计思想,功能强大、容易实现,具有广泛的应用价值。实验结果表明,这些电路性能良好,稳定可靠。     

Reliability optimization of analog integrated circuits considering the trade-off between lifetime and area

The reliability of analog integrated circuits becomes a major concern for the semiconductor industry as technology continuously scales. Among the many contributing factors, manufacturing process induced parameter variations and lifetime operational-condition-dependent transistor aging are two major hurdles limiting the reliability of analog circuits. Process variations mainly influence the parametric yield value of the fresh circuits, while transistor aging due to physical effects, such as Negative Bias Temperature Instability (NBTI) and Hot Carrier Injection (HCI), will cause another yield loss during circuit lifetime. In the past decades, the two issues were mainly studied separately by various communities, but analog designers nowadays need an accurate yet efficient method to analyze and optimize their circuits during the design phase, to ensure a more robust design tolerant of such joint effects.This paper proposes an efficient method for sizing of analog circuits for reliability. It is based on the analysis and optimization of the fresh worst-case distance value for each circuit performance, which can be used to characterize the robustness of circuits considering process variations and aging effects in terms of x-sigma. The fresh and aged sizing rules as well as the maximum area constraints are checked during the optimization. The trade-off between the circuit lifetime and the price we pay in terms of layout area is studied in detail. According to the result of this trade-off analysis, a longer circuit lifetime requires more total area to be spent in layout, and designers can ensure the circuit robustness with certain layout area consumption.     

一种分析模拟电路中互连线的新方法

互连线在高性能模拟集成电路中的影响已变得越来越不可忽视,部分元等效电路法（Partial Element Circuit,PEEC）是一种分析互连线的有效模型,常用方法是再用SPICE等数值模拟软件对PEEC模型进行分析。文中提出的用符号分析法模拟PEEC模型以及其它电路元器件,具有大大降低运算量等优点。基于这一点开发出一套交互式程序,使得包括考虑互连线影响的模拟电路的设计、验证和优化变得更容易、更有效率。     

Trends in CAD of analog ICs

This article presents views on the current trends in the field of computer-aided design (CAD) of analog integrated circuits (ICs), as gathered from a broad survey. The survey was conducted across various academic institutions and semiconductor industries, as well as government research funding agencies. The survey requested in-depth responses and the results were qualitative in nature, therefore, no numerical tabulation was possible. The future directions for the analog CAD field as presented in the survey indicate a need for increased activity and developments. The article gives an overview of analog circuit design and then summarizes the survey results, which are fairly detailed and cover various aspects of the analog circuit design automation process     

一种类OLED驱动的FED驱动电路的设计

通过与有机发光二极管(Organic light emitting diode,OLED)显示驱动电路的比较,得出了场致发射显示器(Field emission display,FED)驱动电路的特征,并在此基础上设计了基于简单IC与专用IC芯片的驱动电路,为FED驱动电路的实际应用提供了一种切实可行的思想方案.     

An insect vision-based motion detection chip

The architectural and circuit design aspects of a mixed analog/digital very large scale integration (VLSI) motion detection chip based on models of the insect visual system are described. The chip comprises two one-dimensional 64-cell arrays as well as front-end analog circuitry for early visual processing and digital control circuits. Each analog processing cell comprises a photodetector, circuits for spatial averaging and multiplicative noise cancellation, differentiation, and thresholding. The operation and configuration of the analog cells is controlled by digital circuits, thus implementing a reconfigurable architecture which facilitates the evaluation of several newly designed analog circuits. The chip has been designed and fabricated in a 1.2-μm CMOS process and occupies an area of 2×2 mm²     

Variability aware SVM macromodel based design centering of analog circuits

Design centering is the term used for a procedure of obtaining enhanced parametric yield of a circuit despite the variations in device and design parameters. The process variability in nanometer regimes manifest into variations in these devices and design parameters. During design space exploration of analog circuits, a methodology to find design-instances with better yield is necessitated; this would ensure that the circuit will function as per specifications after fabrication, even with impact of statistical variations. We need to evaluate circuit performance for a given instance of a circuit-design identified by possessing a set of nominal values of device-design parameters. A lot of instances need be searched, having different sizes for a given circuit topology. HSPICE is very compute intensive. Instead, we employ macromodeling approach for analog circuits based on support vector machine (SVM), which enables efficient evaluation of performance of such circuits of different sizing during yield optimization loops. These performance macromodels are found to be as accurate as SPICE and at the same time, time-efficient for use in sizing of analog circuits with optimal yield. Process variability aware SVM macromodels are first trained and then used inside the Genetic algorithm loops for design centering of different circuits, subsequently resulting into sized-circuit instances having optimal yield. Post design centering, the sized circuits will be able to provide functions as per specifications upon fabrication. The application of this design centering approach as process variability analysis tool is illustrated on various circuits e.g. two stage op amp, voltage controlled oscillator and mixer circuit with layouts drawn into 90?nm UMC technology (Euro-practice).     

数字电路、模拟电路微组装组件

本文介绍数字电路、模拟电路微组装组件的电路模拟、布线设计、工艺途径和关键技术,简要介绍有关组件的可靠性试验。     

超高频无源电子标签芯片的模拟电路设计

电子标签芯片是无线射频识别(RFID)技术的核心,其模拟电路的设计十分关键。基于ISO/IEC18000-6C标准,以设计出符合标准的标签芯片为设计目标,超高频(UHF)无源电子标签芯片模拟电路被提出。它分为电源产生电路、调制解调电路以及上电复位模块等模块。设计结果表明,设计的电路具有很高的整流效率,满足了设计需求。