A 622-Mb/s bit/frame synchronizer for high-speed backplane datacommunication

A compact 622-Mb/s/port bit/frame synchronizer is presented. Sampling equally-phased clocks from a phase-locked loop (PLL) at the data transition edges, the bit synchronizer selects the optimum one as the extracted clock. An elastic serial-to-parallel converter is used for the frame synchronization. The circuit is designed for a 32-port ATM switch chip, achieving 622-Mb/s port capacity by four parallel 156-Mb/s bits. Using 0.5-μm CMOS technology, the circuit was verified by simulations. The bit synchronizer consumes only 15 mW under typical conditions     

A low-power 8-PAM serial transceiver in 0.5-μm digital CMOS

An 8-PAM CMOS transceiver is described in this paper. Pre-emphasis is implemented without an increase in DAC resolution or digital computation. The receiver oversamples with three fully differential 3-bit ADCs. The prototype transmits at up to 1.3 Gb/s and has a measured bit error rate of less than 1 in 10¹³ for an 810-Mb/s pseudorandom bit sequence transmission. The device, packaged in a 68-pin ceramic leadless chip carrier, is implemented in 0.5-μm digital CMOS, occupies 2 mm², and dissipates 400 mW from a 3.3-V supply     

A 9.6-Gb/s HEMT ATM switch LSI with event-controlled FIFO

An asynchronous-transfer-mode (ATM) switch LSI was designed for the broadband integrated services digital network (B-ISDN) and fabricated using 0.6-μm high-electron-mobility-transistor (HEMT) technology. To enhance the high-speed performance of direct-coupled FET logic (DCFL), event-controlled logic was used instead of conventional static memory for the first-in first-out (FIFO) buffer circuit. The 4.8-mm×4.7-mm chip contains 7100 DCFL gates. The maximum operating frequency was 1.2 GHz at room temperature with a power dissipation of 3.7 W. The single-chip throughput was 9.6 Gb/s. An experimental 4-to-4 ATM switching module using 16 switch LSIs achieved a throughput of 38.4 Gb/s     

Single-chip 4×500-MBd CMOS transceiver

A CMOS chip containing four 500-MBd serializer/deserializer pairs has been designed to relieve interconnect congestion in an ATM switch system. The 9.7×9.7 mm² chip fabricated in a 0.8-μm technology is packaged on a ceramic ball grid array and dissipates 3.5 W. It replaces a 72-wire parallel interface with an eight-line serial interface transparent to the user and supports transmission at 1.6 Gb/s per direction in full-duplex mode. Virtually error-free operation in a system environment over electrical serial links having up to 9 dB loss at 500 MHz has been realized using signal predistortion for the serial bit stream and PLL clock recovery for each of the four receivers. Interface timing and serial-link driver strength are programmable     

A CMOS Batcher and Banyan chip set for B-ISDN packet switching

A Batcher and Banyan chip set suitable for broadband packet switch applications is described. Each chip concurrently processes 32 bit-serial packet channels and is a building block for larger networks. Current chip samples have been tested at channel rates of 170 Mb/s in 1.2-μm double-metal single-poly CMOS for both the Batcher and Banyan chips. Each chip requires a 5-V supply, dissipates approximately 1.5 W, provides 5.44 Gb/s of switching capacity, can process 12.8 million asynchronous transfer mode (ATM) cells per second, and is packaged in an 84-pin leadless ceramic chip carrier (LCCC) for convenient testing. The design and implementation of the switching elements capable of supporting the high-speed bit-serial channels and the chip architectures that accommodate them are described in detail     

A 50-Mbit/s CMOS monolithic optical receiver

A general-purpose CMOS optical receiver that operates at data rates from 1 to 50 Mb/s has been fabricated in a 1.75-μm CMOS process. The technology choice resulted in a high level of integration compared with similar bipolar technology receivers. The measured minimum signal current for a 10^-9 bit error rate at 50 Mb/s is 48-nA r.m.s. Automatic gain control gives the receiver an electrical input dynamic range of greater than 60 dB. The outputs are TTL (transistor-transistor logic)-compatible and the chip dissipates less than 500 mW when switching at maximum speed. The die area is 16 mm² . A comprehensive noise analysis of the receiver front end provides insight into the design tradeoffs of optical receiver preamplifiers. A wideband precision amplifier used in the linear channel is discussed in detail. A simple method for recovering low-frequency signal information lost in AC coupling is described     

Polarization-insensitive InP-based MQW digital optical switch

A polarization-insensitive InP-based p-i-n multiple-quantum-well switch is demonstrated for the first time. Polarization-insensitive switching and loss are achieved. Crosstalk and loss measurements across a wavelength range of 20 nm centered at 1.55 μm are reported. A crosstalk of better than -13 dB is achieved for both TE and TM polarizations across the 1.54-1.56-μm wavelength range with a switching voltage of -7 V. A low on-chip loss of less than 3 dB is achieved for both TE and TM across the above wavelength range, with a compact switch structure which is 3 mm long     

Time resolution of NMOS sampling switches used on low-swing signals

A number of recently reported CMOS line receivers and downconversion mixers are based on sampling. A key component in these designs is the NMOS sampling switch. It can sample a very high bandwidth signal, several GHz for a 0.8-μm transistor. We present an expression for the aperture time for an NMOS switch when the input has low swing. The switch can, under this condition, be modeled as a device that determines a weighted average over time of the input signal. The weight function is derived. The aperture time function shows that the maximum theoretical time resolution for a switch in 0.8-μm standard CMOS is 21 ps (~48 Gb/s). SPICE simulations agree with the theory. Transient two-dimensional (2-D) device simulations do not contradict the predicted results. Experiments on a switch made in a 0.8-μm standard CMOS process show successful sampling of every thirty second bit of a 5-Gb/s data stream     

A Single-Chip CMOS-Based Parallel Optical Transceiver Capable of 240-Gb/s Bidirectional Data Rates

We report here on the design, fabrication, and high-speed performance of a parallel optical transceiver based on a single CMOS amplifier chip incorporating 16 transmitter and 16 receiver channels. The optical interfaces to the chip are provided by 16-channel photodiode (PD) and VCSEL arrays that are directly flip-chip soldered to the CMOS IC. The substrate emitting/illuminated VCSEL/PD arrays operate at 985 nm and include integrated lenses. The complete transceivers are low-cost, low-profile, highly integrated assemblies that are compatible with conventional chip packaging technology such as direct flip-chip soldering to organic circuit boards. In addition, the packaging approach, dense hybrid integration, readily scales to higher channel counts, supporting future massively parallel optical data buses. All transmitter and receiver channels operate at speeds up to 15 Gb/s for an aggregate bidirectional data rate of 240 Gb/s. Interchannel crosstalk was extensively characterized and the dominant source was found to be between receiver channels, with a maximum sensitivity penalty of 1 dB measured at 10 Gb/s for a victim channel completely surrounded by active aggressor channels. The transceiver measures 3.25times5.25 mm and consumes 2.15 W of power with all channels fully operational. The per-bit power consumption is as low as 9 mW/Gb/s, and this is the first single-chip optical transceiver capable of channel rates in excess of 10 Gb/s. The area efficiency of 14 Gb/s/mm² per link is the highest ever reported for any parallel optical transmitter, receiver, or transceiver reported to-date.     

A monolithic 480 Mb/s parallel AGG/decision/clock-recovery circuitin 1.2-μm CMOS

A parallel architecture for high-data-rate AGC/decision/clock-recovery circuit, recovering digital NRZ data in optical-fiber receivers, is described. Improvement over traditional architecture in throughput is achieved through the use of parallel signal paths. An experimental prototype, fabricated in a 1.2-μm double-poly double-metal n-well CMOS process, achieves a maximum bit rate of 480 Mb/s. The chip contains variable gain amplifiers, clock recovery, and demultiplexing circuits. It yields a BER of 10^-11 with an 18 mV_p-p differential input signal. The power consumption is 900 mW from a single 5 V supply     

A 2.5-V, 333-Mb/s/pin, 1-Gbit, double-data-rate synchronous DRAM

A double data rate (DDR) at 333 Mb/s/pin is achieved for a 2.5-V, 1-Gb synchronous DRAM in a 0.14-μm CMOS process. The large density of integration and severe device fluctuation present challenges in dealing with the on-chip skews, packaging, and processing technology. Circuit techniques and schemes of outer DQ and inner control (ODIC) chip with a non-ODIC package, cycle-time-adaptive wave pipelining, and variable-stage analog delay-locked loop with the three-input phase detector can provide precise skew controls and increased tolerance to processing variations. DDR as a viable high-speed and low-voltage DRAM I/O interface is demonstrated     

A 0.3-μm CMOS 8-Gb/s 4-PAM serial link transceiver

An 8-Gb/s 0.3-μm CMOS transceiver uses multilevel signaling (4-PAM) and transmit preshaping in combination with receive equalization to reduce intersymbol interference due to channel low-pass effects. High on-chip frequencies are avoided by multiplexing and demultiplexing the data directly at the pads. Timing recovery takes advantage of a novel frequency acquisition scheme and a linear phase-locked loop that achieves a loop bandwidth of 35 MHz, phase margin of 50°, and capture range of 20 MHz without a frequency acquisition aid. The transmitted 8 Gb/s data are successfully detected by the receiver after a 10-m coaxial cable. The 2×2 mm² chip consumes 1.1 W at 8 Gb/s with a 3-V supply     

A 2.5 Gb/s ATM switch chip set

The design and implementation of two application specific integrated circuits used to build an ATM switch are described. The chip set is composed of the CMC which is an input/output processor of ATM cells implemented on a BICMOS 0.7 μm technology and the ICM, a 0.7 μm CMOS IC, that performs cell switching at 68 MHz. The ATM switch exploits parallelism and segmentation to perform 2.5 Gb/s switching per input/output. The main advantage of the high-speed link rates in the range of Gb/s, is the exploitation of statistical gain with bursty high peak rate sources. Another feature of the high speed ATM switches is that the number of interface devices and stages is reduced on an ATM network. To demonstrate the usefulness of the switch, an evaluation of the network efficiency improvement by using statistical gain is presented in the paper     

On-chip sampling in CMOS integrated circuits

This paper presents a technique for precise crosstalk delay measurement based on on-chip sampling. Results obtained on a test chip fabricated in 0.7-μm CMOS technology exhibit a 100% delay increase in a long coupled line configuration     

A programmable focal-plane MIMD image processor chip

An 80×78 pixels vision chip for focal-plane image processing is presented. The chip employs a Multiple-Instruction-Multiple-Data (MIMD) architecture to provide five spatially processed images in parallel. The size, configuration, and coefficients of the spatial kernels are programmable. The chip's architecture allows the photoreceptor cells to be small and parked densely by performing all computations on the read-out, away from the array. The processing core uses digitally programmed current-mode analog computation. Operating at 9.6 K frames/s in 800-lux ambient light, the chip consumes 4 mW from a 2.5-V power supply. Performing 11×11 spatial convolutions, an equivalent computation (5.5 bit scale-accumulate) rate of 12.4 GOPS/mW is achieved using 22 mm² in a 1.2-μm CMOS process. The application of the chip to line-segment orientation detection is also presented     

A 70-Mbit/s (RZ) 16×16 crosspoint switch for ternary-encodedsignals

An experimental 16×16 crosspoint switch that can switch ternary signals and handle data rates of up to 70 Mb/s return-to-zero (RZ) (equivalent to 140-Mb/s nonreturn-to-zero (NRZ)) per channel is described. Ternary signals, in particular, alternate mark inversion (AMI) encoded signals, are widely used in telephone interoffice digital-transmission systems. This chip could be used in an asynchronous cross-connection system at the DS3 (44.736-Mb/s) signal level. This crosspoint chip has 16 input and 16 output channels. Any input can be connected to any output or outputs without blocking. The architecture allows for paralleling many chips to increase the size of the crosspoint array and also for cascading them to provide multistage switching capability. The switch can be addressed in the same way as a memory chip, and the cross-connection map can be written to and read back from the device. The chip is fabricated using a standard 2-μm CMOS technology, and the die size is 20.16 mm² (177.2×176.4 mil), containing about 11000 transistors     

40-Gb/s 2:1 multiplexer and 1:2 demultiplexer in 120-nm standard CMOS

We present an integrated 2:1 multiplexer and a companion 1:2 demultiplexer in CMOS. Both integrated circuits (ICs) operate up to a bit rate of 40 Gb/s. The 2:1 multiplexer features two in-phase data inputs which are achieved by a master-slave flip-flop and a master-slave-master flip-flop. Current-mode logic is used because of the higher speed compared to static CMOS and the robustness against common-mode disturbances. The multiplexer uses no output buffer and directly drives the 50-/spl Omega/ environment. An inductance connected in series to the output in combination with shunt peaking is used to enhance the bandwidth of the multiplexer. Fully symmetric on-chip inductors are used for peaking. The inductors are mutually coupled to save chip area. Lumped equivalent models of both peaking inductors allow optimization of the circuit. The ICs are fabricated in a 120-nm standard CMOS technology and use 1.5-V supply voltage. Measured eye diagrams of both ICs demonstrate their performance.     

1.6 Gb/s/pin 4-PAM signaling and circuits for a multidrop bus

A 1.6 Gb/s/pin 4-pulse-amplitude-modulated (PAM) multidrop signaling system has been designed. The motivation for multi-PAM signaling is discussed. The system uses single-ended+reference current-mode signaling with three dc references for maximum bandwidth per pin. A test chip with six I/O pins was fabricated in 0.35-μm CMOS and tested in a 28-Ω evaluation system using on-chip 2¹⁰ pseudorandom bit sequence (PRBS) generator/checkers. Two different 4-PAM transmitter structures were designed and measured. A high-gain windowed integrating input receiver with wide common-mode range was designed in order to improve signal-to-noise ratio when operating with smaller 4-PAM input levels. Gray coding allowed a folded preamplifier architecture to be used in the LSB input receiver to minimize area and power. In-system margins are measured via system voltage and timing shmoos with a master communicating with two slave devices     

A 10-GHz 8-b multiplexer/demultiplexer chip set for the SONETSTS-192 system

An ultrahigh-speed 8-b multiplexer (MUX) and demultiplexer (DMUX) chip set has been developed for the synchronous optical network (SONET) next-generation optical-fiber communication systems, which will require data bit rates of about 10 Gb/s. These ICs were designed using three novel concepts: a tree-type architecture giving reliable operation, a dynamic divider with a wide operating range, and a 50-Ω on-chip transmission line with high-speed pulse propagation. They were fabricated using a 0.5-μm WN_x-gate GaAs MESFET process. The DMUX and MUX operated at up to 10.4 and 11.4 GHz, respectively, both with an adequate phase margin of more than 230°     

A refreshable analog VLSI neural network chip with 400 neurons and40 K synapses

An on-chip learning neural network LSI circuit that can refresh the analog storage synaptic weights located on a chip is described. The chip integrates 400 neurons and 40000 synapses with a 0.8-μm double-poly double-metal CMOS technology. This device stores learned information by repeating the refresh process at 200-ms intervals