基于分段模型的信源容错译码算法

针对无损信源编码存在误码扩散的问题,建立了以最大后验概率估计为基础的信源序列分段译码模型,设计了基于统计模型的容错译码算法。该算法充分利用了信源编码数据的残留冗余,较好地消除了无损压缩数据对误码的敏感性,为文本压缩数据的容错译码提供了新思路。实验结果表明,该算法具有纠正信源数据中误码的能力,能够显著减少信息损失。     

基于VLC和LDPC的联合信源信道译码

提出了一种基于VLC和LDPC的联合信源信道译码算法。在迭代过程中，利用VLC信源序列中的冗余信息校正LDPC译码的迭代软信息，增强LDPC译码器的纠错性能，并加速LDPC译码迭代收敛。BSC信道的仿真结果证实了该联合信源信道解码算法性能优越。     

利用HMM信源残留冗余的LDPC译码算法

提出一种基于二阶HMM（隐马尔可夫）信源和LDPC的联合信源信道译码算法。在迭代过程中,利用信源序列中的冗余信息校正LDPC译码的迭代软信息,提高LDPC码的纠错性能,加快迭代收敛速度。AWGN信道的仿真结果证实了该联合信源信道解码算法性能优越。     

完全自校验四余度容错系统设计

完全自校验四余度容错系统是由完全自校验电路管理一个传统的四余度容错系统组成,其中完全自校验电路的功能是用来检测冗余模块错误信息和校验电路本身的错误。错误信息指示主要依赖于错误信息输出,它可以用来产生停止信号来阻止错误的传播。校验电路内部错误产生的指示码和冗余模块错误信息无关,但是可以屏蔽冗余模块和完全自校验电路的错误。此系统具有很高的可用性和可维护性。     

软件双冗余容错系统的容错能力和性能分析

双冗余是比较常用的冗余容错设计方法.软件双冗余容错系统通过冗余执行完成相同功能的两个软件副本,并检查它们的结果,根据两者结果是否一致来判断是否出现了错误.建立了软件双冗余容错系统的运行时模型,并引入了软件双冗余容错系统的容错能力的概念.根据该模型分析了单个软件副本的容错能力对软件双冗余容错系统的容错能力和性能的影响.分析结果显示,提高单个软件副本的容错能力不仅能够提高软件双冗余容错系统的容错能力,还能够提高系统的性能.但在极端情况下,双冗余容错系统的容错能力也可能会小于单个软件副本的容错能力.     

1000BASE-T编码技术解析及算法实现

为满足千兆位以太网1000Base-T在5类线双绞线上传输1Gbps数据的要求，对1000BASE-T的编码技术进行了解析，指出了使用扰码的原因和扰码的实现方法，并提出了利用线性反馈移位寄存器LFSR实现PAM5编码的原理，最后给出了实现技术。实践表明，本方案不仅提高了带宽利用率，而且使接收器可以进行错误检测和纠正（通过Viterbi译码），可以补偿损失的抗噪声冗余（去除数据相关性），完全符合802．3ab协议规范。     

基于多重约束的OpenXML复合文档内容源数据区容错定界算法

在高误码率条件下,接收到的OpenXML复合文档往往因数据含错而无法打开,而在文档修复过程中,对信源中每个源文件内容源数据区的定界经常容易出错,针对该问题,提出了一种基于多重约束的OpenXML复合文档内容源数据区容错定界算法。通过对文档协议冗余的分析与归类,将内容源数据区定界问题转化为对起始位置序列的最佳估计问题。在通过适当放宽匹配条件完成粗定界的基础上,利用冗余信息中的约束关系构建代价函数对观测数据进行筛选,有效地剔除“虚警”情况,进而实现对内容源数据区起始位置序列的最佳估计。仿真结果表明,在参数设置合理的情况下,该方法具有较好的容错定界能力。     

支持自适应容错的多处理器实时操作系统

1 引言实时系统的基本特性是任务响应时间的确定性和系统处理任务的高吞吐量。同时,随着实时系统在安全关键领域内越来越广泛的应用,如核电站控制系统、空中交通管制系统、飞行控制系统、病人监护系统、雷达监视系统等,可靠性也逐渐成为实时系统的重要特性。为提高实时系统的可靠性,主要的技术手段包括:避免错误、消除错误、容错和规避错误。在实时系统的运行过程中,容错(fault-tolerant)是最重要的可靠性保障手段。容错指如何保证在出现错误时系统仍能提供正确服务。工程实际中,实时系统在出现错误时,利用冗余资源实现容错操作。     

一种基于列表译码法的改进的安全网络编码

提出一种基于列表译码法的改进的安全网络编码算法,该算法仅在原随机编码体制的基础上对信源和信宿进行了改变,中间节点保持不变.在信源处,该算法向信源信息中加入少量冗余,并利用稀疏矩阵对其进行矩阵变换,从而增强信息在传输过程中的抗窃听能力;在信宿处,用列表译码法对收到的信息进行译码,从而对污染攻击进行检测和排除.信源和信宿之间不需要任何秘密信道.理论分析和仿真结果表明,该算法能够在多项式时间内设计完成,能够抵抗强窃听和污染等安全性攻击,使得原本的随机网络编码以很高的概率达到信息论安全的要求;该算法提高了编码速率,减小了存储空间的占用.     

结合残留冗余信息的Turbo码译码方法

Turbo码有逼近香农极限的优异性能,特别适合用于无线通信链路上的前向纠错编码方案,但是标准Turbo码译码时存在错误平层（error floor）现象,误码率（BER）和误帧率（FER）有待进一步降低。提出了一种结合信源残留冗余信息进行译码的Turbo码（RR-Turbo码）,通过为Turbo码的译码提供更充分的先验信息以进一步降低误码率和误帧率。仿真结果表明,RR-Turbo码比传统Turbo码在高信噪比区可得到2?dB的额外编码增益,有效改善了错误平层现象。     

利用信源残留冗余实现高容错数字分接

正确的数字分接是PDH数字群路信号信息还原的前提。在高误码信道环境下,为实现可靠通信,提出了利用信源残留冗余来实现高容错数字同步分接的改进算法。算法通过挖掘PDH数据最底层的PCM信号中所残留的冗余,根据码速调整对PCM残留冗余的影响,来增强码速恢复的判断依据。实验的仿真结果显示算法较为彻底地解决了群路分接的滑帧问题,在容错性和准确性上比ITU推荐的多数判决法有显著提高,且较低的计算复杂性使其易于用软硬件实现。由于揭示的规律在大容量PDH通信中是普遍存在的,因此提出的算法具有很大的实用性。     

提高T-DMB系统纠错能力的方法

通过对手机电视地面数字多媒体广播（T-DMB）系统外部编码方式的分析,利用TS流中填充字节为固定值的特性,在RS译码前首先检测填充字节区域并预先纠正该区域内的误码;在此基础上,利用解交织前后码元符号间的位置对应关系,对常规纠错RS译码不可译的TS包进行错误位置预测,利用预测结果进行纠错纠删RS译码。实验结果表明,该算法与常规RS码纠错算法相比,能进一步提高系统的纠错能力,改善视音频的播放质量。     

无线上行视频流的跨层容错传输方法

如何通过资源受限的移动通信终端提升无线上行视频流的抗误性能是亟待解决的重要问题。通过不同通信层次的联合调度,提出了一种跨层容错传输方案。移动通信终端的网络层代理首先利用容错包调度为视频流的延时约束帧集合提供重要性分类,随后该终端的链路层代理利用无线链路单元的优先级调度实现选择性重传。在调度延时与传输带宽限制下,跨层容错传输能够将突发错误转移到延时约束帧集合的低优先级视频数据中,从而在突发易错传输环境中实现了无线链路单元粒度的渐进式传输和平稳退化。     

JPEG2000框架下对感兴趣区域多描述图像编码的研究

多描述编码针对不可靠传输信道将信源信号分成多个码流进行传输,解码端通过收到描述中的冗余对丢失信息进行最大限度的恢复。感兴趣区域(ROI,RegionofInterest)编码是新图像编码标准JPEG2000中支持的一项关键技术。这里提出一种对图像在JPEG2000框架下对ROI区域的多描述编码方案,提高了信号传输的鲁棒性,仿真实验结果说明了其有效性。     

Approximate K-Median of Location Streams with Redundancy and Inconsistency

Data streams produced by positioning systems such as Global Positioning System (GPS) or RFID readers can be considered as location streams[12]. Location streams are usually generated in a distributed fashion by a large scale distributed system covering a wide range of areas. Computing on distributed location streams is both practically useful and theoretically challenging. The results of computation could be used to schedule the traffic in a metropolis to avoid traffic jam, dispatch taxis to serve the passengers more quickly and display the current position of goods in supply chain management, etc. Since location streams are usually generated with very high rate in uncertain ways over hostile environments, the collected updates of location are probably redundant and inconsistent in a wide positioning system. To process distributed location streams with redundancy and inconsistency, this paper proposes a novel method based on min-wise hash. With this method, redundant updates of distributed location streams can be effiectively filtered out, while the true location could be derived from inconsistent ones. Consequently, globally uniform samples can be obtained. Based on the uniform samples, an algorithm for computing the approximate k-median of huge number of moving objects is presented in this paper. Furthermore, it is demonstrated that sketch-based methods are not necessarily effiective in processing location streams with redundancy and inconsistency. In addition to theoretical analysis, some extensive experiments are conducted to validate the efficiency and effiectiveness of the proposed approach.     

Analysis and reduction of data spikes in thin client computing

While various optimization techniques have been used in existing thin client systems to reduce network traffic, the screen updates triggered by many user operations will still result in long interactive latencies in many contemporary network environments. Long interactive latencies have an unfavorable effect on users’ perception of graphical interfaces and visual contents. The long latencies arise when data spikes need to be transferred over a network while the available bandwidth is limited. These data spikes are composed of a large amount of screen update data produced in a very short time. In this paper, we propose a model to analyze the packet-level redundancy in screen update streams caused by repainting of graphical objects. Using this model we analyzed the data spikes in screen update streams. Based on the analysis result we designed a hybrid cache-compression scheme. This scheme caches the screen updates in data spikes on both server and client sides, and uses the cached data as history to better compress the recurrent screen updates in possible data spikes. We empirically studied the effectiveness of our cache scheme on some screen updates generated by one of the most bandwidth-efficient thin client system, Microsoft Terminal Service. The experiment results showed that this cache scheme with a cache of 2M bytes can reduce 26.7%–42.2% data spike count and 9.9%–21.2% network traffic for the tested data, and can reduce 25.8%–38.5% noticeable long latencies for different types of applications. This scheme costs only a little additional computation time and the cache size can be negotiated between the client and server.     

Activatable tiles for compact robust programmable molecular assembly and other applications

Algorithmic DNA self-assembly is capable of forming complex patterns and shapes, that have been shown theoretically, and experimentally. Its experimental demonstrations, although improving over recent years, have been limited by significant assembly errors. Since 2003 there have been several designs of error-resilient tile sets but all of these existing error-resilient tile systems assumed directional growth of the tiling assembly. This is a very strong assumption because experiments show that tile self-assembly does not necessarily behave in such a fashion, since they may also grow in the reverse of the intended direction. The assumption of directional growth of the tiling assembly also underlies the growth model in theoretical assembly models such as the TAM. What is needed is a means for enforce this directionality constraint, which will allow us to reduce assembly errors. In this paper we describe a protection/deprotection strategy to strictly enforce the direction of tiling assembly growth so that the assembly process is robust against errors. Initially, we start with (1) a single “activated” tile with output pads that can bind with other tiles, along with (2) a set of “deactivated” tiles, meaning that the tile’s output pads are protected and cannot bind with other tiles. After other tiles bind to a “deactivated” tile’s input pads, the tile transitions to an active state and its output pads are exposed, allowing further growth. When these are activated in a desired order, we can enforce a directional assembly at the same scale as the original one. Such a system can be built with minimal modifications of existing DNA tile nanostructures. We propose a new type of tiles called activatable tiles and its role in compact proofreading. Activatable tiles can be thought of as a particular case of the more recent signal tile assembly model, where signals transmit binding/unbinding instructions across tiles on binding to one or more input sites. We describe abstract and kinetic models of activatable tile assembly and show that the error rate can be decreased significantly with respect to Winfree’s original kinetic tile assembly model without considerable decrease in assembly growth speed. We prove that an activatable tile set is an instance of a compact, error-resilient and self-healing tile-set. We describe a DNA design of activatable tiles and a mechanism of deprotection using DNA polymerization and strand displacement. We also perform detailed stepwise simulations using a DNA Tile simulator Xgrow, and show that the activatable tiles mechanism can reduce error rates in self assembly. We conclude with a brief discussion on some applications of activatable tiles beyond computational tiling, both as (1) a novel system for concentration of molecules, and (2) a catalyst in sequentially triggered chemical reactions.     

基于奇偶校验的三容错数据布局研究

基于单容错编码的数据布局已经不能满足存储系统对可靠性越来越高的要求。对基于多容错编码的数据布局的研究受到了广泛的关注,并且出现了一些三容错的布局算法,如HDD1,HDD2等。但这些布局算法普遍存在冗余度较差、计算负载大等缺点。提出了一种基于三重奇偶校验的多容错数据布局算法TP-RAID(Triple Parity RAID)。该算法只需要在RAID5阵列系统中增加两个校验磁盘,通过水平、正向对角和反向对角三重奇偶校验,可容许同时发生的三个磁盘故障。该算法编码、解码简单,三重校验条纹长度相等,计算负载小,易于实现。此外,由于该算法中尽量减少了三重校验之间逻辑关联,使得该算法的小写性能比其他的三容错算法相比有了大幅度的提高。     

A data embedded video coding scheme for error-prone channels

We propose a novel data embedding scheme for fractional-pixel based video coding algorithms such as H.263 and MPEG-2. By modifying the motion estimation procedure at fractional-pixel precision, two bits data can be embedded in a motion vector (MV) for an inter-mode coded macroblock (MB). For half-pixel precision motion estimation, the resulted bitstream is compatible with the current video coding standards. Performance of the proposed data embedding scheme in terms of compression efficiency is also studied. As an application example of the proposed data embedding scheme, an error-resilient video coding scheme is also presented where some redundant information, which is used to protect MVs and coding modes of MBs in one frame, is embedded into the MVs in the next frame. When errors occur in one group of blocks (GOB), the decoder can exactly recover the MVs of the corrupted GOB if the next frame can be received correctly. Simulations show that the proposed scheme has better performance than standard H.263 coding scheme for transmission over error-prone channels