Positive Bias Temperature Instability Effects in nMOSFETs With $hbox{HfO}_{2}/hbox{TiN}$ Gate Stacks

The Positive Bias Temperature Instability (PBTI) and the stress-induced leakage current (SILC) effects are thoroughly examined in nFETs with $hbox{SiO}_{2}/hbox{HfO}_{2}/hbox{TiN}$ dual-layer gate stacks under a wide range of bias and temperature stress conditions. Experimental evidence of the SILC increase with time is obtained suggesting the activation of a trap generation mechanism. Threshold voltage $(V_{rm T})$ instability is found to be the result of a complicated interplay of two separate mechanisms; filling of preexisting electron traps versus trap generation each one dominating at different stress condition regimes. Furthermore, $V_{rm T}$ instability relaxation experiments, undertaken at judiciously chosen conditions, show that the preexisting and stress-induced traps exhibit similar detrapping kinetics indicating that both types of traps may have similar characteristics. Finally, it is shown that the role of the SILC effect (and the associated trap generation component) on $V_{rm T}$ instability is process dependent and that SILC reduction is accompanied by enhancement of the PBTI device lifetime.      

Stress-induced leakage current (SILC) and oxide breakdown: are theyfrom the same oxide traps?

Many research groups have used stress-induced leakage current SILC as a mean to measure the oxide traps (defects) buildup in the oxide film during electrical stress. It is commonly believed that these very same traps will lead to oxide breakdown when their density reaches a critical value. We studied the annealing kinetic of SILC as well as, the oxide breakdown distribution and found that they are quite different. Our result casts serious doubt on the validity of the popular assumption     

SILC effects on E2PROM memory cell reliability

In this paper, we will investigate SILC effects on the reliability of E²PROM memories. Particularly, we will analyze the influence on the retention properties of E²PROM memory devices of program/erase number of cycles and bias conditions, oxide thickness scaling and quality, and storage field. To accomplish this task, we will use a recently proposed compact E²PROM model, which has been extended to include the stress-induced leakage current (SILC), thus bridging the gap between the oxide quality characterization activity performed on MOS transistors and capacitors, and the actual impact of SILC on the functioning of E²PROM memories     

Junction leakage current degradation under the off-statebias-temperature stress: a new reliability assessment method forhigh-density DRAMs

A new reliability assessment method on retention time failure for high-density DRAMs under off-state bias-temperature (B-T) stress was suggested and investigated using the well-known gated-diode test pattern. The transistor junction leakage current degradation, total junction leakage current especially including gate-induced drain leakage (GIDL) component, under the off-state B-T stress was found to be more sensitive than widely-used gate-oxide degradation under the Fowler-Nordheim (F-N) tunneling stress. The off-state bias stress also gives significantly higher degradation on the gate-oxide stress-induced leakage current (SILC) than F-N tunneling current stress. The features of the off-state B-T stress which gives stress to almost all transistor leakage components and the mechanism of the junction leakage current degradation under the off-state bias condition were discussed     

Electrical and Reliability Studies of “Wet N2O” Tunnel Oxides Grown on Silicon for Flash Memory Applications

In this paper, we report the electrical characteristics and reliability studies on tunnel oxides fabricated by "wet N₂O" oxidation of silicon in an ambient of water vapor and N₂O at a furnace temperature of 800 degC. Tunnel oxides that have an equivalent oxide thickness of 67 A are subjected to a constant-current stress (CCS) amount of -100 mA/cm² using a MOS capacitor to obtain information on stress-induced leakage current (SILC), interface, and bulk trap generation. The obtained results clearly demonstrate the superior performance features of the present tunnel oxides with reduced SILC, lower trap generation, minimum change in gate voltage, and higher charge-to-breakdown during CCS studies. X-ray photoelectron spectroscopy depth profile studies of the tunnel oxide interfaces have shown that the improved performance characteristics and reliability can be attributed to the incorporation of about 8.5% nitrogen at the oxide-silicon interface of the samples formed by the "wet N₂O" process that involves low-temperature oxidation and annealing at 800 degC.     

A simulation framework for modeling charge transport and degradation in high-k stacks

In this paper we present a comprehensive physical model that describes charge transport and degradation phenomena in high-k stacks. The physical mechanisms are modeled using a novel material-related approach that includes in a self-consistent fashion the charge transport (dominated by defect-assisted contribution), power dissipation and temperature increase, defect generation, and ion and vacancy diffusion and recombination. The physical properties of defects, which play a crucial role in determining the electrical behavior of the high-k stacks, depend on their atomistic configurations, as calculated using ab-initio methods. This simulation framework represents a powerful tool to interpret electrical characterization measurements. In addition, it can be used to optimize logic and memory device stacks thanks to its predictive statistical capabilities that allow reproducing gate current, threshold voltage increase and time to breakdown (TDDB) statistics. Simulation results performed using this simulation package are shown to reproduce accurately leakage current, Stress-Induced Leakage Current (SILC), threshold voltage shift observed during Positive Bias Temperature Instability (PBTI) stress, TDDB in various dielectric stacks.     

Temperature Effects on Breakdown Characteristics of High- $kappa$ Gate Dielectrics With Metal Gates

In this paper, the temperature dependence of time-dependent dielectric breakdown (BD) and stress-induced leakage current (SILC) of high-$kappa$ and interfacial layers (ILs) are studied separately and in a gate stack with metal gates as the BD mechanisms of these layers are different at higher temperatures than at room temperature. As observed from the low voltage SILC, the IL initiates the gate stack BD process at elevated temperature, which is followed by the high-$kappa$ layer. Activation energy extracted from Weibulll distribution of time-to-BD $(T_{rm BD})$ data from high- $kappa$ layer further suggests that the gate stack BD occurs when high- $kappa$ layer ultimately breaks down.      

等离子体断路开关工作仿真及特性分析

为了研究有、无外磁场的低密度等离子体断路开关(POS)工作特性,利用单元粒子(PIC)方法模拟了POS中电场和磁场的时空变化、等离子体电子的动力学行为和特性。通过对POS工作过程中的两极间的EMHD运动及其导致的磁场渗透、磁绝缘、动态过程中密度不均匀造成的不规则运动、场畸变等物理现象的分析,研究了POS的断路过程。仿真结果表明:外加时不变均匀角向磁场,提前了电流向负载转移的时刻、减小了电流损失,且未提高负载电流陡度,断路时在负载端得到更高的电压。研究为设计、改进POS结构和提高其断路性能提供了参考依据。     

Collapse of MOSFET drain current after soft breakdown

Gate-oxide soft breakdown (SB) can have a severe impact on MOSFET performance even when not producing any large increase of the gate leakage current. The SB effect on the MOSFET characteristics strongly depends on the channel width W: drain saturation current and MOSFET transconductance dramatically drop in transistors with small W after SB. As W increases, the SB effect on the drain current fades. The drain saturation current and transconductance collapse is due to the formation of an oxide defective region around the SB spot, whose area is much larger than the SB conductive path. Similar degradation can be observed even in heavy ion irradiated MOSFETs where localized damaged oxide regions are generated by the impinging ions without producing any increase of gate leakage current.     

氧化锌压敏陶瓷伏安特性的微观解析

为从微观层面上解析ZnO压敏陶瓷MOV的宏观伏安特性,根据电镜和深能级瞬态谱(DLTS)的观测结果,结合试验实测几种规格MOV小电流和大电流下的试验数据,建立ZnO在小电流区和大电流区的微观集中参数等效电路模型,然后依据晶界势垒、电子陷阱等理论,微观解析了各区的导电特性。结果表明:随着外施电压的增加,电子的穿透能力不断增强,使ZnO在小电流区晶界层的非线性微观等效电阻不断增大,它与纯ZnO晶粒层的线性电阻共同作用使ZnO小电流区伏安特性呈现出3个不同的特性宏观区域即预击穿区、击穿区和回升区;随着外施瞬态冲击大电流幅值的加大,ZnO在大电流区微观等效电感值增加,使ZnO大电流区伏安特性宏观呈现缓慢上升区、快速上升区和迅速上翘区;晶界层厚度的不均匀性和晶界层中电子陷阱密度的差异性宏观表现为等效电阻的非线性变化,晶界层和纯ZnO晶粒层在小电流区和大电流区具有不同的微观作用机理使得ZnO压敏陶瓷在不同电流区呈现出不同的独特宏观伏安特性。     

受端系统负荷对高压直流输电的影响

在仲夏电网极大负荷运行期间，HVDC受端逆变器常有换流不稳定现象出现。该文探讨了地区负荷对逆变器换流容量的影响情况，在负荷幅值和功率因数变化的情况下，短路(换相)电流受到的影响，考虑了线间不对称短路的换相电流状态，提出电容补偿和静止无功补偿器(SVC)可以改善系统短路容量的见解。文中通过实例，从原理上进行了相关计算和仿真，结果表明，地区负载过大，会极大影响系统的短路电流，从而导致直流输电不稳定现象；而采用串联电容补偿或静止无功补偿器不失为一种可选的增大换相电流的方法，但仅增大系统局部的短路容量。     

定子鼠笼式智能多相电机绕组交流损耗研究

针对定子鼠笼式智能多相电机定子绕组受到高频电流引起涡流效应、趋肤效应和邻近效应的问题,重点分析了不同因素对交流损耗的影响。采用有限元软件,建立定子鼠笼式电机模型,分析了绕组上的趋肤效应与邻近效应,探究定子槽型尺寸、导条槽内位置以及导条截面积对于绕组交流损耗的影响规律,对比研究不同极对数、不同材料下的交流损耗情况。研究结果表明：改变定子槽型尺寸、导条截面积以及绕组材料等可以明显降低定子绕组的交流损耗。     

3/2开关接线方式下基于能量制动的抗电流互感器饱和措施

结合一起3/2开关接线方式下,发生区外故障时由于电流互感器(TA)饱和导致差动保护误动作的案例,分析了3/2开关接线方式下TA饱和对比例电流差动保护的影响,得出了基于差动量和制动量比例制动特性的电流差动保护在区外故障出现TA饱和时动作概率会很大的结论。根据在TA线性传变区内差动电流和制动电流能够正确反映区内外故障的思想,提出了基于能量制动的抗TA饱和措施,并且针对3/2开关接线方式下的特殊电气结构,提出了在该接线方式下的一种新的制动能量表达方式,能够对由于区外故障导致的TA饱和进行可靠识别并闭锁差动保护。仿真分析表明,针对3/2接线方式下可能出现的TA饱和现象,提出的抗TA饱和措施能够显著提升电流差动保护的抗TA饱和性能。     

一种新的差动保护动作行为分析方法:分析篇

运用在穿越电流倍数一电流互感器传变率(流出电流比)坐标平面上分析差动保护性能的方法，详细分析了两种新型标积制动判据中各个参数变化时，对判据的抗电流互感器饱和性能和反应内部故障灵敏性的影响。通过这个新的坐标平面，可以有针对性地调节比例制动特性的各个参数，将判据在电流互感器饱和时最易误动的动作点配置电流互感器误差最小的区域。同时尽可能将拒动区配置在系统不可能或很少可能运行的区域，从而最大限度地发挥判据的效能。通过对比分析，明晰了两种判据的优缺点，两种判据在电流互感器饱和时具有同样的安全性，但采用条件动作区的判据在反应轻微内部故障时具有更好的灵敏性和灵活性，略优于采用制动区的判据。     

测量用电流互感器数字补偿算法

为了提高测量用电流互感器（CT）的精度,通常采用高磁导率的材料和大横截面积的核心使励磁电流最小化,这种做法会增加CT的制造成本。提出了一种提高测量用CT精度的数字补偿算法,根据副边电流测量值和铁心磁化特性,通过算法计算并补偿励磁电流来提高测量用CT的精度,仿真和实验验证了该算法的有效性。     

500kV变压器直流偏磁下的铁心损耗分析研究

为了研究变压器直流偏磁下的铁心损耗,文章以某一核电站500 k V主变压器为例,在二维有限元瞬态场A–φ算法基础下构造了直流偏磁下的变压器二维仿真损耗模型。在仿真中,偏磁直流量从0 A增加至30 A,可得到变压器铁心的损耗分布。结果分析可表明:随着偏磁直流量的增加,励磁电流会产生畸变和较大的偶次谐波,并导致铁心局部损耗增大,其中:铁心主柱与上、下铁轭交接区域的损耗值受到直流偏磁的影响最大,铁心水平路径的损耗值相较于垂直路径受直流偏磁的影响较大。     

并联有源电力滤波器双滞环电流控制策略

提出了一种基于最优电压矢量的并联有源电力滤波器双滞环电流控制策略,用于快速控制三相有源电力滤波器的相间误差电流,同时可减少高次谐波、加快响应速度。采用滞环比较器确定参考电压矢量所在的区域,另根据误差电流矢量的越界情况及所在区域采用不同的控制策略来选择输出开关矢量,同时,引入当前开关状态信号和各相电流幅值信号,来辅助开关矢量的选择。仿真结果证明了该方法的有效性和可行性。     

随环境条件变化的输电线路输送容量概率建模研究

充分挖掘线路的输电潜能,提高现有电网的输电效率,是当前研究的一个热点。通常输电线路中静态载流量的计算是在保守的环境下获得,未考虑到实际运行环境。而动态载流量的计算是通过对运行环境的实时监测值,即结合实际环境温度、风速等因素,来确定其传输的极限容量,由此可以提高线路的输电效率。本文通过BP神经网络对某地区的历史气象数据进行分析和预测,由于该方法对气象预测效果较好,故将预测获得的数据作为概率模型的源数据,并提出一种基于电流密度函数的概率建模的动态增容研究方法。通过动态增容方法在某地区的应用分析,表明在迎峰度夏时可适当提高输电线路载流量,且可确保输电线路的供电可靠性。     

Characteristics of the Arc Voltage of a High‐Current Air Arc in a Sealed Chamber

The effect of the arc voltage on various factors of design and control was investigated for high currents in order to develop design guidelines for circuit breakers. In this study, the dependence on such factors, namely, the current, arc length, electrode surface area, and internal pressure of the arc voltage, was evaluated quantitatively. As a result of the evaluations, it was estimated that the arc voltage near the electrode surface rises linearly with the arc current and the power ?0.8 of the surface area, and that the voltage in the arc column rises as the 0.3 power of the pressure increase. We confirmed the validity of the estimated voltage characteristics by comparison with the generated voltage in an actual arc‐extinction chamber. The characteristics of the estimated voltage can provide effective guidelines for the design of arc extinguishing chambers. © 2013 Wiley Periodicals, Inc. Electr Eng Jpn, 186(1): 34–42, 2014; Published online in Wiley Online Library ( wileyonlinelibrary.com ). DOI 10.1002/eej.22487     

Avoiding voltage collapse by fast active power rescheduling

Basic ideas for a method where the active power production is rescheduled in an automatic (fast) way to increase the loadability of the power system during a voltage instability are presented. Active power production is a parameter that is controllable during this instability phase and it may have a positive influence on the system vulnerability to collapse, especially when current limitations of the generators are involved. Depending on the strength of the system, two major objectives can be distinguished: to strengthen a local area from collapsing or to avoid an increase of the voltage depressed area.