Partial scan design of register-transfer level circuits

Register-transfer level designs that are derived from high-level synthesis systems generally consist of functional blocks and registers that are interconnected by multiplexers and buses to maximize resource sharing These multiplexer and bus structures have the unique ability to behave asswitches, i.e., to logically partition the circuit when their control inputs are manipulated in different ways. The presence of switches, the selection of scan registers can be influenced. This leads to an efficient partial scan methodology presented in this paper. Second, switches help set up data transfer paths calledI-paths. By employingI-paths to transport test data, the functional logic in the circuit can be separated from the switching logic for the purpose of test generation. This can lead to a reduction in test generation costs for a partial scan design. Thus the techniques presented in this paper help to minimize both testability overhead and test generation cost in bus-based circuits. This methodology is implemented in the SIESTA system for serial scan design.     

Partial scan and symbolic test at the register-transfer level

This paper presents a partial scan methodology suited for (pipelined) data paths described at the Register-Transfer level. The method is based on feedback elimination by making existing registers scannable or by adding extra transparent scan registers An optimal set (in terms of area cost) of scan registers is selected using an exact branch and bound algorithm. This approach can deal with complex realistic data paths requiring orders of magnitude lower CPU times than gate devel techniques. Furthermore, our symbolic test pattern generation technique can very effectively deal with the delay in the remaining acyclic sequential circuit parts. This symbolic test method makes various scan schemes possible which ensure a correct assembly and application of the test vectors. They are discussed and compared in terms of hardware requirements, test application times and test accuracy.     

Simplified introduction of power intent into a register-transfer level model

Design Automation for Embedded Systems - In highly-integrated electronic circuits designs, power reduction must be properly addressed. The standardized ways of power-intent specification are...     

Leakage reduction through optimization of regular layout parameters

Regular layouts that follow restrictive design rules are essential to robust CMOS design in order to alleviate many manufacturing induced effects, such as the effect of non-rectangular gate (NRG) due to sub-wavelength lithograph. NRG dramatically increases the leakage current by more than 15X compared to that of ideal physical layout. To mitigate such a penalty, we developed a technique to optimize regular layout through restrictive design rule parameters and to benchmark post-lithography circuit performance. We propose a procedure to systematically optimize key layout parameters in regular layout to minimize the leakage energy with minimal over head to active energy, circuit speed and area. The proposed layout optimization technique is demonstrated with a 65 nm technology and projected for 45 nm and 32 nm technology nodes. Experimental results show that more than 70% reduction in leakage can be achieved with area penalty of ～10% and 9–12% overhead on circuit speed and active energy.     

Nonlinear transformations for high level regular array ASIC synthesis

In this paper a new and efficient method is presented for optimizing the mapping ofnonuniform recurrence equations on regular array architectures. The method is based on applyingnonlinear transformations on theindices of the recurrence equations by reindexing groups of operations based on a chosen group communication scheme. The main result of this paper is that the presented method provides a means to map real life high throughput algorithms onto ASIC regular array architectures under real constraints.     

Instruction level power analysis and optimization of software

The increasing popularity of power constrained mobile computers and embedded computing applications drives the need for analyzing and optimizing power in all the components of a system. Software constitutes a major component of today's systems, and its role is projected to grow even further. Thus, an ever increasing portion of the functionality of today's systems is in the form of instructions, as opposed to gates. This motivates the need for analyzing power consumption from the point of view of instructions—something that traditional circuit and gate level power analysis tools are inadequate for. This paper describes an alternative, measurement based instruction level power analysis approach that provides an accurate and practical way of quantifying the power cost of soft-ware. This technique has been applied to three commercial, architecturally different processors. The salient results of these analyses are summarized. Instruction level analysis of a processor helps in the development of models for power consumption of software executing on that processor. The power models for the subject processors are described and interesting observations resulting from the comparison of these models are highlighted. The ability to evaluate software in terms of power consumption makes it feasible to seach fow low power implementations of given programs. In addition, it can guide the development of general tools and techniques for low power software. Several ideas in this regard as motivated by the power analysis of the subject processors are also described.     

Techniques for power estimation and optimization at the logic level: A survey

We present a survey of state-of-the-art power estimation methods and optimization techniques targeting low power VLSI circuits. Estimation and optimizations at the circuit and logic levels are considered.     

内存模组中板级串扰分析与优化

面对系统工作频率的不断提高，信号完整性问题愈发严重，串扰问题是其中的主要问题之一。以服务器及工作站级内存模组为例，通过对内存模组中串扰问题产生原因的分析，借助软件模拟，探讨一种优化内存模组设计中串扰问题的方法。     

气流式水平姿态传感器仿真的优化

利用FLUENT软件,采用功率替代温度的优化方法计算出气流式水平姿态传感器密闭腔体内的温度分布图,分别计算了传感器在不同倾角状态下和不同环境温度下密闭腔体内的温度场分布情况,计算和实验结果表明:气流式水平姿态传感器的两热敏电阻丝的温度差与倾角有很好的线性关系,它们之间的变化率为2.618 3 K/(o);环境温度对传感器的两热敏电阻丝的温度差的影响也是有线性关系的,倾角为24o时它们之间的变化率为–0.135 9K/K,与实验结果有很好的相似度。     

Device and circuit level optimization for high performance a-Si:H TFT-based AMOLED displays

Active matrix organic light-emitting diode (AMOLED) displays with amorphous hydrogenated silicon (a-Si:H) thin-film transistor (TFT) backplanes are becoming the state of art in display technology. Though a-Si:H TFTs suffer from an intrinsic device instability, which inturn leads to an instability in pixel brightness, there have been many pixel driving methods that have been introduced to counter this. However, there are issues with these circuits which limit their applicability in terms of speed and resolution. This paper highlights these issues and provides detailed design considerations for the choice of pixel driver circuits in general. In particular, we discuss the circuit and device level optimization of the pixel driver circuit in a-Si:H TFT AMOLED, displays for high gray scale accuracy, subject to constraints of power consumption, and temporal and spatial resolution.     

On-chip decoupling capacitor optimization using architectural level prediction

Switching activity-generated power-supply grid-noise presents a major obstacle to the reduction of supply voltage in future generation semiconductor technologies. A popular technique to counter this issue involves the usage of decoupling capacitors. This paper presents a novel design technique for sizing and placing on-chip decoupling capacitors based on activity signatures from the microarchitecture. Simulation of a typical processor workload (SPEC95) provides a realistic stimulation of microarchitecture elements that is coupled with a spatial power grid model. Evaluation of the proposed technique on typical microprocessor implementations (the Alpha 21264 and the Pentium II) indicates that this technique can produce up to a 30% improvement in maximum noise levels over a uniform decoupling capacitor placement strategy.     

Architecture level optimization of 3-dimensional tree-based FPGA

We describe a methodology to design and optimize Three-dimensional (3D) Tree-based FPGA by introducing a break-point at particular tree level interconnect to optimize the speed, area, and power consumption. The ability of the design flow to decide a horizontal or vertical network break-point based on design specifications is a defining feature of our design methodology. The vertical partitioning is organized in such a way to balance the placement of logic blocks and switch blocks into multiple tiers while the horizontal partitioning optimizes the interconnect delay by segregating the logic blocks and programmable interconnect resources into multiple tiers to build a 3D stacked Tree-based FPGA. We finally evaluate the effect of Look-Up-Table (LUT) size, cluster size, speed, area and power consumption of the proposed 3D Tree-based FPGA using our home grown experimental flow and show that the horizontal partitioned 3D stacked Tree-based FPGA with LUT and cluster sizes equal to 4 has the best area-delay product to design and manufacture 3D Tree-based FPGA.     

Design and optimization of thermo-mechanical reliability in wafer level packaging

In this paper, a variety of wafer level packaging (WLP) structures, including both fan-in and fan-out WLPs, are investigated for solder joint thermo-mechanical reliability performance, from a structural design point of view. The effects of redistribution layer (RDL), bump structural design/material selection, polymer-cored ball application, and PCB design/material selection are studied. The investigation focuses on four different WLP technologies: standard WLP (ball on I/O WLP), ball on polymer WLP without under bump metallurgy (UBM) layer, ball on polymer WLP with UBM layer, and encapsulated copper post WLP. Ball on I/O WLP, in which solder balls are directly attached to the metal pads on silicon wafer, is used as a benchmark for the analysis. 3-D finite element modeling is performed to investigate the effects of WLP structures, UBM layer, polymer film material properties (in ball on polymer WLP), and encapsulated epoxy material properties (in copper post WLP). Both ball on polymer and copper post WLPs have shown great reliability improvement in thermal cycling. For ball on polymer WLP structures, polymer film between silicon and solder balls creates a ‘cushion’ effect to reduce the stresses in solder joints. Such cushion effect can be achieved either by an extremely compliant film or a ‘hard’ film with a large coefficient of thermal expansion. Encapsulated copper post WLP shows the best thermo-mechanical performance among the four WLP structures. Furthermore, for a fan-out WLP, it has been found that the critical solder balls are the outermost solder balls under die-area, where the maximum thermal mismatch takes place. In a fan-out WLP package, chip size, other than package size, determines the limit of solder joint reliability. This paper also discusses the polymer-cored solder ball applications to enhance thermo-mechanical reliability of solder joints. Finally, both experimental and finite element analysis have demonstrated that making corner balls non-electrically connected can greatly improve the WLP thermo-mechanical reliability.     

On gate level power optimization using dual-supply voltages

In this paper, we present an approach for applying two supply voltages to optimize power in CMOS digital circuits under the timing constraints. Given a technology-mapped network, we first analyze the power/delay model and the timing slack distribution in the network. Then a new strategy is developed for timing-constrained optimization issues by making full use of stacks. Based on this strategy, the power reduction is translated into the polynomial-time-solvable maximal-weighted-independent-set problem on transitive graphs. Since different supply voltages used in the circuit lead to totally different power consumption, we propose a fast heuristic approach to predict the optimum dual-supply voltages by looking at the lower bound of power consumption in the given circuit. To deal with the possible power penalty due to the level converters at the interface of different supply voltages, we use a “constrained F-M” algorithm to minimize the number of level converters. We have implemented our approach under an SIS environment. Experiment shows that the resulting lower bound of power is tight for most circuits and that the predicted “optimum” supply voltages are exactly or very close to the best choice of actual ones. The total power saving of up to 26% (average of about 20%) is achieved without degrading the circuit performance, compared to the average power improvement of about 7% by the gate sizing technique based on a standard cell library. Our technique provides the power-delay tradeoff by specifying different timing constraints in circuits for power optimization     

Probabilistic optimization for FPGA board level routing problems

Field programmable gate arrays (FPGAs) are an enabling technology in circuit designs. We consider the board-level multi-terminal net assignment in the FPGA-based logic emulation. A novel probabilistic optimization method is devised for solving the net assignment problem. The approach incorporates randomized rounding, genetic algorithm, and solution-improvement strategies. Experimental results demonstrate promising performance.     

基于TAO与PETSc的MPI并行编程及应用

文章介绍了TAO和PETSc以及MPI的编程方法，并且通过具体实例就如何在高性能机器上基于TAO进行并行求解最优化问题的编程作了讨论，所给出的程序代码均已在曙光2000Ⅱ上运行成功，并和基于MPI手工编写的并行代码作了比较。     

磨煤机差压料位测量装置改进与优化

耒电#3、#4机组SVEDALA双进双出磨煤机差压料位测量装置改造后,测量准确性差、故障率高,通过分析问题、持续改进后,对取样管路和测量探针以及控制方案进行改造.改造完成后,新的测量系统测量准确,无测量管路堵塞和测量失真等现象,达到提高磨煤机运行安全性和节能降耗的目的.     

A behavioral-based multi-agent optimization algorithm for system level radio design

This paper introduces a multi-agent behavioral-based optimization algorithm for system level radio design. Making multi-standard wireless communication receivers that meet their specs while keeping the requirements of the individual blocks as relaxed as possible is the goal of this algorithm. In order to achieve this goal a “divide and conquer” approach is proposed. Different agents focus on different objectives that are pursued in parallel. Agents adopt different behaviors depending on the status of the environment and their interaction with other agents. Agents are cooperative by default as they try to meet their spec without making changes that affect other agents. However, more aggressive behaviors that lead to global changes can be adopted when needed. The interaction between these simple entities yields an emergent behavior able to deal smoothly with the complexity of the problem at hand.     

基于数据级自动向量化的编译优化研究综述

SIMD扩展部件是一种在多媒体程序和科学计算程序中提供指令并行的加速部件.本文首先介绍SIMD扩展部件的背景及行业现状,然后从挖掘方法、指针别名这2个角度介绍了SIMD现阶段发展情况,在此基础上并对SIMD编译优化方向进行了展望.     

Board level solder joint reliability analysis and optimization of pyramidal stacked die BGA packages

Due to requirements of cost-saving and miniaturization, stacked die BGA has recently gained popularity in many applications. However, its board level solder joint reliability during the thermal cycling test is not as well-studied as common single die BGA. In this paper, solder joint fatigue of wirebond stacked die BGA is analyzed in detail. 3D fatigue model is established for stacked die BGA with considerations of detailed pad design, realistic shape of solder ball, and non-linear material properties. The fatigue model applied is based on a modified Darveaux's approach with non-linear viscoplastic analysis of solder joints. The critical solder ball is observed located between the top and bottom dice corner, and failure interface is along the top solder/pad interface. The modeling predicted fatigue life is first correlated to the thermal cycling test results using modified correlation constants, curve-fitted from in-house TFBGA (thin-profile fine-pitch BGA) thermal cycling test data. Subsequently, design analyses are performed to study the effects of 16 key design variations in package dimensions, material properties, and thermal cycling test conditions. In general, smaller top and bottom dice sizes, thicker top or bottom die, thinner PCB, thicker substrate, higher solder ball standoff, larger solder mask opening size, smaller maximum ball diameter, smaller PCB pad size, smaller thermal cycling temperature range, longer ramp time, and shorter dwell time contribute to longer fatigue life. The effect of number of layers of stacked-die is also investigated. Finally, design optimization is performed based on selected critical design variables.