Modeling and measurement of substrate coupling in Si-bipolar IC'sup to 40 GHz

Parasitic substrate coupling can severely degrade the performance of high-speed ICs and must be considered carefully in circuit design. Therefore, this paper proposes several equivalent circuits that are well suited for modeling substrate coupling up to very high frequencies with standard circuit simulators such as SPICE. Their element values can be calculated for arbitrary layout configurations from numerical simulations (using our SUbstrate SImulator SUSI), which are based on experimentally determined, specific technological/electrical data. The validity of both the simulator and the equivalent circuits has been verified by on-wafer measurements up to 40 GHz, the highest frequency reported so far for modeling of substrate coupling. For this, special test structures were designed and fabricated in an advanced Si-bipolar technology. This work is focused on substrate modeling in very-high-speed rather than in complex ICs     

Solution of PDEs-electrically coupled systems with electrical analogy

This paper presents an approach to solve coupled systems where electrical/mechanical devices, whose behaviour is governed by a PDE or a system of PDEs, are connected together through an electrical circuit. In an earlier paper [1], it had been shown that PDEs can be modeled by an electrical equivalent circuit generated from the complete set of equations arising from the Finite Element Method (FEM). In this paper, the approach is extended to solve a system of PDEs. The approach allows the simulation of coupled systems with circuit simulation tools alone since the resultant system becomes an electrical circuit after an application of electrical analogy. The coupled system is solved by directly replacing PDE devices with the equivalent circuits. Further, a special circuit simulation technique, viz. multiport decomposition is used in order to solve a large coupled system. A sequential as well as a parallel simulator is built for coupled problems based on the proposed approach. A circuit with 100 linear PDE devices (the equivalent circuit contains 8 million nodes) has been simulated using the parallel simulator in less than 1 h. We have achieved a speedup of 5 over the sequential simulator using 8 processors on distributed memory architecture. The characteristic of p–n junction diode (drift–diffusion equation) is analyzed by our circuit simulator to show that the proposed approach can be used to build a circuit-cum-device simulator.     

一种分析模拟电路中互连线的新方法

互连线在高性能模拟集成电路中的影响已变得越来越不可忽视,部分元等效电路法（Partial Element Circuit,PEEC）是一种分析互连线的有效模型,常用方法是再用SPICE等数值模拟软件对PEEC模型进行分析。文中提出的用符号分析法模拟PEEC模型以及其它电路元器件,具有大大降低运算量等优点。基于这一点开发出一套交互式程序,使得包括考虑互连线影响的模拟电路的设计、验证和优化变得更容易、更有效率。     

高压LDMOS I—V特性宏模型的建立

目前LDMOS已经广泛应用于功率集成电路和微波集成电路中,建立LDMOS的SPICE等效电路变得很重要。以往的模型都是将LDMOS分为线性区和饱和区两段来分析,公式复杂而且计算量大。因此在数值模拟的基础上提出了全导通区域的伏安特性方程,建立了LDMOSI-V特性的宏模型。该模型的特点是参数少,易于提取,得到的SPICE等效电路简单,仿真容易收敛。     

用Cauer网络综合技术提取PBG等效电路模型

本文从全波场分析结果出发,提取了PBG单元结构的集总等效有耗电路模型。对每个PBG单元采用时域有限差分（FDTD）方法进行全波分析,然后用Cauer部分分式展开形式和网络综合技术,由全波分析结果提取等效有损电路模型参数,并将提取获得的PBG单元等儿电路模型嵌入HP－ADS软件对整个PBG结构进行SPICE分析,得到的散射参量和全波分析结果比较基本一致,证明了该模型的准确性。这种模型可以嵌入电路分析和设计软件中,用来对应用了PBG结构的无源和有源电路进行优化与设计。     

Physical modeling of GaAs MESFETs in an integrated CAD environment:from device technology to microwave circuit performance

The linkage between a physical device simulator for small- and large-signal characterization and CAD (computer-aided design) tools for both linear and nonlinear circuit analysis and design is considered. Efficient techniques for the physical DC and small-signal analysis of MESFETs are presented. The problem of physical simulation in a circuit environment is discussed, and it is shown how such a simulation makes possible small-signal models accounting for propagation and external parasitics. Efficient solutions for physical large-signal simulation, based on deriving large-signal equivalent circuits from small-signal analyses under different bias conditions, are proposed. The small- and large-signal characterizations allow physical simulation to be performed efficiently in a circuit environment. Examples and results are presented     

Behavioral Fault Modeling and Simulation Using VHDL-AMS to Speed-Up Analog Fault Simulation

One of the main requirements for generating test patterns for analog and mixed-signal circuits is fast fault simulation. Analog fault simulation is much slower than the digital equivalent. This is due to the fact that digital circuit simulators use less complex algorithms compared with transistor-level simulators. Two of the techniques to speed up analog fault simulation are: fault dropping/collapsing, in which faults that have similar circuit responses compared with the fault-free circuit response and/or with another faulty circuit response are considered equivalent; and behavioral/macro modeling, whereby parts of the circuit are modeled at a more abstract level, therefore reducing the complexity and the simulation time. This paper discusses behavioral fault modeling to speed-up fault simulation for analog circuits.     

Numerical TRL calibration technique for parameter extraction of planar integrated discontinuities in a deterministic MoM algorithm

In this letter, a thru-reflect-line (TRL) calibration procedure is applied and integrated with a full-wave method-of-moments (MoM) simulator for the parameter extraction of planar discontinuities and circuits. Three TRL calibration standards are numerically formulated and consistently characterized by the MoM simulator. An equivalent circuit model of a circuit discontinuity of interest can then be extracted by calibrating out the erroneous effect of port discontinuity in the deterministic MoM algorithm. As an example, a microstrip open-end circuit is comparatively studied in terms of its equivalent fringing capacitance, and effectiveness of the proposed technique is verified.     

Fault simulation of linear analog circuits

Research in the areas of analog circuit fault simulation and test generation has not achieved the same degree of success as its digital counterpart owing to the difficulty in modeling the more complex analog behavior. This article presents a novel approach to this problem by mapping the good and faulty circuits to thediscrete Z-domain. An efficient fault simulation is then performed on this discretized circuit for the given input test wave form. This simulator provides an order of magnitude speedup over traditional circuit simulators. An efficient fault simulator and the formulation of analog fault models opens up the ground for analog automatic test generation.     

Extraction of Substrate Resistance in Multifinger Bulk FinFETs Using Shorted Source/Drain Configuration

The substrate resistances of highly scaled bulk FinFETs were extracted by using a new RF equivalent circuit, and this approach was verified by a 3-D device simulator. Small signal model parameters of bulk FinFETs were extracted through proposed equivalent circuit and Y-parameter analysis. Unlike the conventional method, the proposed method showed frequency-independent substrate resistances in highly scaled devices. The extraction of the substrate resistances is investigated with number of finger, device geometry, and bias condition. Our approach was verified up to 50 GHz in devices operating in the saturation region.     

Numerical through-resistor (TR) calibration technique for modeling of microwave integrated circuits

A through-resistor (TR) calibration procedure is proposed for parameter extraction and accurate modeling of planar discontinuities and circuits by using a full-wave technique such as method of moments (MoM). This new scheme allows the effective use of a commercial electromagnetic field simulator in removing inherent numerical noises or errors in simulation, and making the parameter extraction for circuit models. A microstrip open-end and a microstrip gap are studied and effectiveness of this new scheme is verified.     

A switched capacitor circuit simulator: AWEswit

This paper describes the modeling and simulation of switched capacitor circuits in AWEswit. AWEswit is a mixed signal simulator for switched capacitor circuits. It allows for portions of the circuit to be modeled with digital blocks controlled by an event queue. The remainder of the circuit is modeled in the analog domain. The paper describes the circuit formulations employed by AWEswit, and how they are exploited in modeling the nonidealities associated with switched capacitor circuits. AWEswit employs asymptotic waveform evaluation (AWE) as its core simulation engine. It combines circuit formulations in the charge-voltage and current-voltage regimes. This flexibility in the circuit formulations means that if the circuit is modeled entirely with ideal switches (i.e. no resistors), then it is automatically solved in the charge-voltage regime (like SWITCAP2). However, if portions of the circuit need to be solved in the current-voltage regime, then AWEswit automatically partitions the circuit and solves the different partitions in whichever regime is appropriate, i.e., in the current-voltage regime (using AWE to evaluate circuit response) or in the charge-voltage regime. AWEswit naturally handles the bandwidth limitations associated with switched capacitor circuits. In addition, it models the clock feedthrough and signal-dependent charge dump that characterize MOSFET switches. The simulator is illustrated by example     

Modeling MOS VLSI circuits for transient analysis

Modeling plays a significant role in the efficient simulation of VLSI circuits. By simplifying the models used to analyze these circuits, it is possible to perform transient analyses with reasonable accuracy at speeds of one or two orders of magnitude faster than in conventional circuit simulation programs. The author discusses the models that are used in the second-generation MOTIS timing simulator. The methods used have been applied to a wide variety of MOS digital integrated circuits. All MOS transistors are modeled as voltage-controlled current sources using multidimensional tables. The actual currents are computed by approximation using variation-diminishing tensor splines. Nonlinear device capacitances in the circuit are approximated using linear models which are derived from experimental simulations using a circuit simulator. At the subcircuit level, special structures in the circuit are identified automatically by a preprocessor and are modeled using macro-models. Driver-load MOS transistor gates and bootstrapped circuits are examples of these structures. Their modeling is achieved by an experimental process before implementation in the preprocessor. The simplifications in the device and circuit models presented here have provided a significant improvement in the speed of transient analysis for large MOS digital circuits with relatively little loss in accuracy. This has resulted in a viable design verification environment using MOTIS.     

A two-dimensional transmission line matrix microwave fieldsimulator using new concepts and procedures

A two-dimensional field simulator for microwave circuit modeling is described. It incorporates a number of recently developed concepts and advanced transmission line matrix (TLM) procedures. In particular, a discrete Green's function concept based on P.B. John's and K. Akhlarzad's time-domain diakoptics is realized, providing a high level of processing power through modularization of large structures at the field level, simulation of wideband matched loads or absorbing walls, modeling of frequency-dispersive boundaries in the time domain, and large-scale numerical preprocessing of passive structures. Nonlinear field modeling concepts are also implemented in the TLM field simulator. It can analyze two-dimensional circuits of arbitrary geometry containing both linear and nonlinear media. The circuit topology is input graphically. Both time-domain and frequency-domain responses can be computed and displayed. The capabilities and limitations of the simulator are discussed, and several microstrip and waveguide components are modeled to demonstrate its important features     

Monte Carlo harmonic-balance and drift-diffusion harmonic-balanceanalyses of 100-600 GHz Schottky barrier varactor frequency multipliers

To date, high frequency multipliers have been designed and analyzed using harmonic-balance codes incorporating equivalent circuit models for the diodes. These codes, however, are unable to accurately predict circuit performance at frequencies above 100 GHz and do not allow a means for studying the physics of electron transport. In order to analyze these high frequency Schottky doublers, a novel harmonic-balance technique has been integrated into a drift-diffusion numerical simulator and, for the first time, a Monte Carlo numerical device simulator. The unification of the numerical device simulator with the harmonic-balance algorithm allows for the self-consistent study of electron transport phenomena as well as the study of device performance in a given circuit. These combined simulators are tested against experimental data and an equivalent circuit model harmonic-balance approach, and yield superior accuracy with respect to the experimental data     

Electro-thermal circuit simulation using simulator coupling

The paper presents a methodology for simulating the static and dynamic performance of integrated circuits in the presence of electro-thermal interactions on the integrated circuit die. The technique is based on the coupling of a finite element method (FEM) program with a circuit simulator. In contrast to other known simulator couplings a time step algorithm is used, Its implementation in simulation tools is described. The thermal modeling of the die/package structure and the extended modeling of the electronic circuit is discussed. Simulation results which indicate the capabilities of the methodology for electro-thermal simulation are compared to experimental results     

Drain current model for undoped Gate Stack Double Gate (GSDG) MOSFETs including the hot-carrier degradation effects

In this paper, analytical models of drain current and small signal parameters for undoped symmetric Gate Stack Double Gate (GSDG) MOSFETs including the interfacial hot-carrier degradation effects are presented. The models are used to study the device behavior with the interfacial traps densities. The proposed model has been implemented in the SPICE circuit simulator and the capabilities of the model have been explored by circuit simulation example. The developed approaches are verified and validated by the good agreement found with the 2D numerical simulations for wide range of device parameters and bias conditions. GSDG MOSFET design and the accurate proposed model can alleviate the critical problem and further improve the immunity of hot-carrier effects of DG MOSFET-based circuits after hot-carrier damage.     

Design and simulation of a nanoelectronic single electron 2-4 decoder using a novel simulator

The design and simulation of a single-electron 2-4 decoder using a novel single electron circuit simulation tool named single-electron circuit simulator (SECS), is presented in this paper. In single electron circuits bits of information are represented by the presence or absence of single electrons at conducting or semiconducting islands. SECS utilizes the Monte Carlo method and the change in free-energy of the whole circuit determines the tunnel rates of possible tunnel events, providing thus a real time simulation of any arbitrary single-electron circuit. Furthermore, SECS is using the SPICE interface for schematic capture. SPICE models of single-electron circuit structures have been developed and, therefore, SECS can also be used for the design and simulation of hybrid microelectronic—single-electron circuits.     

An Experimental Study on High-Frequency Substrate Noise Isolation in BiCMOS Technology

In this letter, four substrate noise isolation structures in standard 0.18-mum SiGe bipolar CMOS technology were investigated using S-parameter measurements. The experimental and simulated results on different isolation structures, such as triple-well p-n junction isolated walls, deep trench isolation, and double P⁺ guard-ring structures, are presented. Each element in the equivalent circuits has been calculated or fitted based on the parasitic resistance, capacitance, and physical dimensions using the device simulator MEDICI and the measured results of the test patterns. The proposed structure B significantly reduced substrate noise below -70 dB up to 20 GHz. The proposed structure C with an extra triple-well junction achieved the best isolation at the lower frequency range, in which |S₂₁| was less than -71 dB from 50 MHz to 10.05 GHz, and -56 dB from 10.05 to 20.05 GHz. The measured results showed an excellent agreement with the calculations. Structure B is good enough and is recommended for a general-purpose RF circuit design, whereas structure C can be used in a highly sensitive RF circuit block below 10 GHz.     

A novel CMOS charge-pump circuit with current mode control 110 mA at 2.7 V for telecommunication systems

This paper presents a novel organization of switch capacitor charge pump circuits based on voltage doubler structures. Each voltage doubler takes a DC input and outputs a doubled DC voltage. By cascading voltage doublers the output voltage increases up to 2 times. A two-phase voltage doubler and a multiphase voltage doubler structures are discussed and design considerations are presented. A simulator working in the Q-V realm was used for simplified circuit level simulation. In order to evaluate the power delivered by a charge pump, a resistive load is attached to the output of the charge pump and an equivalent capacitance is evaluated. To avoid the short circuit during switching, a clock pair generator is used to achieve multi-phase non-overlapping clock pairs. This paper also identifies optimum loading conditions for different configurations of the charge pumps. The proposed charge-pump circuit is designed and simulated by SPICE with TSMC 0.35-μm CMOS technology and operates with a 2.7 to 3.6 V supply voltage. It has an area of 0.4 mm2; it was designed with a frequency regulation of 1 MHz and internal current mode to reduce power consumption.