Inductance model and analysis methodology for high-speed on-chip interconnect

With operating frequencies entering the multi-gigahertz range, inductance has become an important consideration in the design and analysis of on-chip interconnects. In this paper, we present an accurate and efficient inductance modeling and analysis methodology for high-performance interconnect. We determine the critical elements for a PEEC based model by analyzing the current flow in the power grid and signal interconnect. The proposed model includes distributed interconnect resistance, inductance and capacitance, device decoupling capacitances, quiescent switching currents in the grid, pad connections, and pad/package inductance. We propose an efficient methodology for extracting these elements, using statistical models for on-chip decoupling capacitance and switching currents. Simulation results show the importance of various elements for accurate inductance analysis. We also demonstrate the accuracy of the proposed model compared to the traditional loop-based inductance approach. Since the proposed model can consist of hundreds of thousands of RLC elements, and a fully dense mutual inductance matrix, we propose a number of acceleration techniques that enable efficient analysis of large interconnect structures.     

Measurement and modeling of on-chip transmission line effects in a400 MHz microprocessor

On-chip interconnect delays are becoming an increasingly important factor for high-performance microprocessors. Consequently, critical on-chip wiring must be carefully optimized to reduce and control interconnect delays, and accurate interconnect modeling has become more important. This paper shows the importance of including transmission line effects in interconnect modeling of the on-chip clock distribution of a 400 MHz CMOS microprocessor. Measurements of clock waveforms on the microprocessor showing 30 ps skew were made using an electron beam prober. Waveforms from a test chip are also shown to demonstrate the importance of transmission line effects     

Wafer-level package interconnect options

As integrated circuit technology enters the nanometer era, global interconnects are becoming a bottleneck for overall chip performance. In this paper, we show that wafer-level package interconnects are an effective alternative to conventional on-chip global wires. These interconnects behave as LC transmission lines and can be exploited for their near speed of light transmission and low attenuation characteristics. We compare performance measures such as bandwidth, bandwidth density, latency, and power consumption of the package-level transmission lines with conventional on-chip global interconnects for different International Technology Roadmap for Semiconductors (ITRS) technology nodes. Based on these results, we show that package-level interconnects are well suited for power demanding low-latency applications. We also analyze different interconnect options such as memory buses, long inter tile interconnects, clock, and power distribution.     

Inductive properties of high-performance power distribution grids

The design of high integrity, area efficient power distribution grids has become of practical importance as the portion of on-chip interconnect resources dedicated to power distribution networks in high performance integrated circuits has greatly increased. The inductive characteristics of several types of gridded power distribution networks are described in this paper. The inductance extraction program FastHenry is used to evaluate the inductive properties of grid structured interconnect. In power distribution grids with alternating power and ground lines, the inductance is shown to vary linearly with grid length and inversely linearly with the number of lines in the grid. The inductance is also relatively constant with frequency in these grid structures. These properties permit the efficient estimation of the inductive characteristics of power distribution grids. To optimize the process of allocating on-chip metal resources, inductance/area/resistance tradeoffs in high speed performance distribution grids are explored. Two tradeoff scenarios in power grids with alternating power and ground lines are considered.     

Decreased Effectiveness of On-Chip Decoupling Capacitance in High-Frequency Operation

This paper shows the decreased effectiveness of on-chip decoupling capacitance in high-frequency operation. On-chip decoupling capacitance is often used to decrease the variation of the propagation delay caused by power/ground noise, i.e., dynamic IR-drop and/or delta-I noise. However, it is shown in this paper that decoupling capacitance is only effective for coping with dynamic IR-drop if the recharging time between switching events is sufficient. In other words, the effectiveness of decoupling capacitance for dynamic IR-drop in high-frequency operation is less than that of a fully-charged decoupling capacitor. The recharging time and the effectiveness of a decoupling capacitor depend on the propagation delay of the average circuit path which is used to determine the total switching current of a given macro/chip and clock cycle time. If the propagation delay of the critical paths is approximately equal to that of the average circuit path, then it is shown in this paper that adding decoupling capacitance never improves the maximum frequency of the system due to dynamic IR-drop limitations. On the other hand, if the propagation delay of the critical paths is larger than that of the average circuit path, then the maximum frequency is improved by adding decoupling capacitance. In both cases, a new metric, called the apparent capacitance, can be used to help make correct decisions about decoupling capacitance planning.     

A Micromachined Chip-to-Board Interconnect System Using Electroplating Bonding Technology

We demonstrate a micromachined flexible chip-to-board chip interconnect structure for a chip scale package. Micromachined flexible interconnects enable robust operation in high thermal cycling environments, even for high pinout chips due to the flexible interconnect ability to absorb thermal expansion strain. The interconnects on the chip-side and printed wiring board (PWB)-side are united by electroplating bonding technology, a direct bonding technology resulting in solder-free, underfill-free, low temperature joining by means of copper (Cu) electroplating. Over 200 surface micromachined interconnects, which have a thermal relief geometry, are radially arranged on 11 cm substrates. A chip surrogate consisting of glass with integrated platinum (Pt) microheaters mimics a real electronic device under varying thermal loads. The integrated microheaters can simultaneously test mechanical and electrical performance of the interconnects by generation of on-chip temperatures up to 150 C. Lateral and vertical displacement of the interconnects in the thermal environment are measured and simulated. A mechanical reliability test of the chip scale package is successfully performed for 5000 cycles with thermal cycles of 5 min between 40 C to 147 C. No failures were observed during this period.     

Polylithic Integration of Electrical and Optical Interconnect Technologies for Gigascale Fiber-to-the-Chip Communication

Polylithic integration of electrical and optical interconnect technologies is presented as a solution for merging silicon CMOS and compound semiconductor optoelectronics. In contrast to monolithic and hybrid integration technologies, polylithic integration allows for the elimination of optoelectronic and integrated optic device-related processing from silicon CMOS manufacturing. Printed wiring board-level and compound semiconductor chip-level waveguides terminated with volume grating couplers facilitate bidirectional optical communication, where fiber-to-board and board-to-chip optical coupling occurs through a two-grating (or grating-to-grating) coupling path. A 27% increase in the electrical signal I/O projected by and 33% increase in the number of substrate-level electrical signal interconnect layers implied by the International Technology Roadmap for Semiconductors (ITRS) projections for the 32-nm technology generation are required to facilitate 10 Tb/s aggregate bidirectional fiber-to-the-chip communication. Buried air-gap channels provide for the routing of chip or board-level encapsulated air-clad waveguides for minimum crosstalk and maximum interconnect density. Optical signals routed on-board communicate with on-chip volume grating couplers embedded as part of a wafer-level batch package technology exhibiting compatible electrical and optical input/output interconnects. Measurements of grating-to-grating coupling reveal 31% coupling efficiency between two slab, nonoptimized, nonfocusing volume grating couplers.     

Advanced Packaging: The Redistributed Chip Package

The redistributed chip package (RCP) is a substrate-less embedded chip package that offers a low-cost, high performance, integrated alternative to current wirebond ball grid array (BGA) and flip chip BGA packaging. Devices are encapsulated into panels while routing of signals, power, and ground is built directly on the panel. The RCP panel and signal build up lowers the cost of the package by eliminating wafer bumping and substrates thereby enabling large scale assembly in panel form. The build up provides better routing capabilities and better integration. Also, by eliminating bumping, the device interconnect is inherently Pb-free, and the stress of the package is reduced enabling ultra-low-k device compatibility. The panel is created by attaching the device active side down to a substrate, encapsulating and curing the devices, grinding to desired thickness, and then removing the substrate. Signal, power, and ground planes are created using redistribution-like processing. Multilayer metal RCP packages have passed 40 to 125 C air-to-air thermal cycling and HAST after MSL3/260 preconditioning.     

Predictions of CMOS compatible on-chip optical interconnect

Interconnect has become a primary bottleneck in the integrated circuit design process. As CMOS technology is scaled, the design requirements of delay, power, bandwidth, and noise due to the on-chip interconnects have become more stringent. New design challenges are continuously emerging, such as delay uncertainty induced by process and environmental variations. It has become increasingly difficult for conventional copper interconnect to satisfy these design requirements. On-chip optical interconnect has been considered as a potential substitute for electrical interconnect. In this paper, predictions of the performance of CMOS compatible optical devices are made based on current state-of-the-art optical technologies. Electrical and optical interconnects are compared for various design criteria based on these predictions. The critical dimensions beyond which optical interconnect becomes advantageous over electrical interconnect are shown to be approximately one-tenth of the chip edge length at the 22 nm technology node.     

Fully Integrated AC Coupled Interconnect Using Buried Bumps

Presented is the complete demonstration of an assembled system using AC coupled interconnect (ACCI) and buried solder bumps. In this system, noncontacting input/output (I/O) are created by using half-capacitor plates on both a chip and a substrate, while buried solder bumps are used to provide power/ground distribution and physical alignment of the coupling plates. ACCI using buried bumps is a technology that provides a manufacturable solution for noncontacting I/O signaling by integrating high-density, low inductance power/ground distribution with high-density, high-speed I/O. The demonstration system shows two channels operating simultaneously at 2.5 Gb/s/channel with a bit error rate less than 10^-12, across 5.6 cm of transmission line on a multichip module (MCM). Simple transceiver circuits were designed and fabricated in a 0.35 -mum complementary metal-oxide-semiconductor (CMOS) technology, and for PRBS-127 data at 2.5 Gb/s transmit and receive circuits consumed 10.3 mW and 15.0 mW, respectively. This work illustrates the increasing importance of chip and package co-design for high-performance systems.     

Electromigration assessment for power grid networks considering temperature and thermal stress effects

With technology scaling, reliability has emerged as a major design constraint for very-large-scale integrated circuits. Many prior works have investigated electromigration (EM) on full-chip power grid interconnects. However, most of the published results were obtained under the assumption of uniformly distributed temperature and/or residual stress across interconnects. In this paper, we demonstrate the implementation of novel methodology and flow for full-chip EM assessment on the multi-layered power grid networks of a 32 nm test-chip and investigate the impacts of the within-die temperature and thermal stress variations on the failure rate. The proposed approach is based on recently developed physics-based EM models and the EM-induced IR-drop degradation criterion that replaces the traditional conservative weakest segment method. The cross-layout temperature distribution caused by power dissipations in devices and by interconnect Joule heating has been characterized and taken into account in the full-chip EM assessment methodology. Results of the simulations performed on the analyzed multi-layered power/ground nets show that traditional assumption of the uniform average temperature leads to inaccurate predictions of the time-to-failure. Furthermore, the consideration of thermal stress variation results in a retarded EM induced degradation.     

Evaluating the effects of temperature gradients and currents nonuniformity in on-chip interconnects

The paper provides a compact but accurate electro-thermal model of a long wiring on-chip interconnect embedded in the complex layout of a ULSI digital circuit. The proposed technique takes into account both the effect of temperature gradients over the chip substrate and the interconnect self-heating due to current flow. The proposed compact model is well suited to be interfaced with commercially available CAD tools employed for interconnect parasitic extraction and signal integrity verification. The paper also investigates the electro-thermal effects that arise in a long wiring on-chip interconnect in which current flow is dominated by displacement currents and thus is not uniform along the line.     

On-chip inductance cons and pros

Provides a high level survey of the increasing effects of on-chip inductance. These effects are classified into desirable and nondesirable effects. Among the undesirable effects of on-chip inductance are higher interconnect coupling noise and substrate coupling, challenges for accurate extraction, the required modifications of the infrastructure of CAD tools, and the inevitably slower CAD tools as compared to RC-based tools. Among the desirable effects is lower power consumption, less need for repeaters, faster signal rise time, and less delay uncertainty. The viability of design methodologies considering on-chip inductance is briefly discussed.     

Planar clock routing for high performance chip and packageco-design

A new concept of chip and package co-design for the clock network is presented in this paper. We propose a two level clock distribution scheme which partitions the clock network into two levels. First, the clock terminals are partitioned into a set of clusters. For each cluster, a local on-chip clock tree is used to distribute the clock signal from a locally inserted buffer to terminals inside this cluster. The clock signal is then distributed from the main clock driver to each of local buffers by means of a global clock tree, which is a planar tree with equal path lengths. With the flip chip area I/O attachment, the planar global clock tree can be put on a dedicated package layer. The interconnect on the package layer has two to four order smaller resistance than that on the chip layer. The main contribution of this paper is a novel algorithm to construct a planar clock tree with equal path lengths-the length of the path from the clock source to each destination is exactly the same. In addition, the path length from the source to destinations is minimized     

Compact distributed RLC interconnect models. I. Single linetransient, time delay, and overshoot expressions

Novel compact expressions that describe the transient response of a high-speed distributed resistance, inductance, and capacitance (RLC) interconnect are rigorously derived with on-chip global interconnect boundary conditions. Simplified expressions enable physical insight and accurate estimation of transient response, time delay, and overshoot for high-speed global interconnects with the inclusion of inductance     

Scaling trends of on-chip power distribution noise

The design of power distribution networks in high-performance integrated circuits has become significantly more challenging with recent advances in process technologies. As on-chip currents exceed tens of amperes and circuit clock periods are reduced well below a nanosecond, the signal integrity of on-chip power supply has become a primary concern in the integrated circuit design. The scaling behavior of the inductive and resistance voltage drops across the on-chip power distribution networks is the subject of this paper. The existing work on power distribution noise scaling is reviewed and extended to include the scaling behavior of the inductance of the on-chip global power distribution networks in high-performance flip-chip packaged integrated circuits. As the dimensions of the on-chip devices are scaled by S, where S>1, the resistive voltage drop across the power grids remains constant and the inductive voltage drop increases by S, if the metal thickness is maintained constant. Consequently, the signal-to-noise ratio decreases by S in the case of resistive noise and by S/sup 2/ in the case of inductive noise. As compared to the constant metal thickness scenario, ideal interconnect scaling of the global power grid mitigates the unfavorable scaling of the inductive noise but exacerbates the scaling of resistive noise by a factor of S. On-chip inductive noise will, therefore, become of greater significance with technology scaling. Careful tradeoffs between the resistance and inductance of the power distribution networks will be necessary in nanometer technologies to achieve minimum power supply noise.     

Future challenges in electronics packaging

Packaging solutions for the future are much more complex than our current technologies and still must meet the 5% cost/pin reduction per year. The scaleable area array chip-to-package interconnect provides the required I/O count for the small chip size needed by hand-held products. It also provides the large I/O count needed by cost-performance and high-performance products at an acceptable chip size, and it brings power supply current to the interior of the chip. Package designers face many challenges for high-frequency applications, such as inductance of the interconnects, characteristic impedance of the signal lines on the packages, cross-talk noise between these lines, and placement of decoupling capacitances on the chip, in the package, and on the PCB. Thermal management for the ever-increasing future chip power in a limited space inside a system also presents a demanding challenge. These challenges will require significant R&D focus on understanding the mechanics, thermal behavior, and electrical performance of the new materials, as well as the software tools to design and to model these new configurations. Experimental test vehicles will be needed to validate the models and to confirm the reliability of these constructs. Cooperation among industry, universities, and government on research and development is essential to meet the NTRS needs     

A 16-kbit Block Addressed Charge-Coupled Memory Device

This paper describes the design and performance of a 16-kbit charge-coupled serial memory device. The memory is organized in four blocks of 4 kbits each with on-chip decoding and is mounted in a 16-pin ceramic dual-in-line hermetic package. Each 4-kbit block is organized as a serial-parallel-serial (SPS) array. Operated at a data rate of 1 MHz the mean access time is 2 ms and the on-chip power dissipation is calculated to be 1.5 /spl mu/W/bit with another 0.5 /spl mu/W/bit being required in off-chip clock drivers. The maximum designed output data rate is 10 MHz. Compared to the serpentine and loop organized memory charge-coupled device (CCD), the SPS organization has the advantages of lower power dissipation, greater tolerance to process parameter variations, and higher output data rate. All inputs and outputs are TTL compatible. Write/recirculate control is provided on the chip as well as two-dimensional decoding to permit memory matrix organization with X, Y chip select control. All the on-chip peripheral circuits use dynamic MOS circuitry to minimize power consumption. The charge sensing on the chip is achieved with balanced regenerative sense amplifiers. The memory array uses the three-phase three-level polysilicon electrode structure, and the chip is fabricated using an MOS n-channel polysilicon gate process with self-aligned source, drain, and channel stop.     

Early experience with in situ chip-to-chip alignment characterization of Proximity Communication flip-chip package

Proximity Communication (PxC) facilitates the integration of VLSI chips in a package using near-field capacitive coupling between chips, eliminating the need for solder or wires for I/O at the chip-to-chip interface. PxC provides chip-to-chip interconnect with bandwidth density and energy per bit similar to on-chip I/O, enabling system on a chip performance within a package. We have built early packages to explore assembly concepts and developed test methods for verification of the PxC design space. This package started with an adhesively-bonded three-chip subassembly of two Island chips and one Bridge chip. The two outer Island chips were reflowed to an alumina ceramic substrate. In the resulting package, communication between chips was achieved using PxC from Island to Bridge and then from the Bridge to the other Island. We demonstrated the ability to detect the X, Y, and Z chip-to-chip relative location and the ability to steer PxC data to optimize signal integrity within the package. This paper describes the first demonstration of active monitoring of chip-to-chip alignment during thermal cycling, in a PxC-enabled package. Leveraging this work, future packages will better exploit PxC benefits such as free-space electrical interconnect and re-workability of multi-chip modules.     

基于电源、地桥的电源网络布线后优化

随着集成电路规模的不断增大,电源网络的重要性日趋显著,电源网络的分布直接影响芯片的电压降(IR-drop)。一种布线后通过在空闲处插入电源桥和地桥的方法,可以在不增加芯片面积的情况下,改善IR-drop效应。实验结果表明在芯片布局利用率不高的情况下(70~75%),该方法可以使IR-drop得到明显的优化。