Compact physical models for multilevel interconnect crosstalk in gigascale integration (GSI)

For the first time, compact physical models are derived for crosstalk noise of coplanar resistance-inductance-capacitance lines in a gigascale integration (GSI) chip that simultaneously consider far and near aggressors in both the same metal level and distant metal levels. Since both the amplitude and duration of noise are important, the noise voltage-time integral can be defined as a figure-of-merit for crosstalk, and it is shown that this integral attains its maximum at the length at which the interconnect resistance becomes equal to twice the characteristic impedance. It is also shown that crosstalk can be prohibitively large if interconnects have small resistances. There is, therefore, a tradeoff between interconnect latency and crosstalk. The compact models are finally used to calculate the crosstalk noise voltage for the case that wire width is optimized by simultaneously maximizing data flux density and minimizing latency. It has been proven that by utilizing the optimal wire width for signal interconnects and twice of that for power and ground lines, the worst case peak crosstalk noise voltage becomes smaller than 0.25 V/sub dd/ for all generations of technology.     

Sea of Leads (SoL) ultrahigh density wafer-level chip input/output interconnections for gigascale integration (GSI)

Sea of Leads (SoL) is an ultrahigh density (>10/sup 4//cm/sup 2/) compliant chip input/output (I/O) interconnection technology. SoL is fabricated at the wafer level to extend the economic benefits of semiconductor front-end and back-end wafer-level batch fabrication to include chip I/O interconnections, packaging, and wafer-level testing and burn-in. This paper discusses the fabrication, the mechanical and electrical performance, and the benefits of SoL. SoL can lead to enhancements in reliability, electrical performance, manufacturing throughput, and cost. A chip with 12 /spl times/ 10/sup 3//cm/sup 2/ compliant I/O leads is demonstrated. The mechanically compliant I/O leads are designed to enable wafer-level testing and eliminate the need for underfill between chips and printed wiring boards by mitigating thermo-mechanical expansion mismatches between the two. The fabrication of partially nonadherent, or slippery, leads is desirable as it allows the leads to freely undergo strain during thermal cycling. Compared to adherent metal leads, preliminary results show that slippery leads enhance the overall in-plane compliance. Microindentation experiments show that a polymer film with embedded air gaps provides substantially higher compliance than a polymer film without embedded air gaps.     

Wave-pipelined multiplexed (WPM) routing for gigascale integration (GSI)

In modern-day VLSI systems, performance and manufacturing costs are being driven by the on-chip wiring needs due to the continuous increase in the number of transistors. This paper proposes a low overhead wave-pipelined multiplexed (WPM) routing technique that harnesses the inherent intraclock period interconnect idleness to implement wire sharing throughout the various hierarchical levels of design. It is illustrated in this paper that the WPM network can be readily incorporated into future gigascale integration (GSI) systems to reduce the number of interconnect routing channels in an attempt to contain escalating manufacturing costs. Both, a system level analysis and circuit level verification of this WPM routing are presented in this paper. A multilevel interconnect network design simulator (MINDS) that uses system level interconnect prediction (SLIP) techniques and HSPICE circuit simulations for optimizing the interconnect dimensions has been used to assess the opportunities for application of WPM wire circuits in high performance digital designs. A custom routing example highlights the ease with which the WPM routing technique can be easily incorporated into the existing VLSI systems. In addition, for a 40 million transistor system case study, this system level analysis reveals that the use of a WPM network could result in an almost 20% decrease in the number of metal layers for less than 4% increase in dynamic power with no loss of communication throughput performance. The key virtues of WPM routing are its flexibility, robustness, implementation simplicity and its low overhead requirements.     

Performance comparison between carbon nanotube and copper interconnects for gigascale integration (GSI)

Physical models are used to determine the ultimate potential performance of carbon nanotube interconnects and compare them with minimum-size copper wires implemented at various technology generations. Results offer important guidance regarding the nature of carbon nanotube technology development needed for improving interconnect performance. Since wave propagation is slow in a single nanotube, nanotube bundles with larger wave speeds must be used. At the 45-nm node (year 2010), the performance enhancement that can be achieved by using nanotube bundles is negligible, and at the 22-nm node (year 2016) it can be as large as 80%.     

Interconnect limits on gigascale integration (GSI) in the 21stcentury

Twenty-first century opportunities for GSI will be governed in part by a hierarchy of physical limits on interconnects whose levels are codified as fundamental, material, device, circuit, and system. Fundamental limits are derived from the basic axioms of electromagnetic, communication, and thermodynamic theories, which immutably restrict interconnect performance, energy dissipation, and noise reduction. At the material level, the conductor resistivity increases substantially in sub-50-nm technology due to scattering mechanisms that are controlled by quantum mechanical phenomena and structural/morphological effects. At the device and circuit level, interconnect scaling significantly increases interconnect crosstalk and latency. Reverse scaling of global interconnects causes inductance to influence on-chip interconnect transients such that even with ideal return paths, mutual inductance increases crosstalk by up to 60% over that predicted by conventional RC models. At the system level, the number of metal levels explodes for highly connected 2-D logic megacells that double in size every two years such that by 2014 the number is significantly larger than ITRS projections. This result emphasizes that changes in design, technology, and architecture are needed to cope with the onslaught of wiring demands. One potential solution is 3-D integration of transistors, which is expected to significantly improve interconnect performance. Increasing the number of active layers, including the use of separate layers for repeaters, and optimizing the wiring network, yields an improvement in interconnect performance of up to 145% at the 50-nm node     

A stochastic wire-length distribution for gigascale integration(GSI). I. Derivation and validation

Based on Rent's Rule, a well-established empirical relationship, a rigorous derivation of a complete wire-length distribution for on-chip random logic networks is performed. This distribution is compared to actual wire-length distributions for modern microprocessors, and a methodology to calculate the wire-length distribution for future gigascale integration (GSI) products is proposed     

Sea of polymer pillars electrical and optical chip I/O interconnections for gigascale integration

Optical chip-to-chip communication is a promising technology that can mitigate some of the performance short-comings of electrical interconnections, especially bandwidth. Moreover, future high-performance chips are projected to drain hundreds of amperes of supply current. To this end, it is important to develop a high-density and high-performance integrated electrical and optical chip I/O interconnection technology. We describe sea of polymer pillars (or polymer pins), which enables the simultaneous batch fabrication of electrical and optical I/O interconnections at the wafer-level. The electrical and optical I/O interconnections are designed to be laterally compliant to minimize the stresses on the die's low-k dielectric as well as to maintain optical alignment between the coefficient of thermal expansion (CTE)-mismatched board and die during thermal cycling. We demonstrate the fabrication and mechanical performance of various size and aspect ratio electrical and optical polymer pillars. We also describe methods of fabricating polymer pillars with nonflat tip surface area for optical interconnection.     

A stochastic wire-length distribution for gigascale integration(GSI). II. Applications to clock frequency, power dissipation, and chipsize estimation

For pt.I see ibid., vol.45, no.3, pp.580-9 (Mar. 1998). Based on Rent's Rule, a well-established empirical relationship, a complete wire-length distribution for on-chip random logic networks is used to enhance a critical path model; to derive a preliminary dynamic power dissipation model; and to describe optimal architectures for multilevel wiring networks that provide maximum interconnect density and minimum chip size     

Wafer-level chip size package (WL-CSP)

Size reduction is one of the main driving forces for packaging in nearly all electronic applications. The interaction of size reduction with highest functionality and high reliability is also predominant for all microelectronic systems. Therefore a synergism of optimal product design, smallest single chip package and board technology will give the best solution. Wafer level CSP will be the best solution for single chip packaging matching all requirements for electronic systems and reducing total cost     

Compact physical models for multiwall carbon-nanotube interconnects

Compact physical models are derived for conductivity of multiwall carbon-nanotube (MWCN) interconnects. It is proven that for MWCNs shorter than the critical length (typically around 7 /spl mu/m), the conductivity decreases as diameter increases, whereas for MWCNs longer than the critical length, increasing the diameter results in higher conductivities. For long lengths (hundreds of micrometers), MWCNs can potentially have conductivities several times larger than that of copper or even single-wall carbon nanotube (SWCN) bundles. For short lengths (<10 /spl mu/m), however, SWCN bundles offer more than two times higher conductivities compared to MWCNs.     

Analysis and optimization of shielded RLC global interconnects for gigascale integration

Compact physical models are presented for on-chip double-sided shielded transmission lines, which are mainly used for long global interconnects where inductance effects should not be ignored. The models are then used to optimize the width and spacing of long global interconnects with repeater insertion. The impacts of increasing line width and spacing on various performance parameters such as delay, data-flux density, power dissipation and total repeater area are analysed. The product of data-flux density and reciprocal delay per unit length are defined as a figure of merit (FOM). By maximizing the FOM, the optimal width and spacing of shielded RLC global interconnects are obtained for various international technology roadmap for semiconductors (ITRS) technology nodes.     

Application of the Taguchi method to chip scale package (CSP)design

A three-dimensional (3-D) nonlinear finite element model of an overmolded chip scale package (CSP) on flex-tape carrier has been developed by using ANSYS^TM finite element simulation code. The model has been used to optimize the package for robust design and to determine design rules to keep package warpage within acceptable Joint Electron Device Engineering Council (JEDEC) limits. An L₁₈ Taguchi matrix has been developed to investigate the effect of die thickness and die size, mold compound material and thickness, flex-tape thickness, die attach epoxy and copper trace thicknesses, and solder bail collapsed stand-off height on the reliability of the package during temperature cycling. For package failures, simulations performed represent temperature cycling 125°C to -40°C. This condition is approximated by cooling the package which is mounted on a multilayer printed circuit board (PCB) from 125°C to -40°C. For solder ball coplanarity analysis, simulations have been performed without the PCB and the lowest temperature of the cycle is changed to 25°C. Predicted results indicate that for an optimum design, that is low stress in the package and low package warpage, the package should have smaller die with thicker overmold. In addition to the optimization analysis, plastic strain distribution on each solder ball has been determined to predict the location of solder ball with the highest strain level. The results indicate that the highest strain levels are attained in solder balls located at the edge of the die. The strain levels could then be used to predict the fatigue life of individual solder balls     

Improving the deflection of wire bonds in stacked chip scale package (CSP)

The deformation of gold wire bonds during transfer molding of stacked chip scale package (CSP) can seriously cause wire crossover and shorting. The major challenges of the stacked CSP development are to reduce the wire sweep (deflection), and make the sufficient space clearance between the wires of first to second die. In this paper, M shape wire looping program is developed to increase the wire sweep resistance in the stacked CSP. Both linear elastic finite element analysis and experiments based on wire bonding and molding process evaluation are conducted. It is found that M shape looping program is much better than conventional normal wire shape in terms of wire sweep resistance after molding. X-ray and scanning electronic microscopy (SEM) can verify the improvement of wire deflection after chemical de-capsulation. It is believed that using M shape looping program can efficiently overcome the risk of wire shorting and improve the yield of wire bonds in high volume production of stacked CSP.     

Thermal analysis of a flip chip ceramic ball grid array (CBGA) package

The function of an electronic cooling package is to dissipate heat to ensure proper operation and reliability. The flip chip ball grid array package is probably the most suitable package for high-level thermal performance applications. A high thermal performance flip chip ceramic ball grid array (FC-CBGA) package with an aluminum silicon carbide (AlSiC) lid and one without lid were evaluated using the computational fluid dynamics (CFD) technique. This paper compares the thermal performance of a 35 × 35 mm FC-CBGA package with three different die sizes of 5 × 5 mm, 15 × 15 mm and 20 × 20 mm. The performance of a lid fitted with different heat sinks was investigated in standard JEDEC defined natural and in forced convection environments. Thermal measurements were performed using a functional application specific integrated circuit (ASIC) chip, in compliance with the JEDEC standards. Excellent agreement was found between the numerical results and the measured data. Improved thermal performance was observed with a lidded package as compared to the unlidded one. However, no significant improvement was observed between lidded and unlidded packages when fitted with a heat sink subjected to forced convection. This paper also discusses the package thermal budget estimate with and without heat sinks. Printed circuit board and package top surface temperature patterns were measured using an infrared thermal camera. The usefulness of the thermal characterization parameter is demonstrated in system level applications. Parametric studies were carried out to understand the effect of die size, radiation effect, gird size variations and airflow rate on die junction temperature and package thermal resistance. This study also incorporates the effects of substrate, lid, die and PCB temperatures for different die sizes in natural and forced convection environments.     

硅基光子集成宽带大色散延时芯片（特邀）

集成、宽带、大色散延时的器件在微波光子滤波、真延时相控阵天线等领域有着重要的应用,可以有效地降低系统尺寸和功耗。文中提出并实现了一种基于硅基光子集成的宽带大色散延时芯片,通过采用超低损耗波导结构和侧壁法向量调制结构实现了片上集成大色散波导光栅,色散值超过250 ps/nm, 最大群延时达到2440 ps,带宽大于9.4 nm,该芯片有望用于微波光子学、高速光纤通信系统等领域。     

The effects of underfill and its material models onthermomechanical behaviors of a flip chip package

In this paper, the effects of underfill on thermomechanical behavior of two types of flip chip packages with different bumping size and stand-off height were investigated under thermal cycling both experimentally and two-dimensional (2-D) finite element simulation. The materials inelasticity, i.e., viscoelasticity of underfill U8437-3 and viscoplasticity of 60 Sn40 Pb solder, were considered in the simulations. The results show that the use of underfill encapsulant increases tremendously (~20 times) the thermal fatigue lifetime of SnPb solder joint, weakens the effects of stand-off height on the reliability, and changes the deformation mode of the package. It was found that the thermal fatigue crack occurs in the region with maximum plastic strain range, and the Coffin-Manson type equation could then be used for both packages with and without underfill. Solder joint crack initiation occurred before delamination when using underfill with good adhesion (75 MPa) and the underfill delamination may not be a dominant failure mode in the present study. The interfacial stresses at the underfill/chip interface were calculated to analyze delamination sites, which agree with the results from acoustic image. Moreover, the effects of material models of underfill, i.e., constant elasticity (EC) and temperature dependent elasticity (ET) as well as the viscoelasticity (VE), on the thermomechanical behaviors of flip chip package were also studied in the simulation. The VE model gives comparatively large plastic strain range and large displacements in the shear direction, as well as decreased solders joint lifetime. The ET model gives similar results as the VE model and could be used instead of VE in simulations for the purpose of simplicity     

Optimal n-tier multilevel interconnect architectures for gigascaleintegration (GSI)

A multilevel interconnect architecture design methodology that optimizes the interconnect cross-sectional dimensions of each metal layer is introduced that reduces logic macrocell area, cycle time, power consumption or number of metal layers. The predictive capability of this methodology, which is based on a stochastic wiring distribution, provides insight into defining the process technology parameters for current and future generations of microprocessors and application-specific integrated circuits (ASICs). Using this methodology on an ASIC logic macrocell case study for the 100 nm technology generation, the optimized n-tier multilevel interconnect architecture reduces macrocell area by 32%, cycle time by 16% or number of wiring tracks required on the topmost tier by 62% compared to a conventional design where pitches are doubled for every successive pair of levels. A new repeater insertion methodology is also described that further enhances gigascale integration (GSI) system performance. By using repeaters, a further reduction of 70% in macrocell area, 18% in cycle time, 25% in number of metal levels or 44% in power dissipation is achieved, when compared to an n-tier design without repeaters. The key distinguishing feature of the methodology is its comprehensive framework that simultaneously solves two distinct problems-optimal wire sizing and wiring layer assignment-using independent constraints on maximum repeater area for efficient design space exploration to optimize the area, power, frequency, and metal levels of a GSI logic megacell     

Procedure for design optimization of a T-cap flip chip package

In this study, a 1/4 three-dimensional finite element model of a T-cap flip chip package containing the substrate, underfill, solder bump, silicon die, metal cap and cap attachment was established to conduct thermo-mechanical reliability study during the flip chip fabrication processes. The applied thermal load was cooled from 183 °C to ambience 25 °C to determine the thermal stress and warpage during the curing period of solder ball mounting process. Under fixed geometry, two levels of underfill, metal caps and cap attachments were used to conduct the 2³ factorial design for determining reliable material combinations. The statistical tests revealed that the significant effects affecting the thermal stress were the underfill, metal cap, cap attachment and the interaction between the underfill and cap attachment. The metal cap, cap attachment and their interaction significantly affected the warpage. The proposed regression models were used to perform the surface response simulations and were useful in selecting suitable materials for constructing the package. This study provides a powerful strategy to help the designer to easily determine reliable packaging structures under various reliability considerations.     

Impact of die-to-die and within-die parameter fluctuations on themaximum clock frequency distribution for gigascale integration

A model describing the maximum clock frequency (FMAX) distribution of a microprocessor is derived and compared with wafer sort data for a recent 0.25-μm microprocessor. The model agrees closely with measured data in mean, variance, and shape. Results demonstrate that within-die fluctuations primarily impact the FMAX mean and die-to-die fluctuations determine the majority of the FMAX variance. Employing rigorously derived device and circuit models, the impact of die-to-die and within-die parameter fluctuations on future FMAX distributions is forecast for the 180, 130, 100, 70, and 50-nm technology generations. Model predictions reveal that systematic within-die fluctuations impose the largest performance degradation resulting from parameter fluctuations. Assuming a 3σ channel length deviation of 20%, projections for the 50-nm technology generation indicate that essentially a generation of performance gain can be lost due to systematic within-die fluctuations. Key insights from this work elucidate the recommendations that manufacturing process controls be targeted specifically toward sources of systematic within-die fluctuations, and the development of new circuit design methodologies be aimed at suppressing the effect of within-die parameter fluctuations     

超薄芯片叠层封装器件热可靠性分析

采用通用有限元软件MSC.Marc,模拟分析了一种典型的多层超薄芯片叠层封装器件在经历回流焊载荷后的热应力及翘曲分布情况,研究了部分零件厚度变化对器件中叠层超薄芯片翘曲、热应力的影响。结果表明:在整个封装体中,热应力最大值(116.2 MPa)出现在最底层无源超薄芯片上,结构翘曲最大值(0.028 26 mm)发生于模塑封上部边角处。适当增大模塑封或底层无源芯片的厚度或减小底充胶的厚度可以减小叠层超薄芯片组的翘曲值;适当增大底层无源超薄芯片的厚度(例如0.01 mm),可以明显减小其本身的应力值10 MPa以上。