A novel packaging approach for RF MEMS switching functions on alumina substrate

This paper reports the design of a hermetic-compatible wafer-scale package for RF MEMS based components. The presented packaging concept consists in encapsulating the whole RF device or subsystem instead of encapsulating each MEMS component separately, which will reduce the device size and cost. This approach is based on the MEMS fabrication technology on ceramic substrate and the use of laser drilled vias hole techniques to realize full metallized vias in alumina substrates. These vias holes will allow a low loss RF signal transmission inside the package without breaking its hermeticity. Hence, several packaged switching networks prototypes, based on ohmic contact MEMS switches, have been designed following this approach and the packaging electromagnetic impact on these components has been especially studied to result on good performance devices.     

Influence of a chip scale package on the frequency response of a MEMS microphone

This paper describes the influence of a chip scale MEMS package (CSMP) on the acoustic behaviour of a silicon microphone. The influence was calculated using an electro-mechanical–acoustical equivalent circuit. Standard packaging of microphones using die bonding and wire bonding leads to a large front volume which acts as a Helmholtz resonator. This can dramatically influence the frequency response of the microphone system by adding a second resonance. In the worst case this second resonance is in the acoustic frequency range, thus degrading its performance in an unacceptable way. In case of the CSMP only a small front volume is generated between the substrate and the flip-chipped microphone chip. Thus the resonance step-up is very small compared to standard packages. Furthermore the frequency response can be flattened by optimizing the geometry of the small sound holes in the substrate. By choosing an appropriate geometry of these sound holes the package can act as a low pass filter where the cut-off frequency can be placed to the desired value of the acoustic spectrum.     

A new measurement microphone based on MEMS technology

This paper presents a new type of measurement microphone that is based on MEMS technology. The silicon chip design and fabrication are discussed, as well as the specially developed packaging technology. The microphones are tested on a number of key parameters for measurement microphones: sensitivity, noise level, frequency response, and immunity to disturbing environmental parameters, such as temperature changes, humidity, static pressure variations, and vibration. A sensitivity of 22 mV/Pa (-33 dB re. 1 V/Pa), and a noise level of 23 dB(A) were measured. The noise level is 7 dB lower than state-of-the-art 1/4-inch measurement microphones. A good uniformity on sensitivity and frequency response has been measured. The sensitivity to temperature changes, humidity, static pressure variations and vibrations is fully comparable to the traditional measurement microphones. This paper shows that high-quality measurement microphones can be made using MEMS technology, with a superior noise performance.     

采用倒封装技术的硅热风速传感器封装的研究

本文给出了一个采用倒封装技术实现的硅热风速传感器的封装结构.该传感器使用铜柱凸点技术,倒装于薄层陶瓷上.利用陶瓷的导热性能实现传感器芯片的加热元件和环境风速的热交换,同时陶瓷又起保护和支撑传感器芯片的作用.测试结果表明,封装后的传感器具有良好的性能.     

Flexible Chip-Scale Package and Interconnect for Implantable MEMS Movable Microelectrodes for the Brain

We report here a novel approach called microelectromechanical systems (MEMS) microflex interconnect (MMFI) technology for packaging a new generation of bioMEMS devices that involve movable microelectrodes implanted in brain tissue. MMFI addresses the need for the following: (1) operating space for movable parts and (2) flexible interconnects for mechanical isolation. We fabricated a thin polyimide substrate with embedded bond pads, vias, and conducting traces for the interconnect with a backside dry etch, so that the flexible substrate can act as a thin-film cap for the MEMS package. A double-gold-stud-bump rivet-bonding mechanism was used to form electrical connections to the chip and also to provide a spacing of approximately 15-20 mum for the movable parts. The MMFI approach achieved a chip-scale package that is lightweight and biocompatible and has flexible interconnects and no underfill. Reliability tests demonstrated minimal increases of 0.35, 0.23, and 0.15 mOmega in mean contact resistances under high humidity, thermal cycling, and thermal shock conditions, respectively. High-temperature tests resulted in increases of > 90 and ~ 4.2 mOmega in resistance when aluminum and gold bond pads were used, respectively. The mean time to failure was estimated to be at least one year under physiological conditions. We conclude that MMFI technology is a feasible and reliable approach for packaging and interconnecting bioMEMS devices.     

Temperature characterization of flip-chip packaged piezoresistive barometric pressure sensors

In order to miniaturize piezoresistive barometric pressure sensors, a new flip-chip packaging technology has been developed. The thermal expansions of chip and package are different. So in a standard flip-chip package the strong mechanical coupling by the solder bumps would lead to stress in the sensor chip, which is unacceptable for piezoresistive pressure sensors. To solve this problem, in the new packaging technology the chip is flip-chip bonded on compliant springs to decouple chip and package. As the first step of the packaging process an under bump metallization (UBM) is patterned on the sensor wafer. Then solder bumps are printed. After wafer-dicing the chips are flip-chip bonded on copper springs within a ceramic cavity housing. Due to the compliance of the springs, packaging stress is induced into the sensor chip. As sources of residual stress the UBM and the solder bumps on the sensor chip were identified. Different coefficients of thermal expansion of the silicon chip, the UBM and the solder lead to plastic straining of the aluminum metallization between UBM and chip. As a consequence the measurement accuracy is limited by a temperature hysteresis. The influence of the chip geometry, e.g., the thickness of the chip or the depth of the cavity, on the hysteresis was investigated by simulation and measurements. As a result of this investigation a sensor chip was designed with very low residual stress and a temperature hysteresis which is only slightly larger than the noise of the sensor.     

Dicing challenges in microelectronics and micro electro-mechanical systems (MEMS)

 Both in semiconductor and micro electro-mechanical systems (MEMS) technology, a back end machining process is detaching the individual components by dicing the wafer into chips. To maximize the wafer surface available for integrated circuits or MEMS devices, the street width between the component structures has to be kept at a minimum. Therefore, there is a continuous thrust to minimize edge chipping as well as reduce the dicing wheel width. Furthermore, the dicing process may induce subsurface damages and microcracks particularly detrimental for packaging technology like flip chip technology, putting strain on the chip. Reducing the feed rate will result in a cutting mechanism which not only minimizes edge chip formation but also microcrack. By using gang wheels, the productivity may be maintained despite a lower feed rate.     

Parametric study of flip-chip packaging for an MEMS device with diaphragm

A backside-etched silicon chip with a polysilicon diaphragm flip-chip attached on a printed wiring board and globally bumped on a FR4 printed circuit board was investigated through a finite element analysis for determining three key parameters of flip-chip chip size packaging, namely, the size of solder bump, and the thickness of the printed wiring board with/without U8437-3 underfill. Four kinds of thermal-induced stresses and deformations in the diaphragm, solder bump, and printed wiring board were evaluated for the parametric study. As the simulation results show, the thermal-induced stresses in the diaphragm and solder bump can be reduced effectively if the printed wiring board is thinner. However, the printed wiring board is still required to be sufficiently thick to prevent warping. In addition, the underfill material also can reduce the induced stress occurring at the interface between the solder joint and the chip and improve reliability. In general, the parametric study can provide a basis for the flip chip package of a MEMS device with a diaphragm, such as a MEMS microphone, MEMS pressure sensor, etc.     

MEMS封装技术研究进展与趋势

介绍了MEMS(microelectromechanicalsystems)封装技术的研究现状和存在的问题,重点介绍了倒装芯片技术(flip chiptechnology简称FCT)、上下球栅阵列封装技术和多芯片模块封装技术三种很有前景的封装技术的特点及其在MEMS领域的应用实例,并且对MEMS封装有可能的发展趋势进行了分析。     

Die separation and packaging of a surface micromachined piezoresistive pressure sensor

The processing steps required to obtain a useful single medical sensor assembly are discussed, starting from an entire silicon wafer with thousands of surface micromachined sensors. Experiences concerning dicing and packaging of a piezoresistive pressure sensor are described, together with proposals for solutions. Problems with fracture of essential sensor structures are solved by use of a wafer protection tape. Existing solutions for flip–chip bonding and design of substrate for electrical interconnection are pushed to their limits due to the very small size of the novel sensor. As many of the processes can be simplified by an improved MEMS design, critical points related to the design are addressed.     

Development and optimization of the laser-assisted bonding process for a flip chip package

In a fine pitch flip chip package, a laser-assisted bonding (LAB) technology has recently been developed to overcome several reliability and throughput issues in the conventional mass reflow (MR) and thermal compression bonding technology. This study investigated the LAB process for a flip chip package with a copper (Cu) pillar bump using numerical heat transfer and thermo-mechanical analysis. During the LAB process, the temperature of the silicon die was uniform across the entire surface and increased to 280 °C within a few seconds; this was high enough to melt the solder. The heat in the die was quickly conducted to the substrate through the Cu pillar bumps. Meanwhile, the substrate temperature was low and remained constant. Therefore, a stable solder interconnection was quickly achieved with minimal stress and thermal damage to the package. The substrate thickness, the number of Cu bumps, and the bonding stage temperature were found to be important factors affecting the heat transfer behavior of the package. The temperature of the die decreased when a thinner substrate, a higher number of Cu bumps, and a lower bonding stage temperature were used. If the temperature of the die was not sufficiently high, insufficient heat was transferred to the solder to melt it, resulting in incomplete solder joint formation. Thermo-mechanical analysis also showed that the LAB process produced lower warpage and thermo-mechanical strain than the conventional MR process. These results indicated that a LAB process using a selective local heating method would be beneficial in reducing thermo-mechanical stress and increasing throughput for the fine pitch flip chip packages.

     

Flip chip solder bump inspection using vibration analysis

Flip chip technology is an attractive choice for high-density packaging and complex microsystem architectures. A critical element in the successful application of flip chip technology is the reliability of solder bumps. In this paper a nondestructive detection method is presented for the flip-chip solder bump inspection using ultrasonic excitation and vibration analysis. Simulations are implemented to explore the feasibility of this method, and experimental investigations are also performed, where the flip chips are excited by continuous ultrasonic waves and their vibration velocities are measured by a laser scanning vibrometer for further analysis. The results reveal that the defective chips can be distinguished from the good chips by the chip vibration velocities with the feature coefficient α, which proves the effectiveness of this method. Therefore, it may provide a new path for the improvement and innovation of flip chip on-line inspection systems.     

倒装芯片封装技术概论

高密度电子封装正朝着小型化、高I/O密度、更好的散热性和高的可靠性方向发展,传统引线键合技术已经无法满足要求。先进的倒装芯片封装技术由于具有较高的单位面积内I/O数量、短的信号路径、高的散热性、良好的电学和热力学性能,在电子封装中被广泛关注。底部填充胶被填充在芯片与基板之间的间隙,来降低芯片与基板热膨胀系数不匹配产生的应力,提高封装的稳定性。然而,流动底部填充胶依赖于胶的毛细作用进行填充,存在很多缺点。为了克服这些缺点,出现了非流动底部填充胶,以改善倒装芯片底部填充工艺。文章回顾了倒装芯片封装技术的发展,阐述了流动和非流动底部填充胶的施胶方式和性质。     

MEMS高g加速度传感器封装热应力的研究

封装热应力是导致MEMS器件失效的主要原因之一,本文设计了一种MEMS高g加速度传感器,并仿真研究了传感器在封装过程中的热应力及影响其大小的因素。根据封装工艺,建立设计的高g加速度传感器封装的有限元模型,利用AN-SYS软件仿真传感器在不同的贴片工艺中受到的热应力及影响热应力的因素。结果显示,在封装中,与直接贴片到管壳底部相比,MEMS高g加速度传感器芯片底面键合高硼硅玻璃后再贴片到管壳底部时,封装热应力可从135MPa降低到33MPa;在贴片工艺中,基板的热膨胀系数和贴片胶的弹性模量、热膨胀系数及厚度是影响封装热应力的主要因素;在健合工艺中,基板和键合温度主要影响到热应力的大小。     

Novel interconnection technology for heterogeneous integration of MEMS�CLSI multi-chip module

We developed novel interconnection technology for heterogeneous integration of MEMS and LSI multi-chip module, in which MEMS and LSI chips would be horizontally integrated on substrate and vertically stacked each others. The cavity chip composed of deep Cu TSV-beam lead interconnections was developed for interconnecting MEMS chips with high step height of more than few hundreds micrometer without the degradation of sensing elements. Fundamental characteristics were successfully obtained from pressure sensing MEMS chip with 360 μm thickness, which was connected to Si substrate by the cavity chip. MEMS and LSI chips were vertically integrated by using the cavity chip without any changing of chip design and extra processes. This interconnection technology can give strong solution for heterogeneous integration of MEMS and LSI chips multi-chip module.     

SOCs drive new product development

To dispel a potential misperception that system-on-chip designs are a long way off, the authors describe several examples of new products that derive benefits from using SOCs. These designs emphasize the combination of a complementary set of functions into an economically viable package. SOCs are fueling new products that wouldn't have been possible a few years ago. The article describes the features of Motorola's chip that answers the call for smaller wireless handsets and longer battery life by integrating the separate DSP and microcontroller onto one piece of silicon. It also makes some predictions about what's next in this design area. It goes on to describe how SOCs offer original equipment manufacturers an economical package on which to base new products. It is reported that thin-client vendors like Wyse are using this model to make serious inroads into corporate computing, a domain long dominated by the desktop PC. Next, the article explains how OEMs can save time and money by buying a product that integrates several networking functions-copier, facsimile, and laser-quality printer-into a single chip. Finally, the article presents a sampling of emerging commercial products that use microelectromechanical systems-semiconductor chips that integrate mechanical elements, sensors, actuators, and electronics on a silicon substrate. It describes some advantages of MEMS over current devices that perform the same functions and explains why MEMS is sure to be the technology of the future for many applications     

Sea-of-leads MEMS I/O interconnects for low-k IC packaging

Technology feasibility of MEMS-type chip I/O interconnects (namely Sea-of-Leads or SoL) is demonstrated. Acting like a spring, a MEMS lead can provide high mechanical compliance to compensate for mismatch of coefficient of thermal expansion (CTE) between a Si chip and a composite substrate. The compliant interconnects can provide low-stress connection between a chip and a PWB substrate, and, therefore, are promising to enable wafer-level packaging of IC chips with mechanically weak low-k interlayer dielectrics (ILD). The compliant interconnection also eliminates the need for an expensive underfilling process, which is one of the key challenges for scaling of conventional controlled collapse chip connection (C4) solder bumps in organic flip-chip packages. For the first time, SoL MEMS interconnects were investigated through the whole procedure of process integration, assembly, as well as reliability assessment. Without underfill, the SoL MEMS interconnects survived more than 500 thermal cycles indicating a promising improvement over a regular C4 solder joint. Failure analysis suggests that the MEMS leads do not fracture while failure occurs close to solder-Cu pad interface due to a nonreliable joining. Full reliability potential of the SoL MEMS interconnects may be demonstrated upon optimization of PWB metallurgy, soldermask design and lead compliance.     

圆片级低真空封装的MEMS压电振动能量收集器结构设计

MEMS低真空封装技术能为MEMS器件的可动部分提供低阻尼环境,降低能量损耗,有效提高器件的能量转换效率,具有重要的研究意义和应用前景,是MEMS技术的研究热点和难点。为了进一步提高MEMS压电振动能量收集器的输出性能,提出了圆片级低真空封装的共质量块MEMS压电悬臂梁阵列振动能量收集器新结构,通过有限元分析方法对器件结构参数进行了优化设计,在优化结构参数下仿真器件输出性能：在610 Hz、2 gn加速度下,器件的输出电压为8.88 V,输出功率为1220μW,能满足实际应用需求;根据器件结构设计了加工工艺流程,对低真空封装结构的实现和封装工艺探索具有重要意义。     

微机电系统的封装技术

MEMS封装是在微电子封装技术基础上发展起来的一项关键的MEMS技术。介绍了MEMS封装技术的功能、特点与分类。在此基础上,重点介绍了键合技术、上下球栅阵列技术、倒装芯片技术、多芯片技术以及3-D技术等几种重要的MEMS封装技术。最后,进一步探讨了MEMS封装的发展趋势及研究方向。