Current spreading effects in fully printed p-channel organic thin film transistors with Schottky source–drain contacts

Contact effects have been analyzed, by using numerical simulations, in fully printed p-channel OTFTs based on a pentacene derivative as organic semiconductor and with Au source/drain contacts. Considering source–drain Schottky contacts, with a barrier height of 0.46 eV, device characteristics can be perfectly reproduced. From the detailed analysis of the current density we have shown that current spreading occurs at the source contact, thus influencing the effective contact resistance. At low V_ds and for a given V_gs, the current is mainly injected from an extended source contact region and current spreading remains basically constant for increasing V_ds. However, by increasing V_ds the depletion layer of the Schottky contact expands and reaches the insulator–semiconductor interface, causing the pinch-off of the channel at the source end (V_dsat1). For V_ds > V_dsat1 the current injected from the edge of the source contact rapidly increases while the current injected from the remaining part of the source contact basically saturates. Current spreading shows a V_gs-dependence, since the contact injection area depends on the channel resistance and also barrier lowering of the Schottky source contact depends upon V_gs. The injected current from the edge of the source contact can be reproduced using the conventional diode current expression, assuming a constant value for the zero barrier lowering saturation current and considering a V_gs-dependent barrier lowering. The presented analysis clarifies the V_gs-dependence of the contact current–voltage characteristics and points out that the I–V contact characteristics cannot directly be related to a single diode characteristics. Indeed, the contact characteristics result from the combination of two rather different regimes: at low V_ds the current is injected from an extended source contact region with a current spreading related to V_gs, while for V_ds above the pinch-off of the channel at source end, the current is injected primarily from the edge of the source contact and is strongly enhanced by the barrier lowering.     

Drivability improvement in Schottky barrier source/drain MOSFETs with strained-Si channel by Schottky barrier height reduction

Due to an extra barrier between source and channel, the drivability of Schottky barrier source/drain MOSFETs (SBMOSFETs) is smaller than that of conventional transistors. To reach the drivability comparable to the conventional MOSFET, the Schottky barrier height (SBH) should be lower than a critical value. It is expected that SBH can be effectively reduced by a bi-axially strain on Si. In this letter, p-channel MOSFETs with PtSi Schottky barrier source/drain, HfAlO gate dielectric, HfN/TaN metal gate and strained-Si channel are demonstrated for the first time using a simplified low temperature process. Devices with the channel length of 4 μm have the drain current of 9.5 μA/μm and the transconductance of 14 μS/μm at V_gs − V_th = V_ds = −1 V. Compared to the cubic Si counterpart, the drain current and the transconductance are improved up to 2.7 and 3.1 times respectively. The improvement is believed to arising from the reduced barrier height of the PtSi/strained-Si contact and the enhanced hole mobility in the strained-Si channel.     

Electrical instability in short channel organic thin-film transistors induced by lucky-polaron mechanism

In this work we study the electrical stability under both gate bias stress and gate and drain bias stress of short channel (L = 5 μm) bottom contact/top gate OTFTs made on flexible substrate with solution-processed organic semiconductor and fluoropolymer gate dielectric. These devices show high field-effect mobility (μ_FE> 1 cm²V⁻¹s⁻¹) and excellent stability under gate bias stress (bias stress V_ds = 0V). However, after prolonged bias stress performed at high drain voltage, V_ds, the transfer characteristics show a decreased threshold voltage, degradation of the subthreshold slope and an apparent increase in the field effect mobility. Furthermore, the output characteristics show an asymmetry when measured in forward and reverse mode. These experimental results can be explained considering that the bias stress induces the damage of a small part of the device channel, localized close to the source contact. The analysis of the experimental data through 2D numerical simulations supports this explanation showing that the electrical characteristics after bias stress at high V_ds can be reproduced considering the creation of donor-like interface states and trapping of positive charge into the gate dielectric at the source end of the device channel. In order to explain this degradation mechanism, we suggest a new physical model that, assuming holes injection from the source contact into the channel in bounded polarons, envisages the defect creation at the interface near the source end of the channel induced by injection of holes that gained energy from both the high longitudinal electric fields and the polaron dissolution.     

Modeling and simulation of enhancement mode p-GaN Gate AlGaN/GaN HEMT for RF circuit switch applications

An enhancement mode p-GaN gate AlGaN/GaN HEMT is proposed and a physics based virtual source charge model with Landauer approach for electron transport has been developed using Verilog-A and simulated using Cadence Spectre, in order to predict device characteristics such as threshold voltage, drain current and gate capacitance. The drain current model incorporates important physical effects such as velocity saturation, short channel effects like DIBL (drain induced barrier lowering), channel length modulation (CLM), and mobility degradation due to self-heating. The predicted I_d-V_ds, I_d-V_gs, and C-V characteristics show an excellent agreement with the experimental data for both drain current and capacitance which validate the model. The developed model was then utilized to design and simulate a single-pole single-throw (SPST) RF switch.     

Modeling the gate bias dependence of contact resistance in staggered polycrystalline organic thin film transistors

We have modeled the dependence on the gate voltage of the bulk contact resistance and interface contact resistance in staggered polycrystalline organic thin film transistors. In the specific, we have investigated how traps, at the grain boundaries of an organic semiconductor thin film layer placed between the metal electrode and the active layer, can contribute to the bulk contact resistance. In order to the take into account this contribution, within the frame of the grain boundary trapping model (GBTM), a model of the energy barrier E_B, which emerges between the accumulation layer at the organic semiconductor/insulator interface and injecting contact, has been proposed. Moreover, the lowering of the energy barrier at the contacts interface region has been included by considering the influence of the electric field generated by the accumulation layer on the injection of carriers at the source and on the collection of charges from the accumulation layer to the drain contact. This work outlines both a Schottky barrier lowering, determined by the accumulation layer opposite the source electrode, as well as a Poole-Frenkel mechanism determined by the electric field of the accumulation layer active at the drain contact region. Finally it is provided and tested an analytical equation of our model for the contact resistance, summarizing the Poole-Frenkel and Schottky barrier lowering contribution with the grain boundary trapping model.     

High thermal stability AlGaAs/InGaAs enhancement-mode pHEMT using palladium-gate technology

The dc, flicker noise, power, and temperature dependence of AlGaAs/InGaAs enhancement-mode pseudomorphic high electron mobility transistors (E-pHEMTs) were investigated using palladium (Pd)-gate technology. Although the conventional platinum (Pt)-buried gate has a high metal work function, which is beneficial for increasing the Schottky barrier height of the E-pHEMT, the high rate of intermixing of the Pt-GaAs interface owing to the effect of the continuous production of PtAs₂ on the device influenced the threshold voltage (V_th) and transconductance (g_m) at high temperatures or over the long-term operation. Variations in these parameters make Pt-gate E-pHEMT-related circuits impractical. Furthermore, a PtAs₂ interlayer caused a serious gate leakage current and unstable Schottky barrier height. This study presents the Pd-GaAs Schottky contact because Pd, an inert material with high work function of 5.12 eV. Stable Pd inhibited the less diffusion at high temperatures and simultaneously suppressed device flicker noise. The V_th of Pd/Ti/Au Schottky gate E-pHEMT was 0.183 V and this value shifted to 0.296 V after annealing at 200 °C. However, the V_th shifted from 0.084 to 0.231 V after annealing of the Pt/Ti/Au Schottky gate E-pHEMT because the Pt sunk into a deeper channel. The slope of the curve of power gain cutoff frequency (f_max) as a function of temperature was −5.76 × 10⁻² GHz/°C for a Pd/Ti/Au-gate E-pHEMT; it was −9.17 × 10⁻² GHz/°C for a Pt/Ti/Au-gate E-pHEMT. The slight variation in the dc and radio-frequency characteristics of the Pd/Ti/Au-gate E-pHEMT at temperatures from 0 to 100 °C revealed that the Pd-GaAs interface has great potential for high power transistors.     

Traps centers and deep defects contribution in current instabilities for AlGaN/GaN HEMT's on silicon and sapphire substrates

AlGaN/GaN high electron mobility transistors (HEMTs) with Si and Al₂O₃ substrates reveals anomalies on I_ds-V_ds-T and I_gs-V_gs-T characteristics (degradation in drain current, kink effect, barrier height fluctuations, etc.). Stress and random telegraph signal (RTS) measurements prove the presence of trap centers responsible for drain current degradation. An explanation of the trapping mechanism responsible for current instabilities is proposed. Deep defects analysis performed by capacitance transient spectroscopy (C-DLTS), frequency dispersion of the output conductance (G_ds(f)), respectively, on gate/source and drain/source contacts and RTS prove the presence of deep defects localized, respectively, in the gate and in the channel regions. Defects detected by C-DLTS and G_ds(f) are strongly correlated, respectively, to barrier height inhomogeneities and kink anomalies. Gate current analysis confirms the presence of (G-R) centers acting like traps at the interface GaN/AlGaN. Finally, the localization of these traps defects is proposed.     

14.2 W/mm internally-matched AlGaN/GaN HEMT for X-band applications

High-performance X-band AlGaN/GaN high electron mobility transistor (HEMT) has been achieved by Γ-gate process in combination with source-connected field plate. Both its Schottky breakdown voltage and pinch-off breakdown voltage are higher than 100 V. Beside, excellent superimposition of direct current (DC) I-V characteristics in different V_ds sweep range indicates that our GaN HEMT device is almost current collapse free. As a result, both outstanding breakdown characteristics and reduction of current collapse effect guarantee high microwave power performances. Based upon it, we have developed an internally-matched GaN HEMT amplifier with single chip of 2.5 mm gate periphery, which exhibits power density of 14.2 W/mm with 45.5 dBm (35.5 W) output power and a power added efficiency (PAE) of 48% under V_ds = 48 V pulse operating condition at 8 GHz. To the best of our knowledge, it is the highest power density at this power level.     

Annealing temperature effect on electrical and structural properties of Cu/Au Schottky contacts to n-type GaN

Schottky contacts were fabricated on n-type GaN using a Cu/Au metallization scheme, and the electrical and structural properties have been investigated as a function of annealing temperature by current-voltage (I-V), capacitance-voltage (C-V), Auger electron spectroscopy (AES) and X-ray diffraction (XRD) measurements. The extracted Schottky barrier height of the as-deposited contact was found to be 0.69 eV (I-V) and 0.77 eV (C-V), respectively. However, the Schottky barrier height of the Cu/Au contact slightly increases to 0.77 eV (I-V) and 1.18 eV (C-V) when the contact was annealed at 300 °C for 1 min. It is shown that the Schottky barrier height decreases to 0.73 eV (I-V) and 0.99 eV (C-V), 0.56 eV (I-V) and 0.87 eV (C-V) after annealing at 400 °C and 500 °C for 1 min in N₂ atmosphere. Norde method was also used to extract the barrier height of Cu/Au contacts and the values are 0.69 eV for the as-deposited, 0.76 eV at 300 °C, 0.71 eV at 400 °C and 0.56 eV at 500 °C which are in good agreement with those obtained by the I-V method. Based on Auger electron spectroscopy and X-ray diffraction results, the formation of nitride phases at the Cu/Au/n-GaN interface could be the reason for the degradation of Schottky barrier height upon annealing at 500 °C.     

Source/drain extension region engineering in nanoscale double gate SOI MOSFETs: Novel design methodology for low-voltage analog applications

The present paper proposes for the first time, a novel design methodology based on the optimization of source/drain extension (SDE) regions to significantly improve the trade-off between intrinsic voltage gain (A_VO) and cut-off frequency (f_T) in nanoscale double gate (DG) devices. Our results show that an optimally designed 25 nm gate length SDE region engineered DG MOSFET operating at drain current of 10 μA/μm, exhibits up to 65% improvement in intrinsic voltage gain and 85% in cut-off frequency over devices designed with abrupt SDE regions. The influence of spacer width, lateral source/drain doping gradient and symmetric as well as asymmetrically designed SDE regions on key analog figures of merit (FOM) such as transconductance (g_m), transconductance-to-current ratio (g_m/I_ds), Early voltage (V_EA), output conductance (g_ds) and gate capacitances are examined in detail. The present work provides new opportunities for realizing future low-voltage/low-power analog circuits with nanoscale SDE engineered DG MOSFETs.     

Experimental and numerical analysis of channel-length-dependent electrical properties in bottom-gate,bottom-contact organic thin-film transistors with Schottky contact

Channel length dependence of field-effect mobility and source/drain parasitic resistance in pentacene thin-film transistors with a bottom-gate, bottom-contact configuration was investigated. Schottky barrier effect such as nonlinear behaviors in transistor output characteristics appeared and became more prominent for shorter channel length less than 10 μm, raising some concerns for a simple utilization of conventional parameter extraction methods. Therefore the gate-voltage-dependent hole mobility and the source/drain parasitic resistance in the pentacene transistors were evaluated with the aid of device simulation accounting for Schottky contact with a thermionic field emission model. The hole mobility in the channel region shows smaller values with shorter channel length even after removing the influence of Schottky barrier, suggesting that some disordered semiconductor layers with low carrier mobility exist near the contact electrode. This experimental data analysis with the simulation enables us to discuss and understand in detail the operation mechanism of bottom-gate, bottom-contact transistors by considering properly each process of charge carrier injection, carrier flow near the contact region, and actual channel transport.     

Orders‐of‐Magnitude Reduction of the Contact Resistance in Short‐Channel Hot Embossed Organic Thin Film Transistors by Oxidative Treatment of Au‐Electrodes

In this study we report on the optimization of the contact resistance by surface treatment in short‐channel bottom‐contact OTFTs based on pentacene as semiconductor and SiO₂ as gate dielectric. The devices have been fabricated by means of nanoimprint lithography with channel lengths in the range of 0.3 μm < L < 3.0 μm. In order to reduce the contact resistance the Au source‐ and drain‐contacts were subjected to a special UV/ozone treatment, which induced the formation of a thin AuO_x layer. It turned out, that the treatment is very effective (i) in decreasing the hole‐injection barrier between Au and pentacene and (ii) in improving the morphology of pentacene on top of the Au contacts and thus reducing the access resistance of carriers to the channel. Contact resistance values as low as 80 Ω cm were achieved for gate voltages well above the threshold. In devices with untreated contacts, the charge carrier mobility shows a power‐law dependence on the channel length, which is closely related to the contact resistance and to the grain‐size of the pentacene crystallites. Devices with UV/ozone treated contacts of very low resistance, however, exhibit a charge carrier mobility in the range of 0.3 cm² V^–1 s^–1 < μ < 0.4 cm² V^–1 s^–1 independent of the channel length.     

Scaling behaviors of transient noise current in organic field-effect transistors

Top-contact and bottom-gate organic field-effect transistors (OFETs) based on poly(3-hexylthiophene), P3HT polymer has been fabricated with thermal treatment condition. Transient noise currents of the OFETs are measured at various source–drain voltages ranging from 0 V to ?60 V with respect to a fixed gate voltage of ?60 V. The results from conventional power spectral density method are compared with the more robust Detrended Fluctuation Analysis. The latter has been proven to be reliable for fractal signals particularly in the presence of nonstationary effects. Interesting transitions between multiscaling and monoscaling behaviors are observed in the power spectral density as well as the Detrended Fluctuation Analysis plots for different applied source–drain voltage V_ds. Uncorrelated white noise characteristics are observed for noise current measured at low V_ds, meanwhile 1/f noise-like scaling behaviors are observed at intermediate V_ds. At higher V_ds, the noise characteristics appeared to be close to Brownian-like power-law behavior. The scaling characteristics of the transient noise current can be related to the charge carrier dynamics. It is also found that large numbers of trap centers are induced when the device is stressed at high applied V_ds. The existence of these trap centers would disperse charge carriers, leading to 1/f type noise that could diminish the presence of Brownian noise in a very short time.     

Temperature-dependent current-voltage characteristics of Cr/n-GaAs Schottky diodes

The Cr/n-GaAs/In Schottky contacts have been formed using dc magnetron sputtering. The current-voltage (I-V) characteristics of the device have been measured by steps of 20 K in the temperature range of 60-320 K. The ideality factor n of the device has remained about unchanged between 1.04 and 1.10 and Schottky barrier height around 0.58-0.60 eV from 320 K down to 160 K. It can be said that the experimental I-V data are almost independent of temperature above 160 K. After 160 K, the n value increased with a decrease in temperature and become 1.99 at 60 K. The I-V characteristics at high temperatures have been exactly explained by the standard TE model. The nature and origin of abnormal behaviors at low temperatures have been successfully explained by the current flow through the low SBH circular patches suggested by Tung and used by some studies in literature. It has been seen that the straight line of the nT vs. T plot with a T₀ value of 14 K was parallel to that of the ideal Schottky contact. Again, a lateral homogeneous BH value of 0.62 eV was calculated from the linear relationship between the ideality factor and barrier height values. It has been seen that he ?(T = 0) and BH temperature coefficient α values obtained from the flat band BH and the Norde’s model plots are in close agreement with each other.     

Gate controlled 2-DEG varactor for VCO applications in microwave circuits

A novel gate controlled Schottky diode varactor is introduced. The three-terminal varactor is a modulation-doped heterostructure of AlGaAs/GaAs with two Schottky contacts, similar to a metal–semiconductor–metal (MSM) diode. Schottky metal contacts are made to a two-dimensional electron gas (2-DEG). The third contact, the gate contact is formed from highly doped n⁺ GaAs material to allow an open optical window that can be used for optical gating and mixing. Structure capacitance is less than 1 PF and a change of more than 30% from the zero bias capacitance is observed with the applied gate voltage. On the basis of our quasi two-dimensional C–V model, the layer structure and device dimensions can be optimized and scaled to cover a wide range of operations in the microwave and millimeter wave regimes.     

Non-classical hot-electron mechanism and its implications on the reliability and scalability of the high-κ dielectric N-MOS Flash memory cell

Because a thick gate dielectric is needed for enhanced retention performance, development of deep-submicrometer flash memory technology entails aggressive channel engineering in order to suppress short-channel effect. In this work, we directly observe, in a 0.14 μm N-MOS flash cell with an abrupt channel doping profile, a transition from classical channel hot-electron (CHE) injection at high drain bias (V_ds) to non-classical hot-electron injection at low V_ds under conventional CHE biasing. We have also systematically investigated the effect of V_ds reduction on the scalability of the hot-electron induced oxide damage region via a simple current-voltage measurement method. Scaling of the oxide damage region, as V_ds decreases, is found to be suppressed in cells exhibiting the non-classical hot-electron injection phenomenon. This observation has important implications for the scalability of the high-κ dielectric based MOSFET targeted for multi-bit memory application using separate source and drain side hot-electron injection.     

Improved double-recessed 4H-SiC MESFETs structure with recessed source/drain drift region

An improved double-recessed 4H-SiC MESFETs structure with recessed source/drain drift region was proposed. The recessed source/drain drift region is to reduce channel thickness between gate and drain as well as eliminate gate depletion layer extension to source/drain. The recessed source/drain drift region of the proposed structure can be realized with the formation of double-recessed gate region. The simulated results showed that the breakdown voltage of the proposed structure is 145 V compared to 109 V of that of the published 4H-SiC MESFETs with double-recessed gate structure and yet maintain almost same saturation drain current characteristics. The output power density of the proposed structure is about 33% larger than that of the published double-recessed gate structure. The cut-off frequency (f_T) and the maximum oscillation frequency (f_max) of the proposed structure are 21.8 GHz and 81.5 GHz compared to 19.0 GHz and 76.4 GHz of that of the published double-recessed gate structure, respectively.     

Improved self-gain in deep submicrometer strained silicon-germanium pMOSFETs with HfSiOx/TiSiN gate stacks

The self-gain of surface channel compressively strained SiGe pMOSFETs with HfSiO_x/TiSiN gate stacks is investigated for a range of gate lengths down to 55 nm. There is 125% and 700% enhancement in the self-gain of SiGe pMOSFETs compared with the Si control at 100 nm and 55 nm lithographic gate lengths, respectively. This improvement in the self-gain of the SiGe devices is due to 80% hole mobility enhancement compared with the Si control and improved electrostatic integrity in the SiGe devices due to less boron diffusion into the channel. At 55 nm gate length, the SiGe pMOSFETs show 50% less drain induced barrier lowering compared with the Si control devices. Electrical measurements show that the SiGe devices have larger effective channel lengths. It is shown that the enhancement in the self-gain of the SiGe devices compared with the Si control increases as the gate length is reduced thereby making SiGe pMOSFETs with HfSiO_x/TiSiN gate stacks an excellent candidate for analog/mixed-signal applications.     

A three-region analytical model for short-channel SiC MESFETs

An improved analytical three-region model is proposed for short-channel SiC metal semiconductor field effect transistors (MESFETs). It takes into account two regions in the channel under the gate, and a third ungated high field region between the gate and the drain. This third region, which has been omitted in SiC MESFETs analytical models reported so far, experiences a large potential drop in short channel devices operating under high drain voltages. Therefore, its inclusion is critical in providing an accurate device modeling. To further improve our model, we have also incorporated parasitic resistances and incomplete ionization of dopants. Using this three-region analytical model, we have simulated the I-V characteristics of SiC MESFET with a 0.70 μm gate length, and obtained excellent agreement when compared with published experimental results.     

Simulation of InGaAs subchannel DG-HEMTs for analogue/RF applications

The paper reports on the influence of a barrier thickness and gate length on the various device parameters of double gate high electron mobility transistors (DG-HEMTs). The DC and RF performance of the device have been studied by varying the barrier thickness from 1 to 5 nm and gate length from 10 to 150 nm, respectively. As the gate length is reduced below 50 nm regime, the barrier thickness plays an important role in device performance. Scaling the gate length leads to higher transconductance and high frequency operations with the expense of poor short channel effects. The authors claim that the 30-nm gate length, mole fractions tuned In_0.53Ga_0.47As/In_0.7Ga_0.3As/In_0.53Ga_0.47As subchannel DG-HEMT with optimised device structure of 2 nm In_0.48Al_0.52As barrier layer show a peak g_m of 3.09 mS/µm, V_T of 0.29 V, I_ON/I_OFF ratio of 2.24 × 10⁵, subthreshold slope ~73 mV/decade and drain induced barrier lowering ~68 mV/V with f_T and f_max of 776 and 905 GHz at V_ds = 0.5 V is achieved. These superior performances are achieved by using double-gate architecture with reduced gate to channel distance.