V777测试系统DA／AD测试技术的研究

文章以V777测试系统为平台,用虚拟测试方法和DSP的思想来模拟数模混合测试仪的工作机制,包括激励的产生、响应的采集、数据处理和为DUT提供的测试波形的组合响应处理。利用V777测试系统PMU端口可并行测试的功能获取待测电路AD模块的8位输出,在误差允许范围内匹配其理论对应值。在低频下,利用PMU对DA端口模拟信号的输出进行采样,对采样得到的数据做数字信号算法处理,实现波形的判断。用上述方法以低成本来实现具有一定难度的电路的测试。     

Control of a Cascade STATCOM With Star Configuration Under Unbalanced Conditions

A control scheme for star-connected cascade static synchronous compensators (STATCOMs) operating under unbalanced conditions is proposed. The STATCOM is assumed to be connected to an equivalent three-phase star-connected power supply. By selecting the line-to-neutral voltages of the equivalent power supply, zero average active power in each phase can be obtained under unbalanced compensation currents or unbalanced supply voltages. Furthermore, to implement a separate control for the three-phase dc-link voltages, the average active power in each phase can also be adjusted to a target value determined by the dc-link voltage control loop. Then, by forcing the converter neutral voltage to be equal to the counterpart of the equivalent power supply, the STATCOM can be decoupled into three single-phase systems and the line-to-neutral voltage of the equivalent power supply can be used as the input voltage to the corresponding phase leg. Accordingly, reference current tracking and dc-link voltage maintaining can be simultaneously achieved under unbalanced conditions. The valid operating range of the star-connected cascade STATCOM under unbalanced conditions is also analyzed. The proposed control scheme has been tested using the power systems computer-aided design/electromagnetic transient in dc system (EMTDC) simulation results and the experimental results based on a 30-kVAr cascade STATCOM laboratory prototype are proposed.      

Applications of Mixed-Signal Technology in Digital Testing

For reducing the test application time and required tester pins per device, we propose the use of multi-valued logic (MVL) signals, which increases data rate between the device under test (DUT) and automatic test equipment (ATE). An MVL signal sends multiple bits of information per clock cycle on a physical channel. Conversion of signals between binary and MVL is accomplished by digital to analog and analog to digital converters available in the mixed-signal technology. To support MVL test application and avoid reliability issues, we add necessary modifications on ATE and DUT sides. Theoretical calculation and a prototype experiment demonstrate significant data rate increase. We integrate the proposed MVL technique into test methodologies involving reduced pin-count test (RPCT) for multi-core system-on-chip (SoC) and test compression. An actual automatic test equipment (ATE) based test of a DUT shows notable reduction in test application time with MVL test application.     

基于智能整流技术的电网电流谐波补偿方法研究

目前用于电网电流谐波补偿的电器设备,主要以PWM整流器为主。基于PWM整流器的电源产品只能被动地减小自身向电网输出的谐波电流,而对电网中业已存在的电流谐波污染束手无策。为了解决电网中电流谐波污染以及相关联的电压波形失真问题,采用基于SRM(智能整流模块)技术对电网电流谐波进行补偿。仿真结果表明,基于SRM的电力电子装置在从电网吸取电流并在向负载供电的同时,还能对电网电压的波形进行补偿,使电网电压波形接近正弦波形。     

Current waveform quality from grid‐connected photovoltaic inverters and its dependence on operating conditions

The increasing installation of grid‐connected photovoltaics (PV) in the urban environment will lead to a significant penetration into the low voltage electricity supply network of small power electronic generators. Inevitably some disturbance to the electricity supply quality will result from these embedded generators. It is shown that the inverters used to grid connect PV arrays are susceptible to minor distortion of the network waveform and that this can result in higher levels of current waveform distortion, or harmonic disturbance, being sourced into the supply than would be expected from analyses which assume an ideal voltage waveform. The level of current distortion is shown to be very dependent on the type of inverter control used. Inverter operation is also a function of operating point; clearly a device at part load cannot be expected to deliver the same quality of current waveform as when operating under its rated design conditions. The impedance of the grid connection also has an impact on the inverter's operation. Copyright © 2000 John Wiley & Sons, Ltd.     

Reference current estimation under distorted line voltage for control of shunt active power filters

Shunt active power filters (APF) are used in power systems for the compensation of harmonic currents generated for non linear loads. A new digital reference current estimation method for control of APF using a Kalman digital algorithm is presented. Its capability of prediction avoids the effects of computational lags derived from the digital signal processing. The characteristics of the proposed technique are: the harmonic current compensation in a global or a selective way, the fast dynamical response and its independence from disturbances in the line voltage waveform. Simulation and experimental results under distorted supply voltages demonstrate the usefulness of the presented technique to improve the filtering performance.     

Curvature-compensated BiCMOS bandgap with 1-V supply voltage

We present a bandgap circuit capable of generating a reference voltage of 0.53 V. The circuit, implemented In a submicron BiCMOS technology, operates with a supply voltage of 1 V, consuming 92 μW at room temperature. In the bandgap circuit proposed, we use a nonconventional operational amplifier which achieves virtually zero systematic offset, operating directly from the 1-V power supply. The bandgap architecture used allows a straightforward implementation of the curvature compensation method. The proposed circuit achieves 7.5 ppm/K of temperature coefficient and 212 ppm/V of supply voltage dependence, without requiring additional operational amplifiers or complex circuits for the curvature compensation     

A new dynamic voltage restorer with separating active and reactive power circuit design

Conventional dynamic voltage restorers (DVRs) install parallel battery and capacitor sets at the DC bus to supply the required power for voltage sag compensation. However, the reactive power output of a DVR may increase the ripple voltage at the inner DC bus, possibly resulting in a higher operating temperature of the battery and thus decreased battery life. This paper proposes a DVR system that uses a cascade power module to effectively compensate voltage sag. By separating the active and reactive compensation powers, the proposed DVR provides a lower ripple DC link for extending battery life and offers a flexible way to design the capacitor bank. To confirm the effectiveness of the proposed design, theoretical analysis and experimental validation were conducted under various scenarios. Test results confirm the feasibility and practicality of the proposed method.     

Networking automatic test equipment environments

Automatic test equipment (ATE) is a term that, in its broadest meaning, indicates a generic system capable of performing measurements in an automatic or semiautomated (human-assisted) way. Years ago, this term was used specifically to refer to an automated measurement system employed to test the functionality of some electronic device-under-test (DUT). Typical applications were in the manufacturing area, where ATE had a twofold nature: in-circuit testing and functional testing. For in-circuit testing, ATE often were stand-alone complex programmable machines, equipped with a bed-of-nails adapter specifically designed as a fixture to provide signal inputs and meaningful test-points of the DUT. The test engineer had the responsibility of writing code that determined the exact sequence of stimulus signals, response measurements, and go/no-go decisions. For this aim, a switch matrix and the ATE itself were suitably controlled and coordinated by a workstation. For functional testing, ATE consisted of off-the-shelf instruments connected to the DUT by some kind of front-end adapter. In the latter case, most of the effort of the test engineer consisted of designing a program to control the various instruments to assess DUT performances. When planning the use of a dedicated testing machine as opposed to a test bench, other factors were taken into account: measurement speed, cost, and fault coverage.     

Analysis of the Instantaneous Power Flow for Three-Phase PWM Boost Rectifier Under Unbalanced Supply Voltage Conditions

This paper proposes the analysis of the instantaneous power flow of three-phase pulse-width modulation (PWM) boost rectifier under unbalanced supply voltage conditions. An analytical expression for the instantaneous output power has been derived, which provides the link between the output dc link voltage and the instantaneous output power. A direct relationship between the dc link voltage ripples and the second harmonic component in the instantaneous output power has been established. Based on the input and output instantaneous power analytical expressions provided, the presence of the odd order harmonic components in the ac line currents can be explained. A simple cascaded PI control scheme has been developed for the dc output voltage control. The controller ensures that the dc link voltage is maintained constant and the supply side power factor is kept close to unity under the unbalanced supply voltage operating conditions. Simulation and experimental test results are provided on a 1.6-kVA laboratory-based PWM rectifier to validate the proposed analysis and control scheme.      

High-Efficiency Broadband Parallel-Circuit Class E RF Power Amplifier With Reactance-Compensation Technique

Class E amplifier offers high efficiency approaching 100% for an ideal case. This paper introduces a first practical implementation of a novel broadband class E power amplifier design combining a parallel-circuit load network with a reactance compensation technique. The novel broadband parallel-circuit class E load network using reactance compensation technique has been discussed based on theory and its experimental verification. A proper guidelines method of designing a high-efficiency broadband class E power amplifier with an LDMOS transistor until the final prototype measurement and optimization will be discussed. In the measurement level, the drain efficiency of 74% at an operating power of 8 W and power flatness of 0.7 dB are achieved across a bandwidth of 136-174 MHz. The efficiency result is the highest result for VHF broadband frequency to date with a low supply voltage of 7.2 V. Simulations of the efficiency, output power, drain voltage waveform, and load angle (impedance) were verified by measurements and good agreements were obtained.     

PTF-based control algorithm for three-phase interleaved inverter-based SAPF

In this paper, modelling and hardware implementation of three-phase interleaved inverter-based shunt active power filter (SAPF) is proposed to mitigate current harmonics, reactive power for ensuring unity power factor and load balancing without shoot-through effect. Shoot-through effect is one of the hazardous issues in conventional voltage source inverters such as damage of power electronic switches, electromagnetic interference, ringing in the power circuitry. The present power system has inevitable non-linear loads which create large variations in the supply voltage distortions. Therefore, the compensation capability and efficiency of the SAPFs degrades. A novel predictive tuned filter is proposed in this paper to estimate the variations in the amplitude of supply voltage, frequency and harmonics for extracting the fundamental voltage signal. The fundamental extracted signal is further processed for reference current generation using generalized p-q theory. The performance of the proposed system is simulated using MATLAB®/Simulink environment and tested under different supply voltage conditions. The simulation results have been validated by developing a prototype in the laboratory by using a dSPACE1104 controller. It is found from the simulated and experimental results that the proposed system is fast, robust and accurate which improves the power quality without shoot-through problem.     

一种采用共栅频率补偿的轨到轨输入/输出放大器

提出了一种采用共栅频率补偿的轨到轨输入/输出放大器,与传统的Miller补偿相比,该放大器不仅可以消除相平面右边的低频零点,减少频率补偿所需要的电容,还可获得较高的单位增益带宽.所提出的放大器通过CSMC 0.6μm CMOS数模混合工艺进行了仿真设计和流片测试:当供电电压为5V,偏置电流为20μA,负载电容为10pF时,其功耗为1.34mW,单位增益带宽为25MHz;当该放大器作为缓冲器,供电电压为3V,负载电容为150pF,输入2.66 Vpp10kHz正弦信号时,总谐波失真THD为-51.6dB.     

A novel 2.2 Gbps LVDS driver circuit design based on 0.35μm CMOS

This paper presents a novel high-speed low voltage differential signaling(LVDS) driver design for point-to -point communication.The switching noise of the driver was greatly suppressed by adding a charge/discharge circuit and the operating frequency of the circuit was also increased.A simple and effective common-mode feedback circuit was added to stabilize the output common-mode voltage.The proposed driver was implemented in a standard 0.35μm CMOS process with a die area of 0.15 mm~2.The test result show...     

基于瞬时无功理论的不对称负荷SVC装置研究

针对电力系统日益增多的三相不对称负荷所造成的电网功率因数低、电压波形畸变等问题,本文以平衡化原理与瞬时无功理论为理论支撑,提出一种静止无功补偿装置(Static Var Compensator)补偿导纳新算法。该算法通过对负荷电流有功分量和无功分量的解耦,利用提取出的无功分量计算理想补偿导纳,相比传统算法检测更为简便,且不受谐波分量影响。在Matlab/Simulink环境下建立TCR+FC型SVC模型,通过对三相不对称负荷的仿真,证明了所提算法的正确与可行,也验证了SVC装置对平衡三相不对称网络的有效性。     

雷达发射机阳极电源的原理分析

地波雷达是从事海洋环境研究以及电波传播相关理论探索的关键设备,设备安装和使用条件恶劣,并且处于连续运行状态,如何通过良好的维护来保证地波雷达的可靠运行,尤其是雷达的大功率发射设备,已成为使用和保障部门的重要课题。文中主要介绍了一种地波雷达微波管发射机的电源系统的组成,重点分析了阳极高压开关电源的电路原理,提出了变形脉宽调制控制的概念。 经过仿真和稳态工作波形分解,得出了该电源高可靠性和高效率的结论,给出了电源的主要工作电流、电压波形,希望为设备的使用和维护提供参考。     

Transient-induced latch-up test setup for wafer-level and package-level

Latch-up triggered by an impulse of short duration, is one root cause for field failures of CMOS devices. Standard tests, like JEDEC 78, which apply quasi-static overvoltage and overcurrent may fail to identify this susceptibility. The presented test method and setup allows to study the transient induced latch-up (TLU) phenomenon employing nstrigger impulses at wafer-level and package-level. A TLU-module superimposes the DC voltage of the power supply with a short stress pulse and delivers the combination to the tested pin of the DUT, avoiding destructive EOS. Closest possible distances between the TLU-module and the DUT and the use of RF-probes at wafer level allow risetimes of less than 1 ns, time resolved measurements of voltage and current, and an almost instantaneous limitation of the supply current after latch-up has been triggered. The short stress pulses were generated by transmission lines or solid state pulse generators. Abrupt changes in the voltage and current amplitudes indicate that latch-up has been triggered. The method is successfully demonstrated for several devices in different technologies.     

Pulse-based dead-time compensator for PWM voltage inverters

The dead time necessary to prevent the short circuit of the power supply in pulsewidth-modulated (PWM) voltage inverters results in output voltage errors. Although individually small, when accumulated over an operating cycle, the voltage errors are sufficient to distort the applied PWM signal. This paper presents a method to correct for the dead-time errors. The pulse-based dead-time compensator (PBDTC) is less hardware- and software-intensive than other dead-time compensation methods providing a low-cost solution. The pulse-based technique is developed by analyzing the effects of dead time on a pulse-by-pulse basis and correcting each pulse accordingly. The technique is evaluated through simulation and experimental results. Other compensation methods are evaluated, and the results compared with the pulse-based technique. This comparison indicates previous methods can produce magnitude and phase errors in the applied terminal voltage, whereas the proposed method compensates for the dead time without significant magnitude and phase errors in the terminal voltage of PWM voltage source inverters     

非合作目标脉冲相位式激光测距仪的测程研究

对于非合作目标的中程距离测量, 从测距范围、测量精度、速度和可靠性的折衷方面来讲, 脉冲相位式激光测距法优于常规的脉冲法测距和连续波相位法测距。在脉冲相位式激光测距中提出采用连续发射的正弦调制脉冲信号提高发射激光的峰值功率以提高测程, 但发射激光的平均功率被保持很低保证了发射激光对人眼的安全。同时根据硅雪崩光电二极管(Si-APD)噪声谱密度理论, 设计了具有温度补偿和反馈电阻噪声补偿的激光测距仪前放接收模块, 详细分析了背景光, 反向高压和反馈电阻对于Si-APD接收性能的影响。实验表明：根据该方法设计的前放接收模块使测距仪接收系统获得最大信噪比, APD工作在最佳倍增状态,从而提高测距仪的探测灵敏度和最大测程。     

低电压下CMOS数字电路概率模型研究

为解决数字电路低功耗问题,电路工作电压被不断降低,导致电路逻辑器件呈现概率特性。本文提出了低电压下CMOS数字电路的错误概率模型,并完成硬件电路测试验证。本文首先详述了深亚微米（DSM）量级的门电路及模块在低电压供电条件下导致器件出错的因素,结合概率器件结构模型推导基本逻辑门概率模型,并提出了状态转移法用于完成由门级到模块级的概率分析模型;我们搭建硬件平台对CMOS逻辑芯片进行了低供电压测试,通过分析理论推导结果与实测结果,验证并完善了分析模型。实验结果表明,由状态转移法推导的电路概率模型符合电路实际性能,从而为构建低电压下数字电路概率模型提供了可靠分析模型。