等离子体处理对非晶IGZO柔性薄膜晶体管性能的影响

本文研究了柔性基板上的薄膜晶体管,使用IGZO作为有源层,栅极绝缘层采用NH3等离子体和N2O等离子体分别进行处理,研究器件性能变化。结果表明等离子体类型及处理时间对阈值电压、场效应迁移率、开关比、亚阈值摆幅（SS）和偏压稳定性都有影响。TFT器件用NH3等离子体处理10秒显示出最佳的器件性能,阈值电压达到0.34 V,场效应迁移率为15.97 cm2/Vs,开关比为6.33×107,亚阈值摆幅为0.36 V /dec。本文提出的柔性IGZO-TFT是下一代柔性显示驱动装置较好选择。     

High-performance poly-Si TFTs with fully Ni-self-aligned silicided S/D and gate structure

In this letter, fully Ni self-aligned silicided (fully Ni-salicided) source/drain (S/D) and gate polycrystalline silicon thin-film transistors (FSA-TFTs) have been successfully fabricated on a 40-nm-thick channel layer. Experimental results show that the FSA-TFTs give increased ON/OFF current ratio, improved subthreshold characteristics, less threshold voltage rolloff, and larger field-effect mobility compared with conventional TFTs. The FSA-TFTs exhibit small S/D and gate parasitic resistance and effectively suppress the floating-body effect and parasitic bipolar junction transistor action. The characteristics of the FSA-TFTs are suitable for high-performance driving TFTs with good output characteristics and large breakdown voltage.     

HgTe Nanocrystal-Based Thin-Film Transistors Fabricated on Glass Substrates

HgTe nanocrystal-based thin-film transistors (TFTs) with Al₂ O₃ top-gate dielectrics were fabricated on glass substrates using sintered HgTe nanocrystals as the channel layers. To the best of our knowledge, this is the first report on the fabrication of nanocrystal-based TFTs on glass substrates. Colloidal HgTe nanocrystal films were first formed on the glass substrates by spin-coating. The HgTe nanocrystal films were then sintered at 150 degC, leading to a dramatic increase in their conductance, compared with the as-deposited films. The TFTs fabricated in this letter exhibit the typical characteristics of p-channel transistors with a field-effect mobility of 1.04 cm²/Vmiddots, a threshold voltage of +0.2 V, and an on/off current ratio of 1times10³. These results suggest that spin-coating and sintering at a low temperature enable the simple and low-cost fabrication of nanocrystal-based TFTs on glass substrates     

Asymmetric Electrical Properties of Corbino a-Si:H TFT and Concepts of Its Application to Flat Panel Displays

Inverted stagger hydrogenated-amorphous-silicon (a-Si:H) Corbino thin-film transistors (TFTs) were fabricated with a five-photomask process used in the processing of the active-matrix liquid-crystal displays (AM-LCD). The authors show that the a-Si:H Corbino TFT has the asymmetric electrical characteristics under different drain-bias conditions. To accommodate for these differences when the electrical device parameters are extracted, the authors developed asymmetric geometric factors. The ON-OFF current ratio can be significantly enhanced by choosing the outer electrode as the drain, while the field-effect mobility and threshold voltage are identical when different drain-bias conditions are used. Finally, the authors developed concepts of its possible application to AM-LCDs and active-matrix organic light-emitting displays     

ZnO Thin Film, Device, and Circuit Fabrication using Low-Temperature PECVD Processes

We report undoped ZnO films deposited at low temperature (200°C) using plasma-enhanced chemical vapor deposition (PECVD). ZnO thin-film transistors (TFTs) fabricated using ZnO and Al₂O₃ deposited in situ by PECVD with moderate gate leakage show a field-effect mobility of 10 cm²/V s, threshold voltage of 7.5 V, subthreshold slope <1 V/dec, and current on/off ratios >10⁴. Inverter circuits fabricated using these ZnO TFTs show peak gain magnitude (dV _out/dV _in) ~5. These devices appear to be strongly limited by interface states and reducing the gate leakage results in TFTs with lower mobility. For example, ZnO TFTs fabricated with low-leakage Al₂O₃ have mobility near 0.05 cm²/V s, and five-stage ring-oscillator integrated circuits fabricated using these TFTs have a 1.2 kHz oscillation frequency at 60 V, likely limited by interface states.     

Amorphous-silicon thin-film transistor with liquid phase depositionof silicon dioxide gate insulator

The liquid phase deposition of silicon dioxide (LPD-SiO₂) at 50°C has been successfully applied as the gate insulator for inverted, staggered amorphous silicon thin-film transistors (TFTs). The maximum field-effect mobility of the TFTs, estimated from the saturation region, was 0.53 cm²/V-s, comparable to that obtained for conventional, silicon nitride (SiN_x ) gate transistors. The threshold voltage and subthreshold swing were 6.2 V and 0.76 V/decade, respectively. Interface and bulk characteristics are as good as those obtained for silicon nitride (SiN _x) films deposited by plasma enhanced chemical vapor deposition     

High-Performance Nanowire TFTs With Metal-Induced Lateral Crystallized Poly-Si Channels

High-performance poly-Si thin-film transistors (TFTs) with 50-nm nanowire (NW) channels fabricated by integrating a simple spacer formation scheme and metal-induced-lateral-crystallization (MILC) technique are proposed. By using the sidewall spacer formation scheme, the NW channels with nanometer-scale feature sizes can be easily fabricated, exhibiting superior channel controllability through the triple-gate structure. In employing the MILC technique, the grain crystallinity of NW channels is significantly superior to that formed by the solid-phase-crystallization (SPC) technique. Therefore, the MILC NW TFT exhibits greatly improved electrical performances, including lower threshold voltage, steeper subthreshold swing, and higher field-effect mobility, as compared to those of the SPC NW TFT. Moreover, the superior threshold-voltage rolloff characteristics of MILC NW TFT are also demonstrated.     

Improved Electrical Characteristics and Reliability of MILC Poly-Si TFTs Using Fluorine-Ion Implantation

In this letter, fluorine-ion (F⁺) implantation was employed to improve the electrical performance of metal-induced lateral-crystallization (MILC) polycrystalline-silicon thin-film transistors (poly-Si TFTs). It was found that fluorine ions minimize effectively the trap-state density, leading to superior electrical characteristics such as high field-effect mobility, low threshold voltage, low subthreshold slope, and high on/off-current ratio. F⁺-implanted MILC TFTs also possess high immunity against the hot-carrier stress and, thereby, exhibit better reliability than that of typical MILC TFTs. Moreover, the manufacturing processes are simple (without any additional thermal-annealing step), and compatible with typical MILC poly-Si TFT fabrication processes.     

Improvement of electrical characteristics for fluorine-ion-implanted poly-Si TFTs using ELC

The fluorine ion implantation applied to the polycrystalline silicon thin-film transistors (poly-Si TFTs) is investigated in this letter. Experimental results have shown that fluorine ion implantation effectively minimized the trap state density, leading to superior electrical characteristics such as high field-effect mobility, low threshold voltage, and high ON/OFF current ratio. Furthermore, the fluorine ions tended to segregate at the interface between the gate oxide and poly-Si layers during the excimer laser annealing, even without the extra deposition of pad oxide on the poly-Si film. The presence of fluorine obviously enhanced electrical reliability of poly-Si TFTs.     

Bottom-Gate Gallium Indium Zinc Oxide Thin-Film Transistor Array for High-Resolution AMOLED Display

The fabrication process and the characteristics of bottom-gate $ hbox{Ga}_{2}hbox{O}_{3}{-}hbox{In}_{2}hbox{O}_{3}{-}hbox{ZnO}$ (GIZO) thin-film transistors (TFTs) are reported in detail. Experimental results show that oxygen supply during the deposition of GIZO active layer and silicon oxide passivation layer controls the threshold voltage of the TFT. The field-effect mobility and the threshold voltage of the GIZO TFT fabricated under the optimum process conditions are 2.6 $hbox{cm}^{2}/hbox{V} cdot hbox{s}$ and 3.8 V, respectively. A 4-in QVGA active-matrix organic light-emitting diode display driven by the GIZO TFTs without any compensation circuit in the pixel is successfully demonstrated.      

Complementary-like inverters based on an ambipolar solution-processed molecular bis(naphthalene diimide)-dithienopyrrole derivative

We report on high-mobility top-gate organic field-effect transistors (OFETs) and complementary-like inverters fabricated with a solution-processed molecular bis(naphthalene diimide)-dithienopyrrole derivative as the channel semiconductor and a CYTOP/Al₂O₃ bilayer as the gate dielectric. The OFETs showed ambipolar behavior with average electron and hole mobility values of 1.2 and 0.01 cm² V^?1 s^?1, respectively. Complementary-like inverters fabricated with two ambipolar OFETs showed hysteresis-free voltage transfer characteristics with negligible variations of switching threshold voltages and yielded very high DC gain values of more than 90 V/V (up to 122 V/V) at a supply voltage of 25 V.     

New selfalignment processes for amorphous silicon thin film transistors with polysilicon source and drain

New fabrication processes for selfaligned amorphous silicon TFTs are proposed. The TFTs have a polysilicon source and drain which are formed by ArF excimer laser annealing. They exhibit a field-effect mobility of 0.8 cm/sup 2//Vs, threshold voltage of 11 V, and on/off current ratio of higher than 10/sup 6/.<>     

A novel process-compatible fluorination technique with electrical characteristic improvements of poly-Si TFTs

A process-compatible fluorine passivation technique of poly-Si thin-film transistors (TFTs) was demonstrated by employing a novel CF/sub 4/ plasma treatment. Introducing fluorine atoms into poly-Si films can effectively passivate the trap states near the SiO/sub 2//poly-Si interface. With fluorine incorporation, the electrical characteristics of poly-Si TFTs can be significantly improved including a steeper subthreshold slope, smaller threshold voltage, lower leakage current, higher field-effect mobility, and better on/off current ratio. Furthermore, the CF/sub 4/ plasma treatment also improves the reliability of poly-Si TFTs with respect to hot-carrier stress, which is due to the formation of strong Si-F bonds.     

Effects of mechanical strain on laser crystallized polysilicon thin film transistors and ring oscillators fabricated on stainless steel foil

In this paper the influence of mechanical tensile strain on the performance of thin film transistors (TFTs), with various channel geometries, and of ring oscillators, with 3, 7, 11, 21, and 51 number of stages and device channel lengths of 1, 4, and 8 μm, fabricated on stainless steel foil substrate is investigated. TFT parameters such as field effect mobility, threshold voltage, subthreshold slope, leakage and gate current for both n-channel, and p-channel TFTs are studied at various longitudinal tensile strain levels. For strain levels from 0.0% to 0.5%, the field effect mobility of n-channel TFTs increases while that of p-channel ones decreases as the longitudinal tensile strain increases. The field effect mobility, of both n-channel and p-channel TFTs, becomes independent of longitudinal tensile strain at strain levels greater than 0.5%. Threshold voltage and subthreshold slope of p-channel TFTs increases while that of n-channel ones does not follow a specific trend. The leakage current of both type devices tends to decrease by increasing the longitudinal tensile strain. The propagation delay, per inverter stage of a ring oscillator, is investigated at different supply voltages and tensile strain levels. The propagation delay of inverters with longer device channel length (?4 μm) tends to decrease while that of shorter length tends to increase as the longitudinal tensile strain increases.     

Amorphous Silicon Display Backplanes on Plastic Substrates

Amorphous silicon (a-Si) thin-film transistor (TFT) backplanes are very promising for active-matrix organic light-emitting diode displays (AMOLEDs) on plastic. The technology benefits from a large manufacturing base, simple fabrication process, and low production cost. The concern lies in the instability of the TFTs threshold voltage (V_T) and its low device mobility. Although V_T-instability can be compensated by means of advanced multi-transistor pixel circuits, the lifetime of the display is still dependent on the TFT process quality and bias conditions. A-Si TFTs with field-effect mobility of 1.1 cm²/Vmiddots and pixel driver circuits have been fabricated on plastic substrates at 150 degC. The circuits are characterized in terms of current drive capability and long-term stability of operation. The results demonstrate sufficient and stable current delivery and the ability of the backplane on plastic to meet AMOLED requirements     

Performance of poly-Si TFTs fabricated by SELAX

Selectively enlarging laser crystallization (SELAX) has been proposed as a new crystallization process for use in the fabrication of thin-film transistors (TFTs). This method is capable of producing a large-grained and flat film of poly-Si. The average grain size is 0.3/spl times/5 /spl mu/m, and the surface roughness of the poly-Si layer is less than 5 nm. The TFTs fabricated with this method have better performance and are more uniform than those produced with the conventional excimer laser crystallization (ELC) method. The average values of field-effect mobility are 440 cm/sup 2//Vs (n-type), and 130 cm/sup 2//Vs (p-type). The subthreshold slope for both types is 0.20 V/dec. Values for standard deviation of threshold voltage are 0.03 V (n-type) and 0.20 V (p-type). The delay time of the CMOS-inverter of SELAX TFTs is less than half that of ELC TFTs.     

High performance low-temperature poly-Si n-channel TFTs for LCD

High-performance poly-Si TFTs were fabricated by a low-temperature 600°C process utilizing hard glass substrates. To achieve low threshold voltage (V_TH) and high field-effect mobility (μ_FE), the conditions for low-pressure chemical vapor deposition of the active layer poly-Si were optimized. Effective hydrogenation was studied using a multigate (maximum ten divisions) and thin-poly-Si-gate TFTs. The crystallinity of poly-Si after thermal annealing at 600°C depended strongly on the poly-Si deposition temperature and was maximum at 550-560°C. The V_TH and μ_FE showed a minimum and a maximum, respectively, at that poly-Si deposition temperature. The TFTs with poly-Si deposited at 500°C and a 1000-Å gate had a V _TH of 6.2 V and μ_FE of 37 cm²/V-s. The high-speed operation of an enhancement-enhancement type ring oscillator showed its applicability to logic circuits. The TFTs were successfully applied to 3.3-in.-diagonal LCDs with integration of scan and data drive circuits     

Fabrication of high-mobility p-channel poly-Si thin filmtransistors by self-aligned metal-induced lateral crystallization

High-mobility p-channel poly-Si TFTs were fabricated using a new low-temperature process (⩽500°C): self-aligned metal-induced lateral crystallization (MILC). With a one-step annealing at 500°C, activation of dopants in source/drain/gate a-Si films as well as the crystallization of channel a-Si films was achieved. The TFTs showed a threshold voltage of -1.7 V, and an on/off current ratio of ~10⁷ without post-hydrogenation. The mobility was measured to be as high as 90 cm²/V·s, which is two to three times higher than that of the poly-Si TFTs fabricated by conventional solid-phase crystallization at around 600°C     

采用不同透明电极的非晶铟镓锌氧化物薄膜晶体管

采用透明材料ITO和AZO为源漏电极,在室温下利用射频磁控溅射方法制作了底栅结构的非晶铟镓锌氧化物薄膜晶体管。实验发现,制备的薄膜晶体管均表现出了良好的开关特性。其中采用AZO为电极的薄膜晶体管的场效应迁移率为1.95cm2/V.s,开关比为4.53×105,在正向偏压应力测试下,阈值电压的漂移量为4.49V。     

Phosphorus Doping Effect in a Zinc Oxide Channel Layer to Improve the Performance of Oxide Thin-Film Transistors

In this study, we fabricated phosphorus-doped zinc oxide-based thin-film transistors (TFTs) using direct current (DC) magnetron sputtering at a relatively low temperature of 100°C. To improve the TFT device performance, including field-effect mobility and bias stress stability, phosphorus dopants were employed to suppress the generation of intrinsic defects in the ZnO-based semiconductor. The positive and negative bias stress stabilities were dramatically improved by introducing the phosphorus dopants, which could prevent turn-on voltage (V _ON) shift in the TFTs caused by charge trapping within the active channel layer. The study showed that phosphorus doping in ZnO was an effective method to control the electrical properties of the active channel layers and improve the bias stress stability of oxide-based TFTs.