三维叠层DRAM封装中硅通孔开路缺陷的模拟

采用硅通孔(TSV)技术的三维堆叠封装,是一种很有前途的解决方案,可提供微处理器低延迟,高带宽的DRAM通道.然而,在3D DRAM电路中,大量的TSV互连结构,很容易产生开路缺陷和耦合噪声,从而导致了新的测试挑战.通过大量的模拟研究.本文模拟了在三维DRAM电路的字线与位线中出现的TSV开路缺陷的故障行为,它作为有效...     

On Built-In Self-Test for Adders

We evaluate some of the previously proposed test approaches for various types of adders in an attempt to find an architecture-independent algorithm for testing adders in embedded Digital Signal Processors (DSPs) in Field Programmable Gate Arrays (FPGAs). We find that a minor modification to a previously proposed Built-In Self-Test (BIST) approach provides the highest fault coverage for most types of adders and, equally important, it is simple to implement.     

CLA加法器混合式BIST方案

本文以先行进行加法器为例,将确定性测试方法与伪随机测试方法相结合,提出了实现内建自测试电路中测试生成器的、在测试昨测试电路硬件开锁之间取得折衷的几种方案。最后,比较并分析了所得结果。     

低电压SRAM测试电路设计与实现

本文基于SMIC 40nm LL CMOS工艺对一款256Kb的低电压8T SRAM芯片进行测试电路设计与实现,重点研究低电压SRAM的故障模型和测试算法,并完成仿真验证与分析。电路主要包括DFT电路和内建自测试电路两部分,前者针对稳定性故障有着良好的覆盖率,后者在传统March C+算法基础上,提出了一种新的测试算法,March-Like算法,该算法能够实现更高的故障覆盖率。仿真结果表明,本文设计的DFT电路能够减小稳定性故障的最小可检测电阻,提高了稳定性故障的测试灵敏度;March-Like算法可以检测到低电压SRAM阵列中的写破坏耦合故障、读破坏耦合故障和写干扰故障。     

VLSI流水化格型数字滤波器的内建自测试

格型数字滤波器在信号处理领域得到了广泛应用,本文针对VLSI实现的流水化格型数字滤波器,提出了一种内建自测试方案,不需要对其内部基本功能单元作任何更改,且能在较短时间内检测所有的单固定型故障.所有测试序列都采用简单的算术运算产生.通过对已有功能模块如累加器的复用,作为测试序列生成和响应压缩,该方案能实现真速测试并最大程度的减少了硬件占用和系统性能占用.     

Diagnostic Data Compression Techniques for Embedded Memories with Built-In Self-Test

A system-on-chip (SOC) usually consists of many memory cores with different sizes and functionality, and they typically represent a significant portion of the SOC and therefore dominate its yield. Diagnostics for yield enhancement of the memory cores thus is a very important issue. In this paper we present two data compression techniques that can be used to speed up the transmission of diagnostic data from the embedded RAM built-in self-test (BIST) circuit that has diagnostic support to the external tester. The proposed syndrome-accumulation approach compresses the faulty-cell address and March syndrome to about 28% of the original size on average under the March-17N diagnostic test algorithm. The key component of the compressor is a novel syndrome-accumulation circuit, which can be realized by a content-addressable memory. Experimental results show that the area overhead is about 0.9% for a 1Mb SRAM with 164 faults. A tree-based compression technique for word-oriented memories is also presented. By using a simplified Huffman coding scheme and partitioning each 256-bit Hamming syndrome into fixed-size symbols, the average compression ratio (size of original data to that of compressed data) is about 10, assuming 16-bit symbols. Also, the additional hardware to implement the tree-based compressor is very small. The proposed compression techniques effectively reduce the memory diagnosis time as well as the tester storage requirement.     

Built-In Self-Test of Field Programmable Analog Arrays based on Transient Response Analysis

In this work a strategy for testing analog networks, known as Transient Response Analysis Method, is applied to test the Configurable Analog Blocks (CABs) of Field Programmable Analog Arrays (FPAAs). In this method the Circuit Under Test (CUT) is programmed to implement first and second order blocks and the transient response of these blocks to known input stimuli is analyzed. Taking advantage of the inherent programmability of the FPAAs, a BIST-based scheme is used in order to obtain an error signal representing the difference between fault-free and faulty CABs. Two FPAAs from different manufacturers and distinct architectures are considered as CUT. For one of the devices there is no detailed information about its structural implementation. For this reason, a functional fault model based on high-level parameters of the transfer function of the programmed blocks is adopted, and then, the relationship between these parameters and CAB component deviations is investigated. The other considered device allows a structural programming in which the designer can directly modify the values of programmable components. This way, faults can be injected by modifying the values of these components in order to emulate a defective behavior. Therefore, it is possible to estimate the fault coverage and test application time of the proposed functional test method when applied to both considered devices.

A Built-In Self-Test structure for measuring gain and 1-dB compression point of Power Amplifier

This paper proposes a Built-In Self-Test (BIST) structure for measuring the gain and the 1-dB compression point of the Power Amplifier (PA) in transceiver ICs. In this structure, it is not necessary to use the external devices for mapping and DC measuring because of linearity of blocks, comparative performance in the linear region and the digital representation of the 1-dB compression point and gain value. The BIST Circuit is designed and simulated in 180 nm RF-CMOS process with Spectre-RF for a 900 MHz PA while it can achieve an acceptable accuracy which the input referred 1-dB compression point and gain value can be obtained with an error of about 0.2 dBm and 0.18 dB, respectively and the testing time is about 25 µs depends on resolution. Finally, in order to verify the proposed approach, we implemented practically a similar discrete circuit as proof-of-concept prototype that it obtained input referred 1-dB compression point value with an error of about 0.15 dBm.     

Innovative Built-In Self-Test Schemes for On-Chip Diagnosis, Compliant with the IEEE 1149.4 Mixed-Signal Test Bus Standard

This paper presents a testing scheme for analog and mixed-signal circuitry compatible with the IEEE 1149.4 mixed-signal test bus standard. A high-speed dynamic current sensor is described, as well as an innovative self-diagnostic method called VDDQ. The former is used to measure signature supply currents and to compare them with the footprint of a defect-free circuit. The latter senses the quiescent nodal voltages on several nodes of the circuit under test and compares them to their nominal values. A flag is raised if significant deviations are found. Simulation results are provided for the high-speed dynamic current sensor. Through simulations the VDDQ method has performed at one node test every half millisecond and has potential for much higher speed. It is faster than currently used methods in industry, which average to 5000 nodes per minute. This will potentially allow a defect-free IC to enter the market in significantly less time than with conventional testing methods.     

A 1 Tb/s 3 W Inductive-Coupling Transceiver for 3D-Stacked Inter-Chip Clock and Data Link

A 1 Tb/s 3 W inter-chip transceiver transmits clock and data by inductive coupling at a clock rate of 1 GHz and data rate of 1 Gb/s per channel. 1024 data transceivers are arranged with a pitch of 30 mum in a layout area of 1 mm². The total layout area including 16 clock transceivers is 2 mm² in 0.18 mum CMOS and the chip thickness is reduced to 10 mum. Bi-phase modulation (BPM) is employed for the data link to improve noise immunity, reducing power in the transceiver. Four-phase time division multiple access (TDMA) reduces crosstalk and the bit-error rate (BER) is lower than 10^-13     

一种3D堆叠集成电路中间绑定测试时间优化方案

中间绑定测试能够更早地检测出3D堆叠集成电路绑定过程引入的缺陷,但导致测试时间和测试功耗剧增.考虑测试TSV、测试管脚和测试功耗等约束条件,采用整数线性规划方法在不同的堆叠布局下优化中间绑定测试时间.与仅考虑绑定后测试不同,考虑中间绑定测试时,菱形结构和倒金字塔结构比金字塔结构测试时间分别减少4.39%和40.72%,测试TSV增加11.84%和52.24%,测试管脚减少10.87%和7.25%.在测试功耗约束下,金字塔结构的测试时间增加10.07%,而菱形结构和倒金字塔结构测试时间只增加4.34%和2.65%.实验结果表明,菱形结构和倒金字塔结构比金字塔结构更具优势.     

I/O divided column redundancy scheme for high-speed DRAM withmultiple I/Os

A novel I/O divided column redundancy (IDCR) scheme that can improve the effectiveness of repair and minimise the overhead of the die area is presented. The IDCR scheme has greater flexibility than conventional schemes in multiple I/O DRAMs. Since an IDCR can share neighbouring redundant column lines (RCLs), the RCLs of neighbouring I/O blocks can be used to repair the defective column lines of a self-block. This work also shows that the IDCR scheme improves the data access speed of normal column lines or redundant column lines by reducing the data bus loading     

嵌入式存储器的内建自修复设计

目前，关于嵌入式存储器的内建自测试（MBIST）技术已经日趋成熟。基于这种背景．研究了一种高效的内建自修复（MBISR）方法，试验表明它具有低面积开销和高修复率等优点，保证了嵌入式存储器不仅可测．而且可修复。极大地提高了芯片的成品率。     

Column redundancy scheme for multiple I/O DRAM using mapping table

A new column redundancy scheme is presented that can minimise the die area overhead by repair circuits and also achieve fast access speed in high density dynamic random access memories (DRAMs) with wide data widths. The proposed scheme has a large redundancy-area-unit (RAU) which operates a flexible column redundancy scheme that consecutively shifts RDQ (redundant I/O) to neighbouring MDQ (main I/O) without any speed penalty. By using the proposed mapping fuse algorithm. The number of fuses required to store the fail bit address can be reduced, and the chip area reduced.     

A Design of Linearity Built-in Self-Test for Current-Steering DAC

In this paper, a current-mode Built-In Self-Test (BIST) scheme is proposed for on-chip estimating static non-linearity errors in current-steering digital-to-analog converters (DACs). The proposed DAC BIST scheme is designed to verify a 10-bit segmented current-steering DAC, consist of a 5-bit coarse DAC and a 5-bit fine one. This proposed BIST scheme includes a current-mode sample-and-difference circuit to increase the sampling current accuracy and control a current-controlled oscillator (ICO). In addition, only 36 measurements are required by using the selected-code method rather than 1024 measurements for the conventionally-utilized all-code method. Compared to the conventionally-utilized all-code method, about 85-% reduction of test time can be achieved.     

一种节约面积的可编程存储器内建自测试设计方法

随着深亚微米技术不断的发展,在SoC设计中存储器需求越来越大,芯片的量产需要有效率而又具有相对的低成本的测试方法.可编程存储器内建自测试方法基于客制化的控制器,提供了一定程度可靠的弹性以及所需合理的硬件成本.我们在本文提出了一个P-MBIST设计的硬件分享架构,经由分享共用的地址产生器与控制器,P-MBIST电路的面积开销能够大幅减小,利用加入的两级流水线能够达到更高的测试速度.最后,所提出的P-MBIST电路能够由使用者自定义的配置文档而自动生成.     

Uniqueness in activation energy and charge-to-breakdown of highly asymmetrical DRAM Al/sub 2/O/sub 3/ cell capacitors

Al/sub 2/O/sub 3/ cell capacitors for dynamic random access memory (DRAM) applications were tested using constant voltage, time-dependent dielectric breakdown (TDDB) tests. The capacitors had area-enhancing, hemispherical grain (HSG) polysilicon as bottom electrodes (BEs). These electrodes acted as points of high electric field, and eased charge injection into the Al/sub 2/O/sub 3/. As a result, the capacitors had highly asymmetric current-voltage (I-V) characteristics. Time-to-fails (TTFs) were polarity-dependent, and, thus, much worse for HSG injection. However, activation energy (E/sub a/) and charge-to-breakdown (QBD) obtained from conducting stress under opposite polarities were a unique function of the electric field only. The results point to a common, polarity-independent mechanism responsible for final breakdown, and the possibility that only the kinetics of degradation is electrode controlled. Good correlation with the thermochemical E model suggests that the breakdown mechanism in Al/sub 2/O/sub 3/ might be similar to SiO/sub 2/.     

TFT-LCD驱动控制芯片内置SRAM的自测试设计

针对单片集成TFT-LCD驱动控制芯片内置SRAM的特点,提出了一种将内建自测试与机台测试相结合的SRAM测试方案.测试向量由机台提供,测试过程中启动内部自测试电路.在SRAM的读出寄存器和写入寄存器之间建立一条通路,测试向量通过这条通路在SRAM单元之间传递,形成了一个长的移位链,读出数据送给比较器检测.与传统自测试结构相比,该方案面积开销小,灵活性高.     

A 1-Mbit DRAM with 33-MHz serial I/O ports

High-speed operation, a 33-MHz serial cycle, and a 10-ns serial data access time have been realized by internal serial/parallel conversion circuits, a newly designed I/O controller circuit, new dynamic register circuits, a divided sensing method, and an optimized layout design. The chip is fabricated with a 1.2-/spl mu/m double-level polysilicon and double-level aluminium n-channel MOS process technology. An optimized interlevel insulator realizes equivalent first- and second-level aluminium pitches for a compact chip design. The chip size is 5.88/spl times/11.2 mm/SUP 2/. This memory has high-speed input and output capability as well as random accessibility. These features are suitable for TV and VCR frame-memory-system applications.     

LSC87中嵌入式ROM内建自测试实现

LSC87芯片是与Intel8086配套使用的数值协处理器，体系结构复杂，有较大容量的嵌入式ROM存储器，考虑到与Intel8087的兼容性和管脚的限制，必须选择合适的可测性设计来提高芯片的可测性。文章研究了LSC87芯片中嵌入式ROM存储器电路的设计实现，然后提出了芯片中嵌入式ROM电路的内建自测试，着重介绍了内建自测试的设计与实现，并分析了采用内建自测试的误判概率，研究结果表明，文章进行的嵌入式ROM内建自测试仅仅增加了很少的芯片面积开销，获得了满意的故障覆盖率，大大提高了整个芯片的可测性。