一种改进的层次化SOCs并行测试封装扫描单元

 测试封装是实现SOC内部IP核可测性和可控性的关键,而扫描单元是测试封装最重要的组成部分.然而传统的测试封装扫描单元在应用于层次化SOCs测试时存在很多缺点,无法保证内部IP核的完全并行测试,并且在测试的安全性,功耗等方面表现出很大问题.本文提出一种改进的层次化SOCs测试封装扫描单元结构,能够有效解决上述问题,该结构的主要思想是对现有的扫描单元进行改进,实现并行测试的同时,通过在适当的位置增加一个传输门,阻止无序的数据在非测试时段进入IP核,使得IP核处于休眠状态,保证了测试的安全性,实现了测试时的低功耗.最后将这种方法应用在一个工业上的层次化SOCs,实验分析表明,改进的测试封装扫描单元比现有扫描单元在增加较小硬件开销的前提下,在并行测试、低功耗、测试安全性和测试覆盖率方面有着明显的优势.     

3D TSV测试的挑战和潜在解决方案(英文)

3D硅通孔技术增加电路密度、降低功耗、提高带宽的优势在业内已得到广泛的认可。随着3D TSV技术的迅速发展,对于测试成本的优化就显得尤为突出,现有的测试方法已提出了很多挑战3D TSV技术的解决方案。提出了一种不同的应对3D TSV测试技术挑战的完整的3DTSV测试解决方案,其中某些方面涉及到3D TSV测试的前沿技术,而且也是唯一面向3D TSV测试特定的解决方案。最后,给出了一些采用完整3D TSV测试中其余的挑战。     

3D封装与硅通孔(TSV)工艺技术

在IC制造技术受到物理极限挑战的今天,3D封装技术越来越成为了微电子行业关注的热点。对3D封装技术结构特点、主流多层基板技术分类及其常见键合技术的发展作了论述,对过去几年国际上硅通孔（TSV）技术发展动态给与了重点的关注。尤其就硅通孔关键工艺技术如硅片减薄技术、通孔制造技术和键合技术等做了较详细介绍。同时展望了在强大需求牵引下2015年前后国际硅通孔技术进步的蓝图。     

基于MEMS圆片级封装/通孔互联技术的SIP技术

<正>随着科学技术的发展,3D SIP(system-in-package)技术已成为世界热点。基于MEMS圆片级封装WLP(Wafer-level packaging)的SIP技术是目前3D SIP最重要技术之一,它充分利用MEMS的TSV(Through-silicon via)和圆片级键合技术,实现Si与GaAs、Si与陶瓷等异质材料间垂直互联和圆片级集成。该技术可以将传感     

3DIC集成与硅通孔(TSV)互连

介绍了3维封装及其互连技术的研究与开发现状,重点讨论了垂直互连的硅通孔（TSV）互连工艺的关键技术及其加工设备面临的挑战．提出了工艺和设备开发商的应对措施并探讨了3DTSV封装技术的应用前景。     

A Novel Reconfigurable Wrapper for Testing of Embedded Core-Based SOCs and its Associated Scheduling Algorithm

In this paper a mathematical formulation and an efficient solution, of the embedded core-based system-on-chip (SOC) test scheduling problem (ECTSP) is presented. The ECTSP can be stated as follows; given a chip with N _C cores each having a test T _i; where T _i takes time to execute on a test access mechanism (TAM) of width w _j, and a constraint W on the number of top-level test pins; calculate the TAM assignment vector and the schedule for each test T _i, such that the completion time of the full chip test is minimized. All existing approaches have solved the ECTSP by solving the TAM partition and scheduling problem sequentially. In this paper we present an unified approach to solve the ECTSP. We present the first report of a design of reconfigurable core wrapper which allows for a dynamic change in the width of the test access mechanism (TAM) executing a core test. An automatic procedure for the creation of DfT hardware required for reconfiguration using a graph theoretic representation of core wrappers is also presented. For the case of reconfigurable wrappers, efficient algorithms to compute the schedule are presented based upon some recent results in the field of malleable task scheduling. Cases in which the degree of reconfigurability are constrained are considered; the case when only a single core can have reconfigurable wrapper, a schedule with zero TAM idle time can be found in time O(N _C(N _C + W)lgW), and the case when only 2 different wrapper configurations are allowed can be solved in time O(N _C ³). Comparison with existing results on benchmark SOCs show that our algorithms outperform state-of-art ILP formulations not only in schedule makespan, but also significantly reduce computation time.     

基于IEEE 1500的嵌入式芯核外壳测试封装设计

由于IP芯核被嵌入到片上系统(SoC)后,无法直接对其输入输出引脚进行测试,传统的测试方法已不能满足IP核的测试需求。在对IEEE 1500 标准进行相关研究的基础上,分析了测试架构的结构功能及其相应的操作指令,对ITC’02基准测试电路中的h953芯片进行了外壳测试封装设计,并通过多种指令仿真验证了设计的正确性。     

一种基于仲裁器的键合前硅通孔测试方法

硅通孔(TSV)故障严重降低了三维集成电路的良率和可靠性。为了在制造流程中尽早精确地排除TSV故障,提出了一种基于仲裁器的键合前TSV测试方法。由于高电平信号通过故障TSV的延迟时间小于无故障TSV,比较被测TSV与无故障TSV的延迟时间,即可判断被测TSV是否存在故障,比较结果由仲裁器给出。依次将被测TSV的延迟时间与不同的延迟时间相比,可对其延迟进行区间定位,实现TSV故障分级。实验结果表明,该方案能够检测出开路电阻大于281 Ω的电阻开路故障、泄漏电阻小于223 MΩ的泄漏故障,有效解决了两种TSV故障共存的检测问题。与现有同类方法相比,该方法提高了测试精度,增加了可检测故障范围,并且可以进行故障分级。     

Voltage Optimization of Power Delivery Networks through Power Bump and TSV Placement in 3D ICs

To reduce interconnect delay and power consumption while improving chip performance, a three‐dimensional integrated circuit (3D IC) has been developed with die‐stacking and through‐silicon via (TSV) techniques. The power supply problem is one of the essential challenges in 3D IC design because IR‐drop caused by insufficient supply voltage in a 3D chip reduces the chip performance. In particular, power bumps and TSVs are placed to minimize IR‐drop in a 3D power delivery network. In this paper, we propose a design methodology for 3D power delivery networks to minimize the number of power bumps and TSVs with optimum mesh structure and distribute voltage variation more uniformly by shifting the locations of power bumps and TSVs while satisfying IR‐drop constraint. Simulation results show that our method can reduce the voltage variation by 29.7% on average while reducing the number of power bumps and TSVs by 76.2% and 15.4%, respectively.     

基于TSV转接板的3D SRAM单粒子多位翻转效应

为了研究硅通孔(TSV)转接板及重离子种类和能量对3D静态随机存储器(SRAM)单粒子多位翻转(MBU)效应的影响,建立了基于TSV转接板的2层堆叠3D封装SRAM模型,并选取6组相同线性能量传递(LET)值、不同能量的离子(¹¹B与^4He、²⁸Si与¹⁹F、⁵⁸Ni与²⁷Si、⁸⁶Kr与⁴⁰Ca、¹⁰⁷Ag与⁷⁴Ge、¹⁸¹Ta与¹³²Xe)进行蒙特卡洛仿真。结果表明,对于2层堆叠的TSV 3D封装SRAM,低能离子入射时,在Si路径下,下堆叠层SRAM多位翻转率比上堆叠层高,在TSV(Cu)路径下,下堆叠层SRAM多位翻转率比Si路径下更大;具有相同LET值的高能离子产生的影响较小。相比2D SRAM,在空间辐射环境中使用基于TSV转接板技术的3D封装SRAM时,需要进行更严格的评估。     

Test Wrapper and Test Access Mechanism Co-Optimization for System-on-Chip

Test access mechanisms (TAMs) and test wrappers are integral parts of a system-on-chip (SOC) test architecture. Prior research has concentrated on only one aspect of the TAM/wrapper design problem at a time, i.e., either optimizing the TAMs for a set of pre-designed wrappers, or optimizing the wrapper for a given TAM width. In this paper, we address a more general problem, that of carrying out TAM design and wrapper optimization in conjunction. We present an efficient algorithm to construct wrappers that reduce the testing time for cores. Our wrapper design algorithm improves on earlier approaches by also reducing the TAM width required to achieve these lower testing times. We present new mathematical models for TAM optimization that use the core testing time values calculated by our wrapper design algorithm. We further present a new enumerative method for TAM optimization that reduces execution time significantly when the number of TAMs being designed is small. Experimental results are presented for an academic SOC as well as an industrial SOC.     

基于环形振荡器的TSV故障非接触测试方法

为避免传统的探针检测对硅通孔(TSV)造成损伤的风险,提出了一种非损伤的TSV测试方法.用TSV作为负载,通过环形振荡器测量振荡周期.TSV缺陷造成电阻电容参数的变化,导致振荡周期的变化.通过测量这些变化可以检测TSV故障,同时对TSV故障的不同位置引起的周期变化进行了研究与分析,利用最小二乘法拟合出通过周期来判断故障位置的曲线,同时提出预测模型推断故障电阻范围.测试结构是基于45 nm PTM COMS工艺的HSPICE进行设计与模拟,模拟结果表明,与同类方法相比,此方法在测试分辨故障的基础上对TSV不同位置的故障进行分析和判断,并能推断故障电阻范围.     

用于3D封装的带TSV的超薄芯片新型制作方法

提出了一种应用于3D封装的带有硅通孔(TSV)的超薄芯片的制作方法。具体方法为通过刻蚀对硅晶圆打孔和局部减薄,然后进行表面微加工,最后从硅晶圆上分离出超薄芯片。利用两种不同的工艺实现了TSV的制作和硅晶圆局部减薄,一种是利用深反应离子刻蚀(DRIE)依次打孔和背面减薄,另一种是先利用KOH溶液湿法腐蚀局部减薄,再利用DRIE刻蚀打孔。通过实验优化了KOH和异丙醇(IPA)的质量分数分别为40%和10%。这种方法的优点在于制作出的超薄芯片翘曲度相较于CMP减薄的小,而且两个表面都可以进行表面微加工,使集成度提高。利用这种方法已经在实验室制作出了厚50μm的带TSV的超薄芯片,表面粗糙度达到0.02μm,并无孔洞地电镀填满TSV,然后在两面都制作了凸点,在表面进行了光刻、溅射和剥离等表面微加工工艺。实验结果证实了该方法的可行性。     

基于云模型进化算法的硅通孔数量受约束的3D NoC测试规划研究

针对硅通孔(TSV)价格昂贵、占用芯片面积大等问题,该文采用基于云模型的进化算法对TSV数量受约束的3维片上网络(3D NoC)进行测试规划研究,以优化测试时间,并探讨TSV的分配对3D NoC测试的影响,进一步优化3D NoC在测试模式下的TSV数量。该方法将基于云模型的进化算法、小生境技术以及遗传算法的杂交技术结合起来,有效运用遗传、优胜劣汰以及保持群落的多样性等理念,以提高算法的寻优速度和寻优精度。研究结果表明,该算法既能有效避免陷入局部最优解,又能提高全局寻优能力和收敛速度,缩短了测试时间,并且优化了3D NoC的测试TSV数量,提高了TSV的利用率。     

Fault Modeling and Multi-Tone Dither Scheme for Testing 3D TSV Defects

This paper provides a new test technique for detecting defects in Through Silicon Via (TSV) in 3-D ICs and presents a substrate-dependent equivalent electrical model for TSVs. Process-related defects that affect the functional electrical performance of the TSV are identified, and fault models are developed for each individual defect. The fault models are integrated into the equivalent electrical model of the TSV for testing. Our test technique uses an RF carrier signal modulated with a multi-tone signal with added Gaussian white noise to synthesize the test stimulus; the peak-to-average ratio is measured as output response. We find a significant difference in peak-to-average ratio between defect-free and defective TSVs. Our test technique is very sensitive to small defects in these nanostructures, thereby identifying the defects with high accuracy.     

片上网络路由器的测试及其外壳旁路故障的诊断

目前采用IEEE 1500测试外壳的方法可以一定程度上解决NoC(Netword on Chip)路由器测试的问题,但当测试外壳的旁路出现一个以上的故障时,很可能导致一整条扫描链上的NoC路由器测试失败.针对该问题,本文通过提出一个深度优先最短路径算法得到从固定的扫描输入端到扫描输出端的最短路径,并通过提出的递归划分逐步求精法对路径进行筛选分块排序,构造多条扫描测试链将整个网络中的路由器分开测试.本文给出了测试外壳旁路故障的诊断和容错方法,使用节点分类测试方法实现对NoC路由器旁路故障的定位,并通过本文提出的测试外壳结构实现对故障旁路的容错.     

基于安全控制边界单元的IP核测试封装方法

为了解决测试信息传递的问题,IEEE组织推出了IEEE1500 IP(Intellectual Property)核测试封装标准以标准化口核测试接口.然而该标准给出的典型测试封装存在由测试数据扫描移人造成的不安全隐患.本文提出了一种基于安全控制边界单元的IP核测试封装方法.这种方法的核心思想是在典型的测试封装边界单元的...     

Test infrastructure design for mixed-signal SOCs with wrapped analog cores

Many system-on-chips (SOCs) today contain both digital- and analog-embedded cores. Even though the test cost for such mixed-signal SOCs is significantly higher than that for digital SOCs, most prior research in this area has focused exclusively on digital cores. We propose a low-cost test development methodology for mixed-signal SOCs that allows the analog and digital cores to be tested in a unified manner, thereby minimizing the overall test cost. The analog cores in the SOC are wrapped such that they can be accessed using a digital test access mechanism (TAM). We evaluate the impact of the use of analog test wrappers on area overhead and test time. To reduce area overhead, we present an analog test wrapper optimization technique, which is then combined with TAM optimization in a cost-oriented heuristic approach for test scheduling. We also demonstrate the feasibility of using analog wrappers by presenting transistor-level simulations for an analog wrapper and a representative core. We present experimental results for three SOCs from the ITC '02 test benchmarks that have been augmented with three analog cores: an I-Q transmit path pair and an audio CODEC path used in cellular phone applications.     

三维集成电路中TSV的热特性研究

基于Comsol Multiphysics平台,通过使用有限元仿真对三维集成电路的硅通孔(TSV)模型进行了热仿真分析。分别探究了TSV金属层填充材料及TSV的形状、结构、布局和插入密度对三维(3D)集成电路TSV热特性的影响。结果表明:TSV金属层填充材料的热导率越高,其热特性就越好,并且采用新型碳纳米材料进行填充比采用传统金属材料更能提高3D集成电路的热可靠性;矩形形状的TSV比传统圆形形状的TSV更有利于3D集成电路散热;矩形同轴以及矩形双环TSV相比其他结构TSV,更能提高TSV的热特性;TSV布局越均匀,其热特性越好;随着TSV插入密度的增加,其热特性越好,当插入密度达6%时,增加TSV的数目对TSV热特性的影响将大幅减小。     

基于热电耦合激励的TSV三维封装内部缺陷识别方法研究

由于硅通孔互连(Through Silicon Via,TSV)三维封装内部缺陷深藏于器件及封装内部,采用常规方法很难检测.然而TSV三维封装缺陷在热-电激励的情况下可表现出规则性的外在特征,因此可以通过识别这些外在特征达到对TSV三维封装内部缺陷进行检测的目的 .文章利用理论与有限元仿真相结合,对比了正常TSV与典型缺陷TSV的温度分布,发现了可供缺陷识别的显著差异.分析结果表明,在三种典型缺陷中,含缝隙TSV与正常TSV温度分布差异最小;其次为底部空洞TSV,差异最大的为填充缺失TSV.由此可知,通过检测热-电耦合激励下的TSV封装外部温度特征,可实现TSV三维封装互连结构内部缺陷诊断与定位.