Design of a memristor-based look-up table (LUT) for low-energy operation of FPGAs

This paper presents a scheme for designing a memristor-based look-up table (LUT) in which the memristors are connected in rows and columns. As the columns are isolated, the states of the unselected memristors in the proposed scheme are not affected by the WRITE/READ operations; therefore, the prevalent problems associated with nanocrossbars (such as the write half-select and the sneak path currents) are not encountered. Extensive simulation results of the proposed scheme are presented with respect to the WRITE and READ operations; its performance is compared with previous LUT schemes using memristors as well as SRAMs. It is shown that the proposed scheme is significantly better in terms of WRITE time and energy dissipation for both memory operations (i.e. WRITE and READ); moreover it is shown that the READ delay is nearly independent of the LUT dimension. Simulation using benchmark circuits for FPGA implementation show that the proposed LUT offers significant improvements also at this level.     

High resolution and low distortion digital look-up-table sinusoidal oscillators

We propose two new methods to reduce the spurious harmonic distortion of a digital sinusoidal signal generated using the look-up-table (LUT) method. Spurious harmonic distortion arises when we try to interpolate the value of a sample that is not present in the LUT. The first proposed method depends on a real time evaluation of the missing sample value without the need for any additional LUT length. The second proposed method requires an additional table and some real time processing to calculate the value of the interpolated sample. The two proposed methods are simulated and their performance is compared with that of the existing methods; namely direct LUT, linear interpolation and trigonometric interpolation. The simulation results show that our proposed methods are superior to both direct LUT and linear interpolation methods. Moreover, for practical table lengths, the performance of our proposed methods is of the same order as that of the trigonometric interpolation method.     

Stateful-NOR based reconfigurable architecture for logic implementation

Most commercial Field Programmable Gate Arrays (FPGAs) have limitations in terms of density, speed, configuration overhead and power consumption mostly due to the use of SRAM cells in Look-Up Tables (LUTs), configuration memory and programmable interconnects. Also, hardwired Application Specific Integrated Circuit (ASIC) blocks designed for high performance arithmetic circuits in FPGA reduce the area available for reconfiguration. In this paper, we propose a novel generalized hybrid CMOS-memristor based architecture using stateful-NOR gates as basic building blocks for implementation of logic functions. These logic functions are implemented on memristor nanocrossbar layers, while the CMOS layer is used for selection and connection of memristors. The proposed pipelined architecture combines the features of ASIC, FPGA and microprocessor based designs. It has high density due to the use of nanocrossbar layer and high throughput especially for arithmetic circuits. The proposed architecture for three input one output logic block is compared with conventional LUT based Configurable Logic Block (CLB) having the same number of inputs and outputs; which shows 1.82×area saving, 1.57×speedup and 3.63×less power consumption. The automation algorithm to implement any logic function using proposed architecture is also presented.     

On a Reduced‐Complexity Inner Decoder for the Davey‐MacKay Construction

The Davey‐MacKay construction is a promising concatenated coding scheme involving an outer 2^k‐ary code and an inner code of rate k/n, for insertion‐deletion‐substitution channels. Recently, a lookup table (LUT)‐based inner decoder for this coding scheme was proposed to reduce the computational complexity of the inner decoder, albeit at the expense of a slight degradation in word error rate (WER) performance. In this letter, we show that negligible deterioration in WER performance can be achieved with an LUT as small as 7·2^k+n–1, but no smaller, when the probability of receiving less than n–1 or greater than n+1 bits corresponding to one outer code symbol is at least an order of magnitude smaller than the WER when no LUT is used.     

An improved look-up table predistortion technique for HPA with memory effects in OFDM systems

It is well known that HPAs (High Power Amplifiers) are inherently nonlinear devices and many researches have focused on the predistortion for memoryless HPAs. However, memory effects of HPAs can no longer be ignored when communication systems have wider bandwidth. Memoryless predistortion techniques proposed previously seldom have satisfactory effectiveness for typical wideband applications such as OFDM (Orthogonal Frequency Division Multiplexing) systems. In this paper, an improved adaptive predistortion method called 2D LUT (2-dimension look-up table) with different accuracy levels is presented to linearize HPAs with memory effects. Simulation and experimental results show that 2D LUT implements excellent performance in mitigating the signal deterioration caused by memory effects, both rectifies the signal constellation distortion and suppresses the spectrum emission. Large scale matrix computation is also avoidable in these adaptive algorithms, which makes them feasible when a real-time system is necessary.     

Evaluating logic functionality of cascaded fracturable LUTs

Look Up Tables(LUTs) are the key components of Field-Programmable Gate Arrays(FPGAs). Many LUT architectures have been studied; nevertheless, it is difficult to quantificationally evaluate an LUT based architecture. Traditionally, dedicated efforts on specific modifications to the technology mapping tools are required for LUT architecture evaluation. A more feasible evaluation method for logic functionality is strongly required for the design of LUT architecture. In this paper, a mathematical method for logic functionality calculation is proposed and conventional and fracturable LUT architectures are analyzed. Furthermore, a cascaded fracturable LUT architecture is presented, which achieves twice logic functionality compared with the conventional LUTs and fracturable LUTs.     

温度对液晶波前校正器响应速度及LUT的影响研究

温度起伏会对液晶器件的相位调制特性、响应速度有影响,从而影响自适应光学系统中的液晶波前校正器的相位调制精度。针对该问题,本文研究了温度对512×512像素的硅基液晶波前校正器(LCOS)的LUT(look-up table)的影响,正是由于LUT的变化导致其相位调制特性不同;实验测量了不同温度下LCOS的时间和相位响应特性,由此计算了对应的LUT,利用最小二乘拟合方法对得到的数据进行拟合,给出了16～26℃范围内的关系式,利用此关系式可以获得该温度范围内不同温度下合理的LUT。我们在LCOS上施加闪耀光栅灰度图后,对不同LUT下入射光束的衍射效率分别进行测量,结果表明我们利用关系式内对应温度下的LUT取代LCOS中固定值的LUT方法可以克服温度的起伏带来的影响,提高LCOS的相位调制能力。本方法对于液晶器件在自适应光学、显示等领域的应用也有帮助。     

Adaptive digital/RF predistortion using a nonuniform LUT indexing function with built-in dependence on the amplifier nonlinearity

This paper reports on an integrated adaptive digital/RF predistorter using a nonuniform spaced lookup table (LUT) and in-phase/quadrature (I/Q) RF vector multiplier (VM). The LUT contents are directly deduced from the baseband input and output signals of the power amplifier (PA). In addition, a new nonlinear indexing function of the predistortion LUT with built-in dependence on the PA nonlinearity is proposed. This function is made to be robust to the input signal statistics. A comparison of this new indexation method with conventional approaches, namely, power and logarithmic power indexation functions, is carried out. The superiority of the proposed scheme is demonstrated in particular for class-AB amplifiers where the gain of the PA varies over the whole input range of the drive signal. The measured output spectrum of a linearized 90-W peak lateral double-diffused metal-oxide-semiconductor PA reveals a significant reduction of the power emission at the adjacent channels of approximately 15 dB under IS95, single-carrier, and multicarrier wide-band code-division multiple-access signals. The experimental evaluation is carried out using an RF/digital predistorter prototype that mainly includes an envelope detector, a linear I/Q RF VM, field-programmable gate array and digital signal processor, and fast analog/digital and digital/analog converters.     

Memristor-based approximate matrix multiplier

The parallel structure of matrix multipliers makes them fascinating candidates to benefit from memristors’ high density architecture. This paper first explains a memristor-based analog vector–matrix multiplier suitable for approximate computing. According to the existence of fast and efficient converters, namely, DACs and ADCs, in the field of approximate computing and the programmability of memristors, the presented vector–matrix multiplier is combined with digital circuits which it leads to a matrix–matrix multiplier as an extension. In this work, opamps’ characteristics such as power and speed, distribution of matrix elements, and memristors’ faults have been considered and their effects on performance, accuracy, and efficiency of the proposed multiplier have been analyzed. Also, a new structure for handling negative numbers has been proposed. All the circuits have been simulated using “Ngspice mixed-signal circuit simulator” in C++ programming environment. The simulation results revealed that the multiplier’s analog core brought gains in terms of performance and energy when acceptable ranges of inaccuracies in results could be tolerated.     

两步双向查找表预测的高光谱图像无损压缩

提出一种基于两步双向查找表预测的高光谱图像无损压缩算法。将谱段内预测和谱间预测有效地结合,去除了高光谱图像强的谱间相关性。根据高光谱图像特点,首先,在光谱线的第1谱段图像采用JPEG-LS中值预测器进行谱段内预测,其它谱段图像采用谱间预测。谱间预测采用两步双向预测算法,第1步预测,采用一种双向四阶预测器,利用该预测器得到参考预测值;第2步预测,采用一种8级查表(LUT)搜索预测算法,得出8个LUT预测值。然后,将参考预测值与其比较得出最终的预测值。最后,将预测差值进行熵编码。实验结果表明,本文算法的平均压缩比达到3.05bpp(bits per pixel),与传统高光谱图像无损压缩算法比较,平均压缩比提高了0.14～2.91bpp,有效提高了高光谱图像无损压缩比低的问题。     

具有高资源利用率特征的改进型查找表电路结构与优化方法

该文着重研究了FPGA芯片中核心模块基本可编程逻辑单元(BLE)的电路结构与优化设计方法,针对传统4输入查找表(LUT)进行逻辑操作和算术运算时资源利用率低的问题,提出一种融合多路选择器的改进型LUT结构,该结构具有更高面积利用率;同时提出一种对映射后网表进行统计的评估优化方法,可以对综合映射后网表进行重新组合,通过预装箱产生优化后网表;最后,对所提结构进行了实验评估和验证。结果表明:与Intel公司Stratix系列FPGA相比,采用该文所提优化结构,在MCNC电路集和VTR电路集下,资源利用率平均分别提高了10.428% 和 10.433%,有效提升了FPGA的逻辑效能。     

Inverse halftoning algorithm using edge-based lookup table approach

The inverse halftoning algorithm is used to reconstruct a gray image from an input halftone image. Based on the recently published lookup table (LUT) technique, this paper presents a novel edge-based LUT method for inverse halftoning which improves the quality of the reconstructed gray image. The proposed method first uses the LUT-based inverse halftoning method as a preprocessing step to transform the given halftone image to a base gray image, and then the edges are extracted and classified from the base gray image. According to these classified edges, a novel edge-based LUT is built up to reconstruct the gray image. Based on a set of 30 real training images with both low- and high-frequency contents, experimental results demonstrated that the proposed method achieves a better image quality when compared to the currently published two methods, by Chang et al. and Mes$80e and Vaidyanathan.     

Exploiting Inherent Parallelisms for Accelerating Linear Hough Transform

Accelerating Hough transform in hardware has been of interest due its popularity in real-time capable image processing applications. In most existing linear Hough transform architectures, an m times medge map is serially read for processing, resulting in a total computation time of at least m² cycles. In this paper, we propose a novel parallel Hough transform computation method called the Additive Hough transform (AHT), wherein the image is divided using a k times k grid to reduce the total computation time by a factor of k². We have also proposed an efficient implementation of the AHT consisting of a look-up table (LUT) and two-operand adder arrays for every angle. Techniques to condense the LUT size have also been proposed to further reduce area utilization by as much as 50%. Our investigations based on employing an 8 times 8 grid shows a 1000 times speedup compared to existing architectures for a range of image sizes. Area-time trade-off analysis has been presented to demonstrate that the area-time product of the proposed AHT-based implementation is at least 43% lower than other implementations reported in the literature. We have also included and characterized a hierarchical addition step in order to generate a global accumulation space equivalent to that of the conventional HT. It is shown that the proposed implementation with the hierarchical addition step remains superior to other methods in terms of both performance and area-time product metrics. Finally, we show that the proposed solution is equally efficient when applied on rectangular images.     

An accurate model of domain-wall-based spintronic memristor

Spintronic memristors are promising devices that can be used in various applications such as memory chips and neuromorphic systems. The spintronic memristor combines the non-volatility advantage of resistive memristors, and the good scalability, and radiation hardness of spin-transfer torque magnetic devices. In addition, spintronic memristors can benefit from the maturity of integrating magnetic devices on top of CMOS devices. Current models of spintronic memristor only provide a similar version of the linear ion drift model of resistive memristors, which offers a simplified model, but with low accuracy and without enough linking to the device's physical parameters. In this paper, an accurate model of domain-wall- based spintronic memristor based on Landau-Lifshitz-Gilbert-Slonczewski (LLGS) equation is proposed. The proposed model provides a more accurate dynamical behavior by using the LLGS equation, and better relation to the device's physical parameters. It also uses the required equations that cover different types and geometries of spintronic memristors. The effect of the thermal fluctuations on device's parameters is also included into the model. The model uses the theory of domain-wall motion to explain the behavior of the device. Furthermore, a Verilog-A model is developed in order be compatible with IC CAD tools.     

PD中重频下主瓣杂波特性及抑制滤波器设计

针对中重频PD雷达应用背景,设计了一种主瓣杂波抑制滤波器。对主瓣杂波在实际情况下的参数特点进行了详细分析,得出杂波强度、带宽和功率与俯仰角的对应关系,据此提出了采用查表法设计主瓣杂波抑制滤波器方法;该方法克服了对消器和AMTI滤波器的不足,能有效改善杂波抑制性能,其算法存储容量和实时性满足设计要求,具有良好的工程应用价值。     

Digital sinusoidal oscillators with high frequency resolution and low harmonic distortion

In this paper, we propose two new techniques to significantly improve the frequency resolution of a digital look-up-table (LUT) tunable sinusoidal oscillator. The proposed techniques are based on storing and reading the sine and cosine components of two sinusoidal functions that are not harmonically related and then evaluating the sine or cosine of the phase difference. The proposed techniques are shown to be very efficient in increasing the effective table length and, hence, the frequency resolution of the oscillator. Further performance improvement can be achieved by using interpolation methods as demonstrated. Simulation results verify the analytical results and show that the total harmonic distortion of the generated sinusoid is of the same order as that of the conventional digital LUT tunable sinusoidal oscillator.     

Tree-structured method for LUT inverse halftoning and for imagehalftoning

The authors previously proposed a look up table (LUT) based method for inverse halftoning of images. The LUT for inverse halftoning is obtained from the histogram gathered from a few sample halftone images and corresponding original images. Many of the entries in the LUT are unused because the corresponding binary patterns hardly occur in commonly encountered halftones. These are called nonexistent patterns. In this paper, we propose a tree structure which will reduce the storage requirements of an LUT by avoiding nonexistent patterns. We demonstrate the performance on error diffused images and ordered dither images. Then, we introduce LUT based halftoning and tree-structured LUT (TLUT) halftoning. Even though the TLUT method is more complex than LUT halftoning, it produces better halftones and requires much less storage than LUT halftoning. We demonstrate how the error diffusion characteristics can be achieved with this method. Afterwards, our algorithm is trained on halftones obtained by direct binary search (DBS). The complexity of TLUT halftoning is higher than the error diffusion algorithm but much lower than the DBS algorithm. Also, the halftone quality of TLUT halftoning increases if the size of the TLUT gets bigger. Thus, the halftone image quality between error diffusion and DBS will be achieved depending on the size of the tree-structure in the TLUT algorithm     

用查表法快速实现二维8×8离散余弦逆变换的研究

提出一种基于查表法的二维8×8离散余弦逆变换(2D 8×8 IDCT)的快速算法,其查找表LUT(Look-Up Table)结构的设计是基于二维8×8 DCT的基本图像.利用两种技术减小查找表长度:①利用基本图像的对称特性;②通过对离散余弦正变换(DCT)和量化过程的分析,推导出每个量化后DCT系数的取值范围.使得查找表只有10.9746K项数据,若量化矩阵具有对称性q(u,v)=q(v,u),LUT的长度还可减少近半.新算法利用查表法消除IDCT中乘法运算,并利用图像数据的特点和基本图像的对称特性大大减少加法次数,提高了计算速度.以多幅标准图像为样本数据进行实验,结果表明:新算法实现2D 8×8 IDCT运算平均只需加法182次.与当前运算量最小的Feig快速算法做比较,新算法避免了乘法,所需加法次数也降低了约15%.     

Digital predistorter with improving index accuracy of lookup table based on FPGA

In this paper, a method of function approximation for improving index accuracy of the lookup table (LUT) of digital predistortion (DPD) is proposed to obtain more accurate linearization. The algorithm utilizes approximation of the LUT with the method of Taylor Series. The power values of forward signals are divided into integers and decimals, and the corresponding LUTs are indexed respectively. The index predistortion values of forward signals are approximated by Taylor series, which improves the index accuracy of LUT significantly. Experiment shows that the performance of a DPD system is improved.