NoC边界扫描测试系统硬件设计

为了解决内部结构日益复杂的片上网络系统故障测试的问题,在研究3×3 2D-Mesh体系结构的NoC系统、边界扫描测试技术和资源节点故障类型的基础上,以FPGA为核心器件设计边界扫描测试系统。完成了数据采集、频率计、放大器、SRAM、IEEE1500 Wrapper等资源节点电路以及资源节点边界扫描链路的接口电路设计,并利用测试软件、信号发生器、万用表和数字示波器,通过边界扫描链路完成对整个硬件设计的测试。测试结果表明该设计性能稳定,为研究NoC系统的边界扫描测试技术提供了硬件平台。     

嵌入式逻辑分析仪在FPGA设计中的应用

设计和验证超高密度FPGA的方法是采用逻辑分析仪、示波器和总线分析仪,通过测试头和连接器把信号送到仪器上。随着FPGA设计复杂度的增加,传统的测试方法受到局限。在FPGA内部嵌入逻辑分析核,构成一种嵌入式逻辑分析仪,对FPGA器件内部所有的信号和节点进行测试,这一方法同样可以达到FPGA开发中硬件调试的要求,并且具有无干扰、便于升级和使用方便等优点。SignalTapⅡ正是这样一种嵌入式逻辑分析仪,本文详细介绍了其在调试FPGA时的具体方法和步骤。     

Circuit design of a novel FPGA chip FDP2008

A novel FPGA chip FDP2008 (Fudan Programmable Logic) has been designed and implemented with the SMIC 0.18μm CMOS logic 1P6M process. The new design method means that the configurable logic block can be configured as distributed RAM and a shift register. A universal programmable routing circuit is also presented; by adopting offset lines, complementary hanged end-lines and MUX + Buffer routing switches, the whole FPGA chip is highly repeatable, and the signal delay is uniform and predictable over the total chip. A standard configuration interface SPI is added in the configuration circuit, and a group of highly sensitive amplifiers is used to magnify the read back data. FDP2008 contains 20 × 30 logic TILEs, 200 programmable IOBs and 10 × 4 kbit dual port block RAMs. The hardware software cooperation test shows that FDP2008 works correctly and efficiently.     

虚拟试验系统协议转换模块研制

哈尔滨工业大学自动化测试与控制研究所研发了试验和训练体系结构HIT-TENA平台,用于搭建虚拟试验系统;为了将靶场实物资源接入该系统,研制了基于PCI总线和1553B总线的协议转换模块。采用DSP+FPGA的硬件结构,利用FPGA实现了并行协议帧头识别,利用DSP实现了协议转换。测试表明,该模块能完成协议转换,并将延时降低到1 ms以内,解决了试验设备接入虚拟试验系统时转换效率低下、延时较大等问题。     

基于DSP和FPGA的电视观瞄系统设计

提出了一种基于ADSP2183和EP2S30F484的电视观瞄系统的设计与实现方案。系统以FPGA为处理核心,实现红外数字视频信号的实时图像处理,DSP实现了部分的图像处理算法和FPGA的控制逻辑,并响应中断,实现数据通信和存储。详细讨论了DSP和FPGA的硬件设计,通信接口以及FPGA的配置方案,并介绍了DSP的程序流程。经多项实验表明:此系统实时性良好、工作稳定可靠,达到了电视观瞄系统设计要求。     

基于CPCI和光纤接口的数据采集卡设计与实现

设计了一套基于CPCI总线,PCI9054桥接芯片和可编程逻辑器件（FPGA）的高速数据采集卡。FPGA作为本地主控芯片,根据工控机经PCI9054转发的采集命令,通过光纤接口实现与雷达接收机的通信。采用高速RAM缓存数据,采集的接收机测试数据的分析结果可在工控机上显示,从而实现了对雷达接收机性能的快速测试。该采集卡具有较强的通用性和可扩展性,详细介绍了高速数据采集卡的组成和工作原理、硬件设计。     

FPGA电路动态老化技术研究

近年来,随着FPGA电路在军工和航天领域的广泛应用,用户对FPGA电路的可靠性要求也越来越高。在集成电路的可靠性评估试验中,动态老化试验是最重要的试验之一,FPGA动态老化技术的实现可以提高FPGA电路的可靠性。文章通过研究FPGA电路内部结构和功能模块,讨论FPGA电路加载配置过程的原理和流程,通过对动态老化和静态老化的对比试验和结果分析,研究出FPGA电路动态老化试验方法,并在工程实践中得到了成功实现和应用。     

System fault-tolerance analysis of COTS-based satellite on-board computers

Fault-tolerance analysis reveals possible system behavior under the influence of faults. Such analysis is essential for satellites where faults might be caused by space radiation and autonomous recovery is needed. In this paper we present a statistical simulation approach for fault-tolerance analysis of satellite On-Board Computers (OBCs) that are based on Commercial Off-The-Shelf (COTS) components. Since the logic level of COTS electronics is unknown to satellite designers, a new higher-level fault-tolerance analysis is required. We propose such technique that relies on OBC modeling and fault modeling, based on the modeling principle of Single-Event Upsets (SEUs). For the first time we can compare the efficiency of fault-tolerance techniques implemented in software and Field-Programmable Gate Array (FPGA). In addition, our approach enables to analyze system fault-tolerance at early development stages. In a case study the approach is applied to an OBC with a Microsemi SmartFusion SoC, that executes a satellite attitude control algorithm. The gained statistical simulation results enabled 50% reduction in the hardware overhead of the implemented memory scrubbing technique without loss in fault-tolerance. Our method revealed critical fault-tolerance drawbacks of the initial system design that could have lead to satellite mission failure.     

Online Fault Tolerance for FPGA Logic Blocks

Most adaptive computing systems use reconfigurable hardware in the form of field programmable gate arrays (FPGAs). For these systems to be fielded in harsh environments where high reliability and availability are a must, the applications running on the FPGAs must tolerate hardware faults that may occur during the lifetime of the system. In this paper, we present new fault-tolerant techniques for FPGA logic blocks, developed as part of the roving self-test areas (STARs) approach to online testing, diagnosis, and reconfiguration . Our techniques can handle large numbers of faults (we show tolerance of over 100 logic faults via actual implementation on an FPGA consisting of a 20 times 20 array of logic blocks). A key novel feature is the reuse of defective logic blocks to increase the number of effective spares and extend the mission life. To increase fault tolerance, we not only use nonfaulty parts of defective or partially faulty logic blocks, but we also use faulty parts of defective logic blocks in nonfaulty modes. By using and reusing faulty resources, our multilevel approach extends the number of tolerable faults beyond the number of currently available spare logic resources. Unlike many column, row, or tile-based methods, our multilevel approach can tolerate not only faults that are evenly distributed over the logic area, but also clusters of faults in the same local area. Furthermore, system operation is not interrupted for fault diagnosis or for computing fault-bypassing configurations. Our fault tolerance techniques have been implemented using ORCA 2C series FPGAs which feature incremental dynamic runtime reconfiguration     

基于测试系统的FPGA逻辑资源的测试

FPGA在许多领域已经得到广泛应用,其测试问题也显得越来越突出。文章针对基于SRAM结构FPGA的特点,以Xilinx公司的XC4000系列芯片为例,利用检测可编程逻辑资源的多逻辑单元(CLB)混合故障的测试方法,阐述了如何在BC3192V50测试系统上实现FPGA的在线配置以及功能和参数测试。它是一种基于测试系统的通用的FPGA配置和测试方法。     

Coordinated Control of DFIG's Rotor and Grid Side Converters During Network Unbalance

This paper proposes a coordinated control of the rotor side converters (RSCs) and grid side converters (GSCs) of doubly-fed induction generator (DFIG) based wind generation systems under unbalanced voltage conditions. System behaviors and operations of the RSC and GSC under unbalanced voltage are illustrated. To provide enhanced operation, the RSC is controlled to eliminate the torque oscillations at double supply frequency under unbalanced stator supply. The oscillation of the stator output active power is then cancelled by the active power output from the GSC, to ensure constant active power output from the overall DFIG generation system. To provide the required positive and negative sequence currents control for the RSC and GSC, a current control strategy containing a main controller and an auxiliary controller is analyzed. The main controller is implemented in the positive (dq)⁺ frame without involving positive/negative sequence decomposition whereas the auxiliary controller is implemented in the negative sequence (dq)^- frame with negative sequence current extracted. Simulation results using EMTDC/PSCAD are presented for a 2 MW DFIG wind generation system to validate the proposed control scheme and to show the enhanced system operation during unbalanced voltage supply.     

基于FPGA的32位ALU的设计与实现

针对FPGA运算速度快,设计灵活的特点,提出了一种新颖的利用可编程逻辑器件FP-GA和硬件描述语言VHDL实现的功能齐全的32位ALU的方法.该ALU具备4种算术运算,9种逻辑运算,4种移位运算以及比较、求补、奇偶校验等共20种运算.采用层次化设计,给出了ALU的主要子模块,各模块均占用了较少的逻辑资源（LE）,实现了节省资源与速度提升.通过QuartusⅡ9.1进行编译,Modelsim6.5SE进行仿真,仿真结果与预期结果一致,将设计下载到Altera公司的EP2C35F484C6 FPGA中进行验证,证实了设计的可行性.实验结果表明,采用基于FPGA技术设计运算器灵活易修改,提高了设计效率.     

RAPID PROTOTYPING - Area efficient FIR filters for high speed FPGA implementation

A new algorithm that synthesises multiplier blocks with low hardware requirement suitable for implementation as part of full-parallel finite impulse response (FIR) filters is presented. Although the techniques in use are applicable to implementation on application-specific integrated circuit (ASIC) and Structured ASIC technologies, analysis is performed using field programmable gate array (FPGA) hardware. Fully pipelined, full-parallel transposed-form FIR filters with multiplier block were generated using the new and previous algorithms, implemented on an FPGA target and the results compared. Previous research in this field has concentrated on minimising multiplier block adder cost but the results presented here demonstrate that this optimisation goal does not minimise FPGA hardware. Minimising multiplier block logic depth and pipeline registers is shown to have the greatest influence in reducing FPGA area cost. In addition to providing lower area solutions than existing algorithms, comparisons with equivalent filters generated using the distributed arithmetic technique demonstrate further area advantages of the new algorithm     

基于门控结构的低功耗扫描测试方案

针对芯片测试功耗过高,严重影响芯片的良率的问题,提出了门控扫描时钟方法和门控组合逻辑方法相结合的测试方案来降低芯片测试功耗。采用该测试方案,使用Synopsys公司的DFT Compiler软件,完成了一款电力网载波通信芯片的可测性设计。结果表明,该测试方案在不降低响测试覆盖率和不增加测试时间的前提下,最终将测试功耗降低了37.3%。该测试方案能够快速有效地降低芯片测试功耗,具有广泛的应用价值。     

Reduced Memory and Low Power Architectures for CORDIC-based FFT Processors

This paper presents a pipelined, reduced memory and low power CORDIC-based architecture for fast Fourier transform implementation. The proposed algorithm utilizes a new addressing scheme and the associated angle generator logic in order to remove any ROM usage for storing twiddle factors. As a case study, the radix-2 and radix-4 FFT algorithms have been implemented on FPGA hardware. The synthesis results match the theoretical analysis and it can be observed that more than 20% reduction can be achieved in total memory logic. In addition, the dynamic power consumption can be reduced by as much as 15% by reducing memory accesses.     

A Stochastic-Based FPGA Controller for an Induction Motor Drive With Integrated Neural Network Algorithms

This paper applies stochastic theory to the design and implementation of field-oriented control of an induction motor drive using a single field-programmable gate array (FPGA) device and integrated neural network (NN) algorithms. Normally, NNs are characterized as heavily parallel calculation algorithms that employ enormous computational resources and are less useful for economical digital hardware implementations. A stochastic NN structure is proposed in this paper for an FPGA implementation of a feedforward NN to estimate the feedback signals in an induction motor drive. The stochastic arithmetic simplifies the computational elements of the NN and significantly reduces the number of logic gates required for the proposed NN estimator. A new stochastic proportional-integral speed controller is also developed with antiwindup functionality. Compared with conventional digital controls for motor drives, the proposed stochastic-based algorithm enhances the arithmetic operations of the FPGA, saves digital resources, and permits the NN algorithms and classical control algorithms to be easily interfaced and implemented on a single low-complexity, inexpensive FPGA. The algorithm has been realized using a single FPGA XC3S400 from Xilinx, Inc. A hardware-in-the-loop (HIL) test platform using a Real Time Digital Simulator is built in the laboratory. The HIL experimental results are provided to verify the proposed FPGA controller.     

Automatic Design of Reconfigurable Domain-Specific Flexible Cores

Reconfigurable hardware is ideal for use in systems-on-a-chip (SoC), as it provides both hardware-level performance and post-fabrication flexibility. However, any one architecture is rarely equally optimized for all applications. SoCs targeting a specific set of applications can greatly benefit from incorporating customized reconfigurable logic instead of generic field-programmable gate-array (FPGA) logic. Unfortunately, manually designing a domain-specific architecture for every SoC would require significant design time. Instead, this paper discusses our initial efforts towards creating a reconfigurable hardware generator capable of automatically creating flexible, yet domain-specific, designs. Our tests indicate that our generated architectures are more than 5times smaller than equivalent FPGA implementations and nearly as area-efficient as standard cell designs. We also use a novel technique employing synthetic circuit generation to demonstrate the flexibility of our architecture generation techniques.     

Design and implementation of SVM OTPC searching based on Shared Dot Product Matrix

In this paper, we proposed a FPGA implementation architecture for SVM classifier. The architecture is based on the proposed Shared Dot Product Matrix (SDPM) method which computes and stores the dot product of all training data before SVM searching process. We implemented the proposed method by software simulation and hardware implementation. The software simulation of SDPM method achieves twice the speed of LIBSVM, which is one of the most popular SVM implementation libraries. This acceleration mainly results from the reduction of repeat Kernel function calculation. Then the hardware software collaboration architecture for SDPM is also proposed in this paper. Results show that the proposed architecture achieves approximately 30 times faster searching speed compared with LIBSVM.