AC floating body effects in partially depleted floating body SOInMOS operated at elevated temperature: an analog circuitprospective

AC floating body effects in PD SOI nMOSFETs operated at high temperature are investigated. Both source/body and drain/body junction diode characteristics are greatly influenced by temperature, significantly impacting the ac kink effect as well its low-frequency (LF) noise characteristics. This is especially true for the pre-dc kink operation at high temperature. The increase of junction thermal generation current becomes an important body charging source and induces the LF Lorentzian-like excess noise     

Modeling for floating body effects in fully depleted SOI MOSFETs

A model based on SOI MOSFET and BJT device theories is developed to describe the current kink and breakdown phenomena in thin-film SOI MOSFET drain-source current-voltage characteristics operated in strong inversion. The modulation of MOSFET current by raised floating body potential is discussed to provide an insight for understanding the suppression of current kink in fully depleted thin-film SOI devices. The proposed analytical model successfully simulates the drain current-voltage characteristics of thin-film SOI n-MOSFETs fabricated on SIMOX wafers     

Floating body induced pre-kink excess low-frequency noise insubmicron SOI CMOSFET technology

The well-known post-kink Lorentzian-like noise overshoot has been empirically correlated to the ac kink effect in the SOI CMOSFET in the past. This work demonstrates the existence of a 1/f² excess noise spectrum (<100 Hz) superimposed upon 1/f noise in partially depleted (PD) floating body SOI CMOS when devices are biased in the pre-kink region (before the dc kink onset voltage). While the impact ionization phenomenon is negligible in the pre-kink region, the new observed pre-kink excess noise provides a new insight into the body voltage instability and current fluctuation in the SOI CMOSFET     

Comprehensive study on low-frequency noise characteristics insurface channel SOI CMOSFETs and device design optimization for RF ICs

Low-frequency (LF) noise, a key figure-of-merit to evaluate device technology for RF systems on a chip, is a significant obstacle for CMOS technology, especially for partially depleted (PD) silicon-on-insulator (SOI) CMOS due to the well-known kink-induced noise overshoot. While the dc kink effect can be suppressed by either using body contact technologies or shifting toward fully depleted (FD) operation, the noise overshoot phenomena still resides at high frequency for either FD SOI or poor body-tied (BT) SOI CMOSFETs. In this paper, floating body-induced excess noise in SOI CMOS technology is addressed, including the impact from floating body effect, pre-dc kink operation, and gate overdrive, followed by the proposal of a universal LF excess noise model. As the physical mechanism behind excess noise is identified, this paper concludes with the suggestion of a device design methodology to optimize LF noise in SOI CMOSFET technology     

AC behavior of gate-induced floating body effects in ultrathin oxide PD SOI MOSFETs

In this letter we present for the first time an ac analysis of the gate-induced floating body effects (GIFBE) occurring in ultrathin gate oxide partially depleted (PD) silicon-on-insulator (SOI ) MOSFETs due to tunneling gate current. A simple equivalent circuit is proposed, which indicates that the ac behavior of GIFBE is related to the small-signal voltage variations of the floating body region. It also shows that due to the high impedance seen by the body region toward the external nodes, the GIFBE frequency dependence is characterized by a very low cut off frequency (< a few kilohertz), which is consistent with experimental data and circuit simulations performed with BSIMSOI.     

Transient behavior of the kink effect in partially-depleted SOIMOSFET's

The behavior of transients in the drain current of partially-depleted (PD) SOI MOSFET's down to L_eff=0.2 μm is examined as a function of drain bias, gate pulses of varying magnitude (V_GS), pulse duration, and pulse frequency. At fixed V_DS, the gate is pulsed to values ranging from 0.1 V above V_T to V_GS=V_DS. A slow transient is seen when the drain is biased at a V_DS where the current kink is observable. This slow transient can be on the order of microseconds depending on the relative magnitude of the impact ionization rate. For short times after the pulse edge or for very short pulses at low frequencies, it is shown that the subthreshold drain current value can be very different from the corresponding DC, and that the kink characteristic of PD MOSFET's disappears. However, the kink values can be approached when the pulse frequency and/or duration applied to the gate is increased, due to the latent charge maintained in the floating body at higher frequencies. No transient current effects were observed in fully-depleted SOI MOSFET's     

AC floating-body effects in submicron fully depleted (FD) SOInMOSFETs and the impact on analog applications

We report the impact of submicron fully depleted (FD) SOI MOSFET technology on device AC characteristics and the resultant effects on analog circuit issues. The weak DC kink and high frequency AC kink dispersion in FD SOI still degrade circuit performance in terms of distortion and low-frequency noise requirements. These issues raise concerns about FD devices for mixed-mode applications. Therefore, further device optimization such as source/drain engineering is still necessary to solve the aforementioned issues for FD SOI. On the other hand, partially depleted SOI MOSFET with body contact structures provide an alternative technology for RF/baseband analog applications     

部分耗尽SOI MOSFET中的浮体效应

介绍了部分耗尽SOI MOSFET中的浮体效应;简要描述了浮体效应的物理机制、测试结果,以及减小浮体效应的方法;同时,给出了在有体接触的情况下出现kink效应的测试结果.     

SOI MOSFET with buried body strap by wafer bonding

Although the buried oxide in the silicon-on-insulator (SOI) MOSFET makes possible higher performance circuits, it is also responsible for various floating body effects, including the kink effect, drain current transients, and history dependence of output characteristics. It is difficult to incorporate an effective contact to the body because of limitations imposed by the SOI structure. One candidate, which maintains device symmetry, is the lateral body contact. However, high lateral body resistance makes the contact effective only in narrow width devices. In this work, a buried lateral body contact in SOI is described which consists of a low-resistance polysilicon strap running under the MOSFET body along the device width. MOSFET's with effective channel length of 0.17 μm have been fabricated incorporating this buried body strap, showing improved breakdown characteristics. Low leakage of the source and drain junctions demonstrates that the buried strap is compatible with deep submicron devices. Device modeling and analysis are used to quantify the effect of strap resistance on device performance. By accounting for the lateral resistance of the body, the model can be used to determine the maximum allowable device width, given the requirement of maintaining an adequate body contact     

Phase noise characteristics associated with low-frequency noise insubmicron SOI MOSFET feedback oscillator for RF IC's

Phase noise in silicon-on-insulator (SOI) MOSFET feedback oscillators for RF IC applications is investigated. The observed correlation between the oscillator's high frequency phase noise and the transistor's low-frequency noise characteristics demonstrates that the phase noise overshoot still exists in partially-depleted (PD) floating body SOI nMOS Colpitts oscillators. These results suggest that kink-induced effects associated with low-frequency components of the signal are upconverted into the ideally kink-free high frequency domain operation mode of PD floating body SOI oscillators     

Clarification of floating-body effects on drive current and shortchannel effect in deep sub-0.25 μm partially depleted SOIMOSFETs

We point out for the first time that floating-body effects cause the reduction of the saturation drive current in partially depleted (PD) Sol MOSFETs. It is demonstrated that when the channel concentration of the SOI MOSFETs is set higher in order to suppress the increase of the off current caused by floating-body effects, the drive current decreases due to the large body effect. In the conventional SOI structure where the source-drain junction is in contact with the buried oxide, the 0.18 μm floating PD SOI MOSFET suffers around 17% decrease in the drive current under the same threshold voltage (V_th) in comparison with body-fixed one. However, floating ID SOI MOSFETs show smaller V_th-roll-off. Further considering the short channel effect down to the minimum gate length of 0.16 μm, the current decrease becomes 6%. Also, we propose a floating PD SOI MOSFET with shallow source-drain junction (SSD) structure to suppress the floating-body effects. By using the SSD structure, we confirmed an increase in the drive current     

On the performance advantage of PD/SOI CMOS with floating bodies

The performance advantage of floating-body (FB) partially depleted (PD) SOI CMOS technology is analyzed via device/circuit simulations, with emphasis on providing insight into the physical mechanisms underlying the advantage. Comparisons of predicted propagation delay of contemporary and scaled FB PD/SOI CMOS, including hysteresis, with those of the bulk-Si and body-tied-to-source/SOI counterparts, all with controlled off-state current, are made, and the impact of junction capacitance, the kink effect, and capacitive-coupling effects are quantified. Scaling the technologies is shown to diminish the performance advantage of FB PD/SOI CMOS, but this tendency can be mitigated by typically elevated operating temperatures, stacked-transistor logic, and device-design optimization     

Direct tunneling-induced floating-body effect in 90-nm pseudo-kink-free PD SOI pMOSFETs with DTMOS-like behavior and low input power consumption

This paper reports the investigation of the direct tunneling-induced floating-body effect in 90-nm H-gate floating body partially depleted (PD) silicon-on-insulator (SOI) pMOSFETs with dynamic-threshold MOS (DTMOS)-like behavior and low input power consumption. Based on this paper, with the decrease of the gate-oxide thickness, the direct-tunneling current will dominate the floating body potential of H-gate PD SOI pMOSFETs, which makes the floating body potential highly gate voltage dependent like DTMOS behavior with a larger drain current. However, the input power consumption is still kept lower. Simultaneously, the highly gate voltage dependent direct-tunneling current will reduce the influence of the impact ionization current on the neutral region with a higher kink onset-voltage. It contributes to the pseudo-kink-free phenomenon in 90-nm H-gate floating body PD SOI pMOSFETs.     

Empirical correlation between AC kink and low-frequency noiseovershoot in SOI MOSFETs

Low-frequency (LF) noise overshoot has been empirically correlated with the frequency dependence of the kink effect in floating body SOI MOSFETs. Based on the correlation between these unique ac characteristics in SOI, a new mechanism is proposed to explain the well-known kink-related noise overshoot. Also, device solutions for suppressing LF noise overshoot will be discussed     

Physical noise modeling of SOI MOSFETs with analysis of theLorentzian component in the low-frequency noise spectrum

The implementation of a general physics-based compact model for noise in silicon-on-insulator (SOI) MOSFETs is described. Good agreement is shown between model-predicted and measured low-frequency (LF) noise spectra. In particular, the behavior of an excess Lorentzian component that dominates the LF noise spectra of SOI MOSFETs is investigated. Shot noise associated with the generation and removal (via recombination or a body contact) of body charge is shown to underlie the behavior of the Lorentzian in both floating-body and body-tied-to-source SOI MOSFET's operating under partially depleted or “mildly” fully depleted conditions; the Lorentzian is suppressed when the body is “strongly” fully depleted. Good physical insight distinguishes the behavior of the Lorentzian components in all these devices, and predicts the occurrence of additional excess noise sources in future scaled technologies. Simple analytic expressions that approximate the full model are derived to provide the insight     

Simulation of partially and near fully depleted SOI MOSFET devices and circuits using SPICE compatible physical subcircuit model

A four-terminal physical subcircuit model for floating body (FB) partially depleted (PD) and near fully depleted (near FD) SOI CMOS devices is presented. The model accounts for the unique characteristics of PD devices associated with the drain (V_ds) induced floating body effects. Unlike other models, the proposed circuit model accounts physically for the back MOSFET device, and accurately predicts the bias dependence of the current kink in near FD devices. It allows for proper capacitance scaling and more accurate simulations related to the front and back oxides/channels. Self-heating effects related to the low thermal conductivity of the back oxide are also included. The circuit model is SPICE compatible and provides insights for understanding optimal device design needs for high performance. A simple technique for extracting the model parameters is described. The model is verified by the good agreement of the simulation results with the experimental data. The predictive capabilities of the subcircuit model are supported by circuit level simulation examples.     

The effect of body contact series resistance on SOI CMOS amplifierstages

This paper examines some implications for analogue design of using body ties as a solution to the problem of floating body effects in partially-depleted (PD) SOI technologies. Measurements on H-gate body-tied structures in a 0.7-μm SOI process indicate body-tie series resistances increasing into the MΩ region. Both circuit simulation and measurement results reveal a delayed but sharper kink effect as this resistance increases. The consequences of this effect are shown in the context of a simple amplifier configuration, resulting in severe bias-dependent degradation in the small signal gain characteristics as the body-tie resistance enters the MΩ region. It is deduced that imperfectly body tied devices may be worse for analogue design than using no body-tie at all     

A physical model of floating body thin film silicon-on-insulatornMOSFET with parasitic bipolar transistor

An analytical model for SOI nMOSFET with a floating body is developed to describe the I_ds-V_ds characteristics. Considering all current components in MOSFET as well as parasitic BJT, this study evaluates body potential, investigates the correlations among many device parameters, and characterizes the various phenomena in floating body: threshold voltage reduction, kink effect, output conductance increment, and breakdown voltage reduction. This study also provides a good physical insight on the role of the parasitic current components in the overall device operation. Our model explains the dependence of the channel length on the I_ds-V_ds characteristics with parasitic BJT current gain. Results obtained from this model are in good agreement with the experimental I_ds-V _ds curves for various bias and geometry conditions     

Substrate-bias effect and source-drain breakdown characteristics inbody-tied short-channel SOI MOSFET's

The substrate-bias effect and source-drain breakdown characteristics in body-tied short-channel silicon-on-insulator metal oxide semiconductor field effect transistors (SOI MOSFET's) were investigated. Here, “substrate bias” is the body bias in the SOI MOSFET itself. It was found that the transistor body becomes fully depleted and the transistor is released from the substrate-bias effect, when the body is reverse-biased. Moreover, it was found that the source-drain breakdown voltage for reverse-bias is as high as that for zero-bias. This phenomenon was analyzed using a three-dimensional (3-D) device simulation considering the body-tied SOI MOSFET structure in which the body potential is fixed from the side of the transistor. This analysis revealed that holes which are generated in the transistor are effectively pulled out to the body electrode, and the body potential for reverse-bias remains lower than that for zero-bias, and therefore, the source-drain breakdown characteristics does not deteriorate for reverse-bias. Further, the influence of this effect upon circuit operation was investigated. The body-tied configuration of SOI devices is very effective in exploiting merits of SOI and in suppressing the floating body-effect, and is revealed to be one of the most promising candidates for random logic circuits such as gate arrays and application specific integrated circuits     

Impact of the twin-gate structure on the linear kink effect in PD SOI nMOSFETS

In this work, the influence of the twin-gate structure on the gate-induced floating body effects in thin gate oxide partially depleted (PD) silicon-on-insulator (SOI) nMOSFETs is investigated through two-dimensional numerical simulations, which are validated by experimental results. The asymmetric behavior of the body potential with the interchange of the master and slave transistor of the twin-gate structure will be shown, as well as the relation between the total resistance and the effective mobility degradation factor. It will be demonstrated that a similar reduction of the linear kink effect is obtained in a twin-gate structure and in a conventional SOI transistor with an external resistance in series.