部分耗尽SOI MOSFETs中沟道的非对称掺杂效应

利用二维模拟软件对部分耗尽SoI器件中的非对称掺杂沟道效应进行了模拟.详细地研究了该结构器件的电学性能,如输出特性,击穿特性.通过本文模拟发现部分耗尽SOI非对称掺杂沟道相比传统的部分耗尽SOI,能抑制浮体效应,改善器件的击穿特性.同时跟已有的全耗尽SOI非对称掺杂器件相比,部分耗尽器件性能随参数变化,在工业应用上具有可预见性和可操作性.因为全耗尽器件具有非常薄的硅膜,而这将引起如前栅极跟背栅极的耦合效应和热电子退化等寄生效应.     

部分耗尽SOI MOSFETs中沟道的非对称掺杂效应

利用二维模拟软件对部分耗尽SoI器件中的非对称掺杂沟道效应进行了模拟.详细地研究了该结构器件的电学性能,如输出特性,击穿特性.通过本文模拟发现部分耗尽SOI非对称掺杂沟道相比传统的部分耗尽SOI,能抑制浮体效应,改善器件的击穿特性.同时跟已有的全耗尽SOI非对称掺杂器件相比,部分耗尽器件性能随参数变化,在工业应用上具有可预见性和可操作性.因为全耗尽器件具有非常薄的硅膜,而这将引起如前栅极跟背栅极的耦合效应和热电子退化等寄生效应.     

部分耗尽SOI体接触nMOS器件的关态击穿特性

分别采用具有硅化物和不具有硅化物的SOI工艺制成了部分耗尽SOI体接触nMOS晶体管.在体接触浮空和接地的条件下测量了器件的关态击穿特性.通过使用二维工艺器件模拟,并测量漏体结的击穿特性,详细讨论和分析了所制成器件击穿特性的差异和击穿机制.在此基础上,提出了一个提高PD-SOI体接触nMOS击穿特性的方法.     

采用新的抬高源漏工艺技术制作的全耗尽SOI CMOS器件和电路

采用新的工艺技术,成功研制了具有抬高源漏结构的薄膜全耗尽SOI CMOS器件.详细阐述了其中的关键工艺技术.器件具有接近理想的亚阈值特性,nMOSFETs和pMOSFETs的亚阈值斜率分别为65和69mV/dec.采用抬高源漏结构的1.2μm nMOSFETs的饱和电流提高了32%,pMOSFETs的饱和电流提高了24%.在3V工作电压下101级环形振荡器电路的单级门延迟为75ps.     

0.8 μm PDSOI CMOS器件和环振电路研究

研究了0.8μm部分耗尽绝缘体上硅(PDSOI)CMOS器件和电路,开发出成套的0.8μmPDSOI CMOS工艺.经过工艺投片,获得了性能良好的器件和电路.其中,当工作电压为5 V时,基于浮体SOI CMOS技术的0.8μm 101级环振单级延时为49.5 ps;基于H型栅体引出SOI CMOS技术的0.8μm 101级环振单级延时为158 ps.同时,对PDSOI CMOS器件的特性,如浮体效应、背栅特性、反常亚阈值斜率、击穿特性和输出电导变化等进行了讨论.     

一个连续且解析的SOI LDMOS表面势模型

提出了一个实现全耗尽与部分耗尽自动转换的体接触SOI LDMOS连续解析表面势模型.采用PSP的精确表面势算法求解SOI器件的表面势方程,得到了解析的以栅压和漏压为变量的SOI器件正、背硅/氧化层界面的表面势.修正了全耗尽状态下的反型层电荷和体电荷表达式,结合PSP的模型方程,给出连续解析的体接触SOI LDMOS直流模型.仿真结果与实验数据比较,二者吻合得很好,表明该模型能精确表征SOI LDMOS直流特性.     

一个连续且解析的SOI LDMOS表面势模型

提出了一个实现全耗尽与部分耗尽自动转换的体接触SOI LDMOS连续解析表面势模型.采用PSP的精确表面势算法求解SOI器件的表面势方程,得到了解析的以栅压和漏压为变量的SOI器件正、背硅/氧化层界面的表面势.修正了全耗尽状态下的反型层电荷和体电荷表达式,结合PSP的模型方程,给出连续解析的体接触SOI LDMOS直流模型.仿真结果与实验数据比较,二者吻合得很好,表明该模型能精确表征SOI LDMOS直流特性.     

0.13μm部分耗尽薄膜SOI MOSFETs击穿特性研究

以0.13μm部分耗尽薄膜SOI器件为研究对象,简要分析了体接触器件和浮体器件基本特性,指出两类器件击穿特性的差异性,并重点讨论了栅长、栅端偏压和衬底偏压等对器件击穿特性的影响,阐明了击穿特性的失效机理,为器件优化和电路设计提供参考。     

利用改善的体连接技术制备SOI LDMOSFET

对功率器件中常用的体连接技术进行了改进,利用一次硼离子注入技术形成体连接.采用与常规1μm SOI(硅-绝缘体)CMOS工艺兼容的工艺流程,在SIMOX SOI片上制备了LDMOS结构的功率器件.器件的输出特性曲线在饱和区平滑,未呈现翘曲现象,说明形成的体连接有效地抑制了部分耗尽器件的浮体效应.当漂移区长度为2μm时,开态击穿电压达到10V,最大跨导17.5mS/mm.当漏偏压为5V时,SOI器件的泄漏电流数量级为1nA,而相应体硅结构器件的泄漏电流为1000nA.电学性能表明,这种改善的体连接技术能制备出高性能的SOI功率器件.     

0.15μm薄膜全耗尽MOS／SOI器件的设计和研制

利用自己开发的二维数值深亚微米SOI器件模拟软件,较为详细地分析了沟道长度小于o.2μm的 SOI器件的阈值电压特性、穿通和击穿特性、亚阈值特性以及直流稳态特性等.通过这些模拟和分析计算,给出了沟道长度为0.18、0.15和0.1μm的薄膜全耗尽 SOI／MOS器件的设计方案,并根据该设计方案成功地研制出了性能良好的沟道长度为0.15μm的凹陷沟道 SOI器件.沟道长度为0.15μm薄膜全耗尽凹陷沟道SOI器件的亚阈值斜率为87mV/dec,击穿电压为1.6V,阈值电压为0.42V,电源电压为1.5V时的驱动电流为1.85mA,泄漏电流为0.5pA/μm沟道宽度.     

绝缘体上硅动态阈值nMOSFETs特性研究

基于绝缘体上硅技术,提出并研制动态阈值nMOSFETs结构.阐述了动态阈值nMOSFETs的工作原理.动态阈值nMOSFETs的阈值电压从VBS=0 V时的580 mV动态变化到VBS=0.6 V时的220 mV,但是这种优势并没有以增加漏电流为代价.因此动态阈值nMOSFETs的驱动能力较之浮体nMOSFETs在低压情况下,更具有优势.工作电压为0.6 V时,动态阈值nMOSFETs的驱动能力是浮体的25.5倍,0.7 V时为12倍.而且浮体nMOSFETs中的浮体效应,诸如Kink效应,反常亚阈值斜率和击穿电压降低等,均被动态阈值nMOSFETs结构有效抑制.     

非均匀指间距MOSFET弱雪崩效应考察和建模

本文对RF CMOS工艺下非均匀栅间距版图结构弱雪崩行为进行了考察。和均匀栅间距多指结构相比,采用非均匀栅间距器件漏源击穿电压有近8.5%左右和近20%的热相关漏电导特性的改善。提出了一种新颖的器件有源区总面积相关的紧凑模型用于精确预见漏击穿行为。器件总面积处理为和栅指间距相关。该模型精确预见了一组同时有均匀和非均匀栅间距nMOSFET的弱雪崩行为,仿真和测试结果的良好拟合度验证和证实了提出模型的精度。     

Study of the linear kink effect in PD SOI nMOSFETs

We present in this work a study of the linear kink effect (LKE) occurrence in partially depleted (PD) SOI nMOSFETs with thin gate oxide. The experimental LKE dependence on the channel length, channel width and drain voltage are reported as well as the impact of various parameters on the second peak has been studied by two-dimensional numerical simulations, namely, the gate current level, the carrier lifetime, the increase of the body potential, the threshold voltage variation and AC analysis. Three-dimensional simulations were also performed in order to evaluate the LKE dependence on the channel width.     

Analysis of drain breakdown voltage in SOI n-channel MOSFETs

The reduction of drain breakdown voltage in SOI nMOSFETs with floating substrate is related to the presence of a parasitic n-p-n bipolar structure, the base of which is the floating body of the device. reduction of breakdown voltage (compared to the case where a body contact is used) is shown to be dependent on both channel length and minority carrier lifetime in the SOI material. Conversely, it is shown that mere measurement of MOSFET breakdown voltages can be used to extract the minority carrier lifetime in the SOI material.<>     

Back-channel hot-electron effect on the front-channelcharacteristics in thin-film SOI MOSFETs

The front-channel I-V characteristics in thin-film SOI MOSFETs have been studied before and after back-channel hot-electron stress. As a result of electron trapping in the buried oxide near the drain junction, this stress causes the following changes: (1) a reduction of the channel current for a given gate voltage; (2) the appearance of the kink effect when measured in the reverse mode (with source and drain interchanged); and (3) an increased breakdown voltage when measured in the reverse mode. Both the kink effect and the change in the breakdown behavior can be attributed to the increased barrier height of the drain-body junction resulting from the localized electron trapping in the buried oxide     

LDMOS in SOI technology with very-thin silicon film

In this paper, we extensively investigate, by two-dimensional simulations, the output characteristics accuracy and breakdown voltage performance for very-thin film (80 nm) SOI lateral double-diffused MOS (LDMOS) transistor as a function of the drift doping, drift length and field plate length. Trade-offs are discussed to optimize the off-state breakdown voltage versus the occurrence of kink effect and quasi-saturation in on-state. The conclusions are supported by experimental results.     

Suppression of the floating-body effect using SiGe layers invertical surrounding-gate MOSFETs

The use of silicon germanium (SiGe) heterostructures in vertical surrounding-gate MOSFETs provides an additional means for tailoring current-voltage (I-V) characteristics by controlling physical effects inside the device. Incorporation of an SiGe layer in the vertical MOSFET source can delay the floating-body effect by changing the back injection efficiency and current gain of the parasitic bipolar junction transistor (BJT). Structures with abrupt and ramped SiGe source layers showed up to 2 V and 6 V increases in breakdown voltage at low gate voltages with suppression of the floating-body effect kink. Comparison of simulation to experiment displayed the difficulties of accurately predicting device parameters, but demonstrated the usefulness of simulation to qualitatively predict device behavior     

PDSOI nMOSFETs关态击穿特性

分别采用不同的背栅沟道注入剂量制成了部分耗尽绝缘体上硅浮体和H型栅体接触n型沟道器件.对这些器件的关态击穿特性进行了研究.当背栅沟道注入剂量从1.0×1013增加到1.3×1013cm-2,浮体n型沟道器件关态击穿电压由5.2升高到6.7V,而H型栅体接触n型沟道器件关态击穿电压从11.9降低到9V.通过测量寄生双极晶体管静态增益和漏体pn结击穿电压,对部分耗尽绝缘体上硅浮体和H型栅体接触n型沟道器件的击穿特性进行了定性解释和分析.     

Numerical analysis of surface-state effects on kink phenomena of GaAs MESFETs

Effects of surface states on the "kink" (or an abnormal increase in output conductance with the drain voltage) in GaAs MESFETs are studied by two-dimensional (2-D) simulations. It is shown that the kink could arise due to a space-charge effect originated from impact ionization of holes and the following hole trapping by the surface states. The onset voltage for current rise depends on the nature of surface states, which strongly affects the potential profiles. Transient or dynamic simulation indicates that the trap-related kink phenomenon should be a rather slow process. Substrate-related kink dynamics are also analyzed.     

PDSOI nMOSFETs关态击穿特性

分别采用不同的背栅沟道注入剂量制成了部分耗尽绝缘体上硅浮体和H型栅体接触n型沟道器件.对这些器件的关态击穿特性进行了研究.当背栅沟道注入剂量从1.0×1013增加到1.3×1013cm-2,浮体n型沟道器件关态击穿电压由5.2升高到6.7V,而H型栅体接触n型沟道器件关态击穿电压从11.9降低到9V.通过测量寄生双极晶体管静态增益和漏体pn结击穿电压,对部分耗尽绝缘体上硅浮体和H型栅体接触n型沟道器件的击穿特性进行了定性解释和分析.