使用新注入锁定技术的低相位噪声正交振荡器

提出了一种利用新注入锁定技术的低相位噪声正交振荡器,激励信号直接注入子谐波振荡器的共源连接点.原理上,正交振荡器的相位噪声性能会比子谐波振荡器的相位噪声性能好.该正交振荡器已经采用0.25μmCMOS工艺实现,测试结果表明该正交振荡器的振荡频率约为1.13GHz,在偏离振荡频率1MHz处的相位噪声约为-130dBc/Hz.该振荡器采用2.5V电源电压,消耗的电流约为8.0mA.     

基于HBT工艺的高功率低相位噪声QVCO

基于Sanan 2 μm GaAs HBT工艺,提出了一种差分Colpitts结构的高功率低相位噪声正交压控振荡器(QVCO)。该QVCO采用四只环形连接的二极管,通过二次谐波反相作用,迫使压控振荡器基波正交。该QVCO比传统串并联晶体管耦合电路具有更高的输出功率和更低的相位噪声。仿真结果表明,该QVCO的调谐范围为12.98~14.05 GHz。振荡频率为13.51 GHz时,输出信号功率为12.557 dBm。相位噪声为-117.795 dBc/Hz @1 MHz。     

基于超谐波注入锁定的低相噪QVCO的设计

对基于注入锁定的正交压控振荡器(QVCO)电路进行了研究和分析,设计了一个低相位噪声、低相位误差的QVCO电路,该电路由两个电感电容压控振荡器(LC VCO)在正交相位进行超谐波耦合,通过一个频率倍增器在交叉耦合对的共模信号点注入同步信号.通过对相位误差公式的推导,提出了降低相位误差的方法,由于该电路在共模点采用二倍频取样,抑制了尾电流的闪烁噪声,降低了相位噪声.电路基于TSMC 0.18 μm互补金属氧化物半导体(CMOS)工艺实现,测试结果表明,当谐振频率从4.5 GHz调谐到4.9 GHz时,在电源电压为1.8V时,电路消耗功率为13 mW,1 MHz频偏处的单边带(SSB)相位噪声为-129.95 dBc/Hz,与传统的QVCO相比,噪声性能得到了改善.     

单片UHF RFID阅读器中VCO及其预分频器设计

提出了一种应用于860～960 MHz UHF波段单片射频识别(RFID)阅读器的低相位噪声CMOS压控振荡器(VCO)及其预分频电路.VCO采用LC互补交叉耦合结构,利用对称滤波技术改善相位噪声性能,预分频电路采用注入锁定技术,用环形振荡结构获得了较宽的频率锁定范围.电路采用UMC 0.18 μm CMOS工艺实现,测试结果表明:VCO输出信号频率范围为1.283～2.557 GHz,预分频电路的频率锁定范围为66.35%,输出四相正交信号.芯片面积约为1 mm×1 mm,当PLL输出信号频率为895.5 MHz时,测得其相位噪声为-132.25 dBc/Hz@3 MHz,电源电压3.3 V时,电路消耗总电流为8 mA.     

基于对称螺旋型电感和差分二极管的2.4GHz CMOS正交输出压控振荡器

提出了一种产生2.4GHz正交本地振荡信号的方法.它将LC-VCO和两级环路振荡器两种结构组合起来以实现正交输出的低相位噪声压控振荡器.LC网络是由在片对称螺旋型电感和差分二极管组成的.详细论述了VCO原理及其噪声性能.该电路已经用0.25μm单层多晶、五层金属N阱CMOS数字工艺制作.测量结果表明:它可以提供正交的本地振荡信号,其振荡频率可以在300MHz的范围内调节,当仅对差分输出振荡信号的一端进行测试时,振荡频率为2.41GHz时,去偏移中心为600kHz时的相位噪声为-104.33dBc/Hz.而且,它能在很低的电源电压下工作,功耗也很低,所以,它在集成收发机中将得到广泛的应用.     

锁相环电路中压控振荡器的分析与设计

本文设计了一个应用于高频锁相环（PLL）系统的负阻LC压控振荡器,在传统LC压控振荡器基础上,通过采用二次谐波滤波技术降低了振荡器的相位噪声,并完成了电路的仿真。仿真结果表明,该压控振荡器的振荡频率在1．9—2．1GHz,其频率调节范围达到200MHz,并且在距中心频率1MHz处其相位噪声为-148．825dBc／Hz...     

基于对称螺旋型电感和差分二极管的2.4GHz CMOS正交输出压控振荡器

提出了一种产生2.4GHz正交本地振荡信号的方法.它将LC-VCO和两级环路振荡器两种结构组合起来以实现正交输出的低相位噪声压控振荡器.LC网络是由在片对称螺旋型电感和差分二极管组成的.详细论述了VCO原理及其噪声性能.该电路已经用0.25μm单层多晶、五层金属N阱CMOS数字工艺制作.测量结果表明:它可以提供正交的本地振荡信号,其振荡频率可以在300MHz的范围内调节,当仅对差分输出振荡信号的一端进行测试时,振荡频率为2.41GHz时,去偏移中心为600kHz时的相位噪声为-104.33dBc/Hz.而且,它能在很低的电源电压下工作,功耗也很低,所以,它在集成收发机中将得到广泛的应用.     

一种低相位噪声的毫米波压控振荡器

基于推推振荡器结构设计了一种低相位噪声的毫米波压控振荡器,相比传统采用直接振荡和倍频实现的振荡器,该振荡器具有体积小、相位噪声低及电路简单等优点.振荡器中的谐振电路采用多级串联谐振,电感采用微带线的形式,提高了谐振器的品质因数,进而降低了振荡器的相位噪声,且在谐振电路通过微带耦合方式实现了基频输出.基于GaAs异质结双极晶体管(HBT)工艺对振荡器进行了设计和流片,芯片尺寸为1.8 mm×1.4 mm.在5V工作电压和0～13 V调谐电压条件下,振荡器的输出频率为42.1～46.2 GHz,电流为120 mA,输出功率为1 dBm,1/2次谐波抑制大于15 dB,相位噪声为-60 dBc/Hz@10 kHz、-85 dBc/Hz@100 kHz和-105 dBc/Hz@1 MHz.     

使用三位三阶Δ∑调制器的集成1GHz小数频率合成器

本文实现了一个采用三位三阶Δ∑调制器的高频谱纯度集成小数频率合成器.该频率合成器采用了模拟调谐和数字调谐组合技术来提高相位噪声性能,优化的电源组合可以避免各个模块之间的相互干扰,并且提高鉴频鉴相器的线性度和提高振荡器的调谐范围.通过采用尾电流源滤波技术和减小振荡器的调谐系数,在片压控振荡器具有很低的相位噪声,而通过采用开关电容阵列,该压控振荡器达到了大约100MHz的调谐范围,该开关电容阵列由在片数字调谐系统进行控制.该频率合成器已经采用0.18μm CMOS工艺实现,仿真结果表明,该频率频率合成器的环路带宽约为14kHz,最大带内相位噪声约为-106dBc/Hz;在偏离载波频率100kHz处的相位噪声小于-120dBc/Hz,具有很高的频谱纯度.该频率合成器还具有很快的反应速度,其锁定时间约为160μs.     

基于阶梯阻抗hair-pin谐振器的X波段振荡器的设计

介绍一种采用新颖hair-pin谐振器设计低相位噪声平面微波振荡器的方法。新hair-pin谐振器利用阶梯阻抗可以转移基波倍频处的伪谐振频率并可以消除谐波互调分量的优势,使振荡器的相位噪声明显地降低。与传统均匀阻抗hair-pin谐振器设计的振荡器相比,新hair-pin谐振器设计的振荡器表现出更好的相位噪声。实验测量结果表明:振荡频率为12.07GHz,在100kHz和1 MHz频偏处,相位噪声分别为-96.15dBc/Hz和-127.29dBc/Hz。此外,振荡器的功耗为37.4mW,输出功率为-0.76dBm。     

New implementation of injection locked technique and its application to low phase noise quadrature oscillators

A new implementation of the injection locked technique is proposed. The incident signal is directly injected into the common-source connection node of the sub-harmonic oscillator instead of the gate of the tail current source, and a narrowband noise filtering network is inserted into the same node to suppress the tail current source noise. A novel quadrature oscillator with the proposed injection locked technique is presented. The simulations show that the phase noise of the quadrature oscillator is about 7 dB better than that of the stand-alone sub-harmonic oscillator. The quadrature oscillator has been implemented in 0.25 um CMOS process and the measured results show that the proposed quadrature oscillator could achieve a phase noise of −130 dBc/Hz at 1 MHz offset from 1.13 GHz carrier while only drawing an 8.0 mA current from the 2.5 V power supply.     

Analysis and Design of a Double-Quadrature CMOS VCO for Subharmonic Mixing at Ka-Band

In this paper, we analyze the potentials of a four-phase 14-GHz CMOS voltage-controlled oscillator, tailored to a sub-harmonic receiver, for signal processing at Ka-band. When mild phase accuracies between in-phase and quadrature down-converted signals are required, the four-phase oscillator displays roughly the same phase noise figure-of-merit as quadrature oscillator counterparts. However, the operation at half-frequency leads to an improved performance due to a higher quality factor of the tuning varactors, and because the local oscillator circuitry and signal path run at different frequencies, relaxing coupling issues. A detailed time-variant analysis of phase noise in multiphase oscillators is introduced and validated by both simulations and experiments. Prototypes realized in a 65-nm technology occupy an active area of 0.5 mm² and show the following performances: a 26% frequency tuning range (from 12.2 to 15.9 GHz), maximum phase error from pi/4 of 2deg, and a phase noise of -110 dBc/Hz at 1 MHz from 14 GHz, while consuming 18 mA from 0.8-V supply.     

Analysis and design of an optimally coupled 5-GHz quadrature LCoscillator

A 5-GHz quadrature LC oscillator has been realized, in which the two LC stages are coupled with phase shifters. Analysis on the behavioral level shows that an N-stage LC oscillator is optimally coupled when each stage is connected with phase shifters providing ±180°/N phase shift. Simulation of the 5-GHz two-stage quadrature LC oscillator reveals a 4.3-dB reduction in phase noise compared to a quadrature LC oscillator without phase shifters. Measurements of the 5-GHz quadrature LC oscillator, made in a 30-GHz f _T process, show a phase noise lower than -113 dBc/Hz, with a resonator quality factor of only 4 and an oscillator core power dissipation of 21.2 mW     

Noise property of a quadrature balanced VCO

A quadrature balanced voltage controlled oscillator (B-VCO) with current source switching is proposed and analyzed. This letter shows analytically that the switching improves the phase noise. A switched transistor is also used as a coupling transistor to generate quadrature signals without degrading the phase noise. To investigate the effect of quadrature coupling on the phase noise, a single B-VCO and a quadrature B-VCO are implemented with identical components in an 0.18-/spl mu/m CMOS process. Both VCO cores draw about 8.8mA under a low bias voltage of 1.8V. The oscillation frequencies are 10.21GHz and 10.81GHz. The measured phase noises of the single at an offset frequency of 1MHz VCO is -114.83 dBc/Hz while that of the quadrature VCO is -116.67 dBc/Hz. The quadrature B-VCO is superior to the single B-VCO with respect to phase noise and oscillation frequency in the X-band.     

A 1 V 2.2 mW 7 GHz CMOS Quadrature VCO Using Current-Reuse and Cross-Coupled Transformer-Feedback Technology

A current-reused quadrature voltage-controlled oscillator (CR-QVCO) is proposed with the cross-coupled transformer-feedback technology for the quadrature signal generation. This CR-QVCO has the advantages of low-voltage/low-power operation with an adequate phase noise performance. A compact differential three-port transformer, in which two half-circle secondary coils are carefully designed to optimize the effective turn ratio and the coupling factor, is newly constructed to satisfy the need of signal coupling and to save the area consumption simultaneously. The quadrature oscillator providing a center frequency of 7.128 GHz for the ultrawideband (UWB) frequency synthesizer use is demonstrated in a 0.18 mum RF CMOS technology. The oscillator core dissipates 2.2 mW from a 1 V supply and occupies an area of 0.48 mm². A tuning range of 330 MHz (with a maximum control voltage of 1.8 V) can be achieved to stand the frequency shift caused by the process variation. The measured phase noise is -111.2 dBc/Hz at 1 MHz offset from the center frequency. The IQ phase error shown is less than 2deg. The calculated figure-of-merit (FOM) is 184.8 dB.     

High performance QVCO design with series coupling in CMOS technology

A high performance quadrature voltage-controlled oscillator（QVCO） is presented.It has been fabricated in SMIC 0.18μm CMOS technology with top thick metal.The proposed QVCO employed cascade serial coupling for in phase and quadrature phase signal generation.Source degeneration capacitance is added to the NMOS differential pair to suppress their flicker noise from up-conversion to close in phase noise.A dedicated low noise and high power supply rejection low drop out regulator is used to supply this QVCO.The measured phase noise of the proposed QVCO achieves phase noise of-123.3 dBc/Hz at an offset frequency of 1 MHz from the carrier of 4.78 GHz,while the QVCO core circuit and LDO draw 6 mA from a 1.8 V supply.The QVCO can operate from 4.09 to 4.87 GHz（17.5%）.Measured tuning gain of the QVCO(K_vco) spans from 44.5 to 66.7 MHz/V.The chip area excluding the pads and ESD protection circuit is 0.41 mm².     

Design of a novel differential quadrature crystal oscillator

A novel crystal oscillator circuit with differential quadrature outputs is presented in this paper. It couples two differential Pierce structures with an annular cascade structure to realize differential quadrature outputs directly. A prototype of the circuit was fabricated in SMIC 0.18 μm CMOS process technology. The measurement results show that the maximum quadrature phase mismatch of adjoining signals is lower than 1.3° and the maximum amplitude mismatch is less than 1 %. Compared to the conventional quadrature signal implementations such as poly phase filter network, or a current mode logic divider, our proposed circuit can directly achieve differential quadrature outputs with much better phase noise and excellent differential quadrature matching. It proves potential application prospect in many radio frequency transceiver systems which require rigorous matching characteristics of differential quadrature local oscillator for excellent performance of image rejection.     

A 1-V 17-GHz 5-mW CMOS Quadrature VCO Based on Transformer Coupling

A 1-V 17-GHz 5-mW quadrature voltage-controlled oscillator (QVCO) based on transformer coupling is presented. Transformer coupling between two LC tank oscillators is proposed to achieve quadrature outputs with improved performance in terms of high frequency, wide tuning range, low phase noise, and low power as compared to existing active-coupling QVCOs. Implemented in a 0.18-mum CMOS process, the proposed QVCO measures a frequency tuning range of 16.5% at 17 GHz and phase noise of -110 dBc/Hz at 1 MHz offset while consuming 5 mA from a 1-V power supply and occupying a core area of 0.37 mm².     

一种基于注入锁定环形振荡器的时钟产生电路

提出了一种基于谐波注入锁定数控环形振荡器的时钟产生电路。采用注入锁定技术,极大地抑制了环形振荡器的相位噪声。在频率调谐环路关断的情况下,数控式振荡器可以正常工作,与需要一直工作的锁相环相比,大大节省了功耗。分析了电路的参考杂散性能。在65 nm CMOS工艺下进行流片测试,芯片的面积约为0.2 mm²。测试结果表明,设计的时钟产生电路工作在600 MHz时,1 MHz频偏处的相位噪声为-132 dBc/Hz,在1 V的电源电压下仅消耗了5 mA的电流。     

A symmetrical 6-GHz fully integrated cascode coupling CMOS LC quadrature VCO

A fully symmetrical integrated quadrature LC oscillator with a wide tuning range of 1.2GHz is presented. The quadrature voltage-controlled oscillator (QVCO) is implemented using a symmetrical coupling method which has been used to produce the large tuning range with a low control voltage and to achieve good phase noise performance in 0.18/spl mu/m complementary metal oxide semiconductor technology. The measured phase noise at 1MHz offset from the center frequency (5.5GHz) is -115 dBc/Hz. The QVCO draws 3.2mA from a 1.8V supply. The equivalent phase error between I and Q signal was at most 0.5/spl deg/.