真实缺陷的矩形模型及其关键面积计算

在集成电路(IC)中,为了进行有效的成品率估计和故障分析,与光刻有关的缺陷形状通常假设为圆模型.然而,真实缺陷的形状多种多样.本文提出一种真实缺陷的矩形模型及与之相关的关键面积计算模型,该模型既考虑了真实缺陷的形状又考虑了IC版图布线的特点.在缺陷引起故障概率预测方面,仿真结果表明新模型比圆模型更接近真实缺陷引起的故障概率.     

考虑缺陷形状分布的IC成品率模型

实现了基于圆缺陷模型的蒙特卡洛关键面积及成品率估计,模拟了圆缺陷模型估计的成品率误差与缺陷的矩形度之间的关系,提出了更具有一般性的两种集成电路成品率模型,它们分别对应于矩形度相同和不同的缺陷．仿真结果表明该模型为成品率的精确表征提供了新途径．     

IC缺陷轮廓的分形插值模型

现用于集成电路（ＩＣ）成品率预报及故障分析的缺陷模型均是用圆或正方形来代替真实缺陷的复杂轮廓进行近似建模的,从而在模型中引入了很大的误差。本文利用分形插值的思想直接对真实缺陷的轮廓进行模拟,从而提出了一种新的缺陷轮廓表征模型。实验结果表明：与传统的最大圆模型,最小圆模型及椭圆模型相比,新模型的建模精度有很大的提高。     

一种IC缺陷轮廓建模的新方法

现用于集成电路（ＩＣ）成品率预报及故障分析的缺陷模型均是用圆或正方形来代替真实缺陷的复杂轮廓进行近似建模的,从而在模型中引入了很大的误差。本文利用分段线性插值瓣思想直接对真实缺陷的方向尺寸进行逼近,从而提出了一种亲折缺陷轮廓表征模型。实验结果表明：与传统的最大圆模型、最小圆模型及椭圆模型相比,新模型的建模精度有了较大的提高。     

IC缺陷轮廓的分形插值模型

现用于集成电路(IC)成品率预报及故障分析的缺陷模型均是用圆或正方形来代替真实缺陷的复杂轮廓进行近似建模的,从而在模型中引入了很大的误差。本文利用分形插值的思想直接对真实缺陷的轮廓进行模拟,从而提出了一种新的缺陷轮廓表征模型。实验结果表明:与传统的最大圆模型、最小圆模型及椭圆模型相比,新模型的建模精度有了很大的提高。     

IC缺陷轮廓分形维估计的小波方法

为了有效的进行集成电路成品率预报和故障分析,与光刻有关的硅片表面缺陷通常被假定为圆形、椭圆或方形.然而,真实缺陷的形貌是多种多样的,它们的形状对集成电路的成品率估计有重要影响.本文讨论了缺陷轮廓所具有的分形特征,并用小波变换的方法对其分形维数进行了估计,估计结果与实例的特征相符,从而为缺陷轮廓的表征和计算机模拟提供了新的特征参数.     

考虑缺陷形状分布的IC成品率模型

实现了基于圆缺陷模型的蒙特矩形度之间的关系,提出了更具有一般性的两种集成电路成品率模型,它们分别对应于矩形度相同和不同的缺陷.仿真结果表明该模型为成品率的精确表征提供了新途径.     

IC缺陷轮廓多分形特征研究

IC真实缺陷轮廓曲线的形状特征对集成电路成品率预报及故障分析有重要影响。该文提出缺陷轮廓曲线具有多分形特征,以某一真实缺陷为例,用小波变换模极大(WTMM)的方法估计了其轮廓曲线参数方程的多分形谱,该结果为硅片表面缺陷的精细表征及其计算机模拟作了有益探索。     

基于小波变换的IC缺陷轮廓曲线分形维估计

硅片表面缺陷轮廓的形状特征对集成电路(IC)成品率预报及故障分析有重要影响。讨论了IC缺陷轮廓所具有的分形特征,利用小波变换对其参数曲线的分形维数进行了估计,估计结果与实际特征相符,从而为缺陷轮廓特征的描述和计算机模拟提供了一条新的途径。     

IC制造中真实缺陷轮廓模型的比较

本文对现有的IC制造中真实缺陷轮廓的建模方法进行了比较,得到了一些有意义的结果。该结果为进行有效的集成电路(IC)成品率预报及故障分析提供了有益的借鉴。     

Yield Modeling of Rectangular Defect Outline

In integrated circuits,the defects associated with photolithography are assumed to be in the shape of circular discs in order to perform the estimation of yield and fault analysis.However,real defects exhibit a great variety of shapes.In this paper,a novel yield model is presented and the critical area model of short circuit is correspondingly provided.In comparison with the circular model corrently available,the new model takes the similarity shape to an original defect,the two-dimensional distributional characteristic of defects,the feature of a layout routing and the character of yield estimation into account.As for the aspect of prediction of yield,the experimental results show that the new model may predict the yield caused by real defects more accurately than the circular model does.It is significant that the yield is accurately estimated and improved using the proposed model.     

Equivalent circular defect model of real defect outlines in the ICmanufacturing process

For efficient yield prediction and inductive fault analysis of integrated circuits (IC's), it is usually assumed that defects related to photolithography have the shape of circular discs or squares. Real defects, however, exhibit a great variety of shapes. This paper presents an accurate model to characterize those real defects. The defect outline is used in this model to determine an equivalent circular defect such that the probability that the circular defect causes a fault is the same as the probability that the real defect causes a fault, so a norm is available which ran be used to determine the accuracy of a defect model, and thus estimate approximately the error that will be aroused in the prediction of fault probability of a pattern by using circular defect model. Finally, the new model is illustrated with the real defect outlines obtained by optical inspection     

Modeling of real defect outlines and parameter extraction using acheckerboard test structure to localize defects

For efficient yield prediction and inductive fault analysis, it is usually assumed that defects have the shape of circular discs or squares. Real defects, however, exhibit a great variety of different shapes. This paper presents a more accurate model. The defect outline is approximated by an ellipse, and an equivalent circular defect is determined that causes a fault with the same probability as the real defect. To utilize this model, only the maximum and the minimum extension of detected defects have to be determined. That can be done easily using a novel test structure design. The checkerboard test structure uses the boundary pad frame of standard chips and thus achieves a large defect sensitive area. This area is partitioned into many small regions that can be analyzed separately. Defects are localized by simple electrical measurements. This allows an efficient optical inspection that can provide detailed information about the detected defects     

基于缺陷均匀分布的集成电路制造成品率与可靠性之间的关系模型

在集成电路可制造性设计研究中,成品率与可靠性之间的关系模型备受人们关注.缺陷对成品率和可靠性的影响不仅与出现在芯片上的缺陷粒径大小有关而且与缺陷出现在芯片上的位置有关.本文主要考虑了出现在互连线上的金属丢失物缺陷对互连线的影响,分析了同一粒径的缺陷出现在互连线不同位置对互连线有效宽度的影响,给出了基于缺陷均匀分布的互连线平均有效宽度,结合已有成品率和可靠性估计模型,提出了基于缺陷位置信息的集成电路制造成品率与可靠性之间的关系模型.在工艺线稳定的情况下,利用该工艺线的制造成品率可以通过该关系式有效地估计出产品的可靠性,从而有效地缩短新产品的研发周期.     

Introducing dependency into IC yield models

Many models have been proposed to explain the distribution of point defects on integrated circuit (IC) chips. The most popular of these models are based on distributions derived from the Poisson distribution for describing the number of defects expected on a chip. These models do not inherently allow for dependence between the number of defects expected on two adjacent chips. This paper introduces a model for generating an IC defect distribution that allows for dependence in the number of defects on chips that are near one another. Simulations are done to compare the new dependent model to a previously proposed independent model. These simulations with the new model show defective chips clustered near each other on the water. This clustering property has been observed on real wafers. Methods of parameter and yield estimation in the dependent model are discussed.