高深宽比深隔离槽的刻蚀技术研究

体硅集成MEMS器件中的一个非常重要的技术就是微结构与电路部分的电隔离和互连。由于体硅工艺与传统CMOS工艺不兼容，所以形成高深宽比的深隔离槽(宽约3μm，深20～100μm)是体硅集成中急待解决的工艺难题。本文采用MEMS微加工的DRIE(Deep Reactive Ion Etclaing)技术、热氧化技术和多晶硅填充技术，形成了高深宽比的深电隔离槽(宽3．6μm，深85μm)。还提出了一种改变深槽形状的方法，使深槽的开口变大，以利于多晶硅的填充，避免了空洞的产生。     

高深宽比深隔离槽的刻蚀技术研究

体硅集成MEMS器件中的一个非常重要的技术就是微结构与电路部分的电隔离和互连。由于体硅工艺与传统CMOS工艺不兼容 ,所以形成高深宽比的深隔离槽 (宽约 3μm ,深 2 0～ 10 0μm)是体硅集成中急待解决的工艺难题。本文采用MEMS微加工的DRIE (DeepReactiveIonEtching)技术、热氧化技术和多晶硅填充技术 ,形成了高深宽比的深电隔离槽 (宽 3.6 μm ,深 85μm)。还提出了一种改变深槽形状的方法 ,使深槽的开口变大 ,以利于多晶硅的填充 ,避免了空洞的产生     

高深宽比深隔离槽的刻蚀技术研究

体硅集成MEMS器件中的一个非常重要的技术就是微结构与电路部分的电隔离和互连.由于体硅工艺与传统CMOS工艺不兼容,所以形成高深宽比的深隔离槽(宽约3 μm,深20～100 μm)是体硅集成中急待解决的工艺难题.本文采用MEMS微加工的DRIE(Deep Reactive Ion Etching)技术、热氧化技术和多晶硅填充技术,形成了高深宽比的深电隔离槽(宽3.6 μm,深85 μm).还提出了一种改变深槽形状的方法,使深槽的开口变大,以利于多晶硅的填充,避免了空洞的产生.     

用于自对准Si MMIC的等平面深槽隔离工艺(英文)

研究了在自对准硅MMIC中等平面深槽隔离工艺的实现。该工艺包括如下过程:首先应用各向异性刻蚀的Bosch工艺刻蚀出用于隔离埋集电极的1.6μm宽、9μm深的隔离槽,接着对隔离槽通过热氧化二氧化硅、淀积氮化硅和多晶硅的形式进行填充,然后再采用高密度等离子体刻蚀设备对多晶硅进行反刻,其刻蚀时间通过终点检测系统来控制,最后再刻蚀出0.8μm深的有源区硅台面和采用1.5～1.6μm厚的氧化层对场区进行填充,藉此来保证隔离槽和有源区处于同一个平面上。此深槽隔离工艺与目前的多层金金属化系统兼容,且该工艺不会造成明显的硅有源区台面缺陷,测试结果表明:在15 V下的集电极-集电极漏电流仅为10 nA,该值远低于全氧化填充隔离槽工艺的5μA。     

一种新的硅深槽刻蚀技术研究

本文报告了一种获得侧壁陡直的硅深槽新技术．实验中采用一种新材料──氮化锆（ＺｒＮ）作为反应离子刻蚀的掩模，所需掩模厚度约５００．采用氟基气体ＳＦ６作为刻蚀气体，并附加Ａｒ和Ｏ２，这样刻蚀过程中在槽的侧壁会形成氧化硅作为阻挡刻蚀层，结果得到了深约６μｍ，侧壁垂直接近９０°的硅深槽．     

沟槽肖特基器件Si深槽刻蚀工艺

深硅刻蚀工艺是制造沟槽肖特基器件的关键技术.Si深槽的深度影响肖特基反向击穿电压,深槽的垂直度影响多晶Si回填效果,侧壁平滑度及深槽底部长草现象对器件的耐压性能影响显著.采用SF6/O2常温刻蚀工艺刻蚀Si深槽.研究了工艺压力、线圈功率、SF6/O2比例以及下电极功率等参数对沟槽深度均匀性和垂直度的影响.得到了使Si深槽形貌为槽口宽度略大于槽底,侧壁光滑,且沟槽深度均匀性为2.3％左右的工艺条件.利用该刻蚀工艺可实现沟槽多晶Si无缝回填.该工艺条件成功应用于沟槽肖特基器件制作中,反向击穿电压达到58 V,反向电压通48 V,漏电流为11.2 μA,良率达到97.55％.     

基于双面TSV互连技术的超厚硅转接板制备

为了满足异质集成应用中对转接板机械性能方面的需求,提出了一种基于双面硅通孔(TSV)互连技术的超厚硅转接板的制备工艺方案。该方案采用Bosch工艺在转接板正面形成300μm深的TSV,通过结合保型性电镀工艺和底部填充电镀工艺进行TSV填充。在转接板背面工艺中首先通过光刻将双面TSV的重叠部分控制在一个理想的范围内,然后经深反应离子刻蚀(DRIE)工艺形成深度为20μm的TSV并完成绝缘层开窗,最后使用保型性电镀完成TSV互连。通过解决TSV刻蚀中侧壁形貌粗糙、TSV底部金属层过薄和光刻胶显影不洁等关键问题,最终得到了双面互连电阻约为20Ω、厚度约为323μm的硅转接板。     

反应离子刻蚀硅槽工艺研究

在CMOS多晶硅刻蚀工艺的基础上进行工艺开发,采用氯气和溴化氢气体进行硅槽刻蚀。通过对功率、压力、气体流量等工艺参数拉偏,用扫描电子显微镜观察硅槽侧壁形貌,分析各参数在反应离子刻蚀中所起到的作用,得到对硅槽形貌影响较大的因素,最终得到一种能够与CMOS工艺兼容的硅槽刻蚀方法。该方法能够制作出深度6μm、深宽比4∶1、侧壁光滑的硅槽,可以用于光电继电器、硅电容等新型器件的研发。     

深硅槽开挖工艺

本文介绍了硅槽应用,即硅槽隔离和硅槽电容,对器件性能的改善。并介绍了硅槽隔离和硅槽电容的形成步骤及硅槽刻蚀剖面的形貌控制,CBrF_3刻蚀硅槽侧壁保护层的形成等等。     

基于MEMS工艺的硅基红外辐射源研制

利用微机电系统( MEMS)制造工艺制备出了一种硅基红外辐射源.该辐射源采用单晶硅为衬底,通过直流溅射沉积Pt/Ti薄膜,并利用深反应离子刻蚀与湿法腐蚀工艺制备隔离槽和释放支撑层.研究了支撑层厚度对红外辐射源辐射特性的影响.结果表明,随着支撑层厚度的减小,红外辐射源的调制驱动电压会降低.当支撑层厚度为1μm时,辐射源调...     

Process optimization of a deep trench isolation structure for high voltage SOI devices

The process reasons for weak point formation of the deep trench on SOI wafers have been analyzed in detail.An optimized trench process is also proposed.It is found that there are two main reasons:one is over-etching laterally of the silicon on the surface of the buried oxide caused by a fringe effect;and the other is the slow growth rate of the isolation oxide in the concave silicon corner of the trench bottom.In order to improve the isolation performance of the deep trench,two feasible ways for optimizi...     

A novel mechanical diced trench structure for warpage reduction in wafer level packaging process

The wafer warpage problem, mainly originated from coefficient of thermal expansion mismatch between the materials, becomes serious in wafer level packaging as large diameter wafer is adopted currently. The warpage poses threats to wafer handling, process qualities, and can also lead to serious reliability problems. In this paper, a novel mechanical diced trench structure was proposed to reduce the final wafer warpage. Deep patterned trenches with a depth about 100 μm were fabricated in the Si substrate by mechanical dicing method. Both experiment and simulation approaches were used to investigate the effect of the trenches on the wafer warpage and the influence of the geometry of the trenches was also studied. The results indicate that, by forming deep trenches, the stress on the individual die is decoupled and the total wafer warpage could be reduced. The final wafer warpage is closely related to the trench depth and die width. Trenched sample with a depth of 100 μm can decrease the wafer warpage by 51.4%.     

The optimization of deep trench isolation structure for high voltage devices on SOI substrate

In this paper, the process and layout optimizations for improving the isolation performance of deep trench structures on SOI substrate are proposed. In the view of process flow, the reasons for forming weak points (located at the trench bottom) in deep trench structure are analyzed. In order to solve this problem of the weak points, a method of etching partial buried oxide after etching silicon is put forward, which can increase the thickness of isolation oxide at trench bottom by 10-20%. In aspect of layout structure, a voltage drop model of double trench structures is presented and verified by the experimental results, which indicates that breakdown voltage of double trench is a function of trench spacing. It is noted that the minimum trench spacing allowed by the process design rule can ensure superior isolation capability for double trench structure. Both methods for improving the performance of the device have also been verified in 0.5 μm HV SOI technology.     

DRIE技术加工W波段行波管折叠波导慢波结构的研究

简要介绍了利用深反应离子刻蚀制作折叠波导慢波结构的现状及制作的工艺流程。对深反应离子刻蚀掩膜制作即光刻工艺,以及折叠波导慢波结构的深刻加工进行了深入的研究。详细分析了各光刻工艺对光刻胶图形的影响,尤其是前烘对光刻胶图像侧壁垂直度的影响;在深反应离子刻蚀中,还详细分析了刻蚀时间、下电极功率以及刻蚀气体气压对刻蚀结果的影响。经参数优化后获得最佳工艺参数,并制作出带有电子注通道的W波段折叠波导慢波结构,慢波结构深为946μm,侧壁垂直度为91°,电子注通道深为225μm,侧壁垂直度为90°。     

Sub-micron imaging on high-topography wafers using spray coating and projection lithography

We propose a method to image inside deep trenches (50 μm) using spray-coated resist and the ASML PAS 5500/100 system with the new functionality multi-step imaging. Multi-step imaging allows extending the focus offset range of the PAS 5500/100 system from ±30 μm to ±200 μm. Isolated trenches and contact holes were both imaged inside the deep trenches and on the surface of the wafer to study the versatility of the new functionality. A resolution of 700 nm in 3 μm thick photoresist, at the bottom of 50 μm deep, 200 μm wide trench, was obtained with this process. Finally, multi-focus exposure that consists in exposing the same image several times at various focus offsets was performed in order to image thick photoresist on high topographic substrates.     

Oxidation-induced defect generation in advanced DRAM structures

Structures containing deep-trenched storage capacitors and shallow-trench isolation were examined in patterns suitable for future generation dynamic RAMs (DRAMs). These same effects were also examined in similar structures which included only the shallow isolation trenches. Observed was a strong interaction between the deep and shallow trenches, which makes structures which incorporate both types much more susceptible to oxidation-induced defect generation than those without deep trenches. It was observed that at higher oxidation temperatures, more oxide can be grown before defects are generated. This is interpreted as a combination of more-efficient visco-elastic relaxation in the oxide and a lower differential oxidation rate between the {110} trench sidewalls and the {100} planar surface at higher temperatures. It was also observed that substantial defect immunity can be obtained by incorporating an oxidation barrier in the trench structures. An overall processing strategy to eliminate defect generation in these advanced structures is suggested     

A double-epitaxial process for high-density DRAM trench-capacitor isolation

A new double-epi structure for isolating deep (>5 µm) trench capacitors with 1 µm or less spacing is described. This technique consists of a thin lightly doped upper epilayer on top of a thicker and more heavily doped bottom layer of epi. The low resistivity bottom epilayer is designed to isolate trench capacitors of any depth. The upper layer with high resistivity is used for the CMOS periphery and can be selectively doped to achieve a near-uniform concentration to isolate trench capacitors in the core. Isolation between deep trenches at 1.0-µm spacing has been demonstrated to be applicable for 4 Mbit and greater DRAM integration levels.     

Study of the pixel-pitch reduction for HgCdTe infrared dual-band detectors

The third generation of HgCdTe infrared-detector focal-plane arrays (FPAs) should be able to detect simultaneously in two spectral bands. The feasibility of this type of dual-band detectors has already been shown in our laboratory with a pixel size of 50 μm in the 3–5-μm wavelength range. To improve the detector resolution, it is necessary to decrease the pixel pitch. Dry etching is a key process technology to fulfill this goal because of the high aspect-ratio structures needed (typically 10–15-μm deep and 2–5-μm wide trenches). In this paper, we present results of a parametric study on HgCdTe dry etching, as well as results obtained on detector arrays made with the dry-etching technique. The etching study has been done in a microwave plasma reactor with the aim of controlling the surface roughness, the etch rate, and the slope of the trench side. We show how these parameters are influenced by the reactive gas-mixture composition (based on CH₄, H₂, and Ar) and the substrate self-bias. We show how polymer film deposition can prevent etching from occurring but can improve anisotropy. We show some examples of results obtained when manufacturing the trenches that separate the pixels, keeping a high fill factor, and anisotropic etching. We also show results of the material surface characterizations done with scanning electron microscopy (SEM) and Hall effect measurements. These studies allow us to evaluate and compare the damages done to the HgCdTe surface with different etching conditions. Our best process allows us to make a light electrical damage, confined to less than a micron deep in the material. Using the dry-etching process, we have developed detector arrays fabricated with a pixel pitch as low as 30 μm. We finally present the results of the first electrical characterizations made on these arrays, showing promising results for the development of high-resolution dual-band detectors.     

1/4-µm CMOS isolation technique using selective epitaxy

A new CMOS isolation technique has been developed for reducing isolation width to a 1/4 µm with large latchup immunity. This technique is supported by three key processes. The first is to form 1/4 µm thick insulator films on trench sidewalls, which are shaped perpendicularly to the substrate surface plane. The second is to refill the trenches with selectively grown single-crystal silicon with a planar surface. The third is to form a low-resistance well for latchup prevention. The CMOS devices are composed of n-channel devices fabricated on a p-type substrate and p-channel devices fabricated on an n-type epi-layer. In this isolation structure, a parasitic MIS operation with vertical channel induces large leakage currents along the isolation sidewalls. However, the highly doped p-type region, due to deep boron implant in the p-type substrate, is effective to suppress parasitic operation. Submicrometer-gate CMOS inverter operation is shown, when the channel stop implant is carried out.