FinFET器件的集约阈电压模型

对FinFET器件(或称三栅MOSFET器件)的二维截面做了解析静电学分析以得出阈电压的计算公式.结果显示,由于三栅结构在高度方向的限制作用,需要引入一个H系数来修正栅电容,随着高度不断变大,它渐近于双栅MOSFET器件的情况.由该解析模型得出的电势分布与数值模拟结果吻合.提出了一个包含量子效应的Fin-FET器件的集约阈电压模型,结果表明,当高度或者顶栅的氧化层厚度变小时,栅电容及阈电压都会上升,这与FinFET设计时发现的趋势是相符合的.     

考虑二维量子力学效应的MOSFET解析电荷模型

在亚 5 0 nm的 MOSFET中 ,沿沟道方向上的量子力学效应对器件特性有很大的影响。基于 WKB理论 ,考虑MOSFET中该效应对垂直沟道方向上能级的影响 ,引入了其对于阈电压的修正。在此基础上 ,对沟道方向的子带作了抛物线近似 ,从而建立了一个考虑二维量子力学的电荷解析模型。根据该模型 ,得到二维量子力学修正和沟道长度以及其他工艺参数的关系。与数值模拟结果的比较表明 ,该解析模型的精度令人满意 ,并且得出以下结论 :二维量子力学效应使阈电压下降 ,并且在亚 5 0 nm的 MOSFET中 ,这个修正不可忽略。     

基于摄动法研究短沟道SOI MOSFET亚阈值特性

提出了一种新的方法对短沟道SOI MOSFETs亚阈区的二维表面势的解析模型进行了改进,即摄动法.由于在短沟道SOI MOSFETs中不仅需要计及不可动的电离杂质,而且需要考虑自由载流子的数量和分布的影响.利用摄动法求解非线性泊松方程可以得到短沟道SOI MOSFETs二维的表面势解析模型.通过与二维数值模拟器MEDICI模拟结果比较,证明了在亚阈区改进模型所得的结果比只计及不可动的电离杂质的SOI MOSFETs模型所得的结果吻合更好.     

高k栅介质SOILDMOS管阈特性分析与建模

通过分析高k栅介质SOI LDMOS管沟道与埋氧层的关系,建立了SOI LDMOS管的阈特性模型。研究了器件主要结构参数对阈特性及小尺寸效应的影响,分析了阈值电压与高k栅介质的介电常数和应变Si层的掺杂浓度的关系。通过软件ISE TCAD进行模拟仿真。结果表明,在不同的tSi和NA条件下,阈值电压的模型计算与数值模拟值吻合率为94.8%,最大差值为0.012 V,不同沟道长度SOI LDMOS的阈值电压漂移率为3.52%,最大漂移电压为0.008 V,模型计算值与数值模拟结果基本吻合。     

包含多子带结构的MOS器件开启电压量子力学效应修正模型

量子力学效应对于深亚微米MOSFET特性的影响随着衬底浓度的增加和栅氧层厚度的减小而日益显著.实验结果表明:量子力学效应能够导致开启电压明显的漂移.本文通过比较薛定谔方程在抛物线势垒下的数值解和三角势垒下的解析解验证了MOS结构弱反型区量子力学效应三角势垒近似的正确性.在计算弱反型区量化层内子带结构的基础上,提出量子化有效态密度和经典有效态密度的概念,分析了载流子在子带中的分布情况,讨论了量子力学效应影响开启电压的两个因素,并在此基础上给出了开启电压的量子力学修正模型.该模型准确地揭示了量子力学效应影响开启电压的物理实质     

亚100nm体硅MOSFET集约I-V模型

利用"局域化"的概念和二维泊松方程的解析解,建立了沟道方向上二维量子效应对阈电压的修正模型.基于密度梯度理论,建立了多晶硅栅内量子效应对阈电压的修正模型.在此基础上,结合弹道理论,开发了一个适用于亚100nm MOSFET的集约I-V模型.通过与TSMC提供的沟长为45nm实际器件测试结果[1],以及与三组亚100nm MOSFET的数值模拟结果的比较,证明了该模型具有良好的精度(平均误差小于8%)和可延伸性.     

用于SPICE-Ⅱ程序的耗尽型MOS器件模型

分析了SPICEⅡ程序模拟耗尽型MOS器件所遇到的限制及其原因,用线性区阈电压和饱和区阈电压描述耗尽型器件线性区和饱和区特性,讨论了饱和区阈电压与线性区阈电压之差随衬偏电压变化的关系,建立了耗尽型MOS器件模型及其参数提取的新方法.模拟结果与实验基本吻合.     

表面栅静电感应晶体管沿沟道中心线电势分布的解析分析

本文从表面栅静电感应晶体管(SIT)的基本物理模型出发,求出了沿沟道中心线的电势分布和沟道势垒高度的解析表达式.根据所得表达式具体计算了一个典型器件在不同栅源电压V_(GS)和漏源电压V_(DS)下的电势分布和势垒高度.其结果与1978年J.L.Morenza等人对同一器件用计算机数值分析所得的结果吻合较好. 本文给出了该种器件中势垒存在的物理模型,指出了表面栅与隐埋栅器件在势垒形成上的差别:表面栅器件中势垒的形成与源沟n~+n结有关;而隐埋栅器件势垒的形成与源沟n~+n结无关. 本文所得的解析表达式也表明,表面栅结构中势垒的出现需要沟道夹断一定的深度.这与1980年日本J.Ohmi用计算机数值分析所得结论是一致的. 本文所得的势垒高度的解析表达式可以作为进一步求解该种器件各电参数的解析表达式的基础.     

一种新的有沟道注入的短沟MOSFET的阈电压解析模型

本文提出一个非均匀掺杂、短沟道MOSFET阈电压的准二维解析模型。用此模型对各种不同条件下的微米、亚微米MOSFET的阈电压进行了计算,其结果与二维数值分析程序得到的结果相符甚好。本模型可用于电路分析程序,工艺容错分析及器件的优化设计。     

亚100nm体硅MOSFET集约I-V模型

利用“局域化”的概念和二维泊松方程的解析解，建立了沟道方向上二维量子效应对阈电压的修正模型．基于密度梯度理论，建立了多晶硅栅内量子效应对阈电压的修正模型．在此基础上，结合弹道理论，开发了一个适用于亚100nm MOSFET的集约I-V模型．通过与TSMC提供的沟长为45nm实际器件测试结果，以及与三组亚100nm MOSFET的数值模拟结果的比较，证明了该模型具有良好的精度（平均误差小于8%）和可延伸性．     

A new approach to threshold voltage modelling of short-channel MOSFETS

A simple analytical model has been developed to predict the threshold voltage on drain bias dependence of an arbitrarily doped short-channel MOSFET. Based on an analytical solution of the two-dimensional Poisson equation, the potential distribution in the channel depletion region has been derived. The maximum surface field and the minimum surface potential are used to determine the threshold voltage. The influence of drain voltage on threshold voltage has been included by an equivalent shrinkage of the virtual channel length hereafter called “voltage-length transformation”. This simple but general procedure enables us to account for the drain effect and to extend other threshold voltage models derived under assumption of low drain-source voltage. Predictions for threshold voltage have been compared with results of two-dimensional numerical analysis and experimental data. The comparison has been made for a wide variety of doping profiles, channel length, substrate and drain bias, gate oxide thickness and junction depth. Excellent agreement has been obtained down to submicron channel length.     

An analytical threshold voltage model of NMOSFETs with hot-carrier induced interface charge effect

An analytical threshold voltage model of NMOSFETs including the effect of hot-carrier-induced interface charges is presented. A step function describing the interface charge distribution along the channel is used to account for the hot carrier induced damage, and a pseudo-2D method is applied to derive the surface potential. The threshold voltage model is then developed by solving the gate-to-source voltage at the onset of surface inversion where the minimum surface potential equals the channel potential. Both the drain-induced barrier lowering (DIBL) and body effects are included in the present model as well. The present threshold voltage model is validated for both fresh and damaged devices. The results show that the threshold voltage shifts upward and approaches a maximum value with negative interface charges and shifts downward and reaches a minimum value with positive interface charges as the interface charge region length is increased from zero to the channel length. Model is successfully verified using simulation data obtained from TCAD (technology-based computer-aided design).     

Analytical threshold voltage model for cylindrical surrounding-gate MOSFET with electrically induced source/drain extensions

Physics-based analytical threshold voltage model for cylindrical surrounding-gate MOSFET with electrically induced source/drain extensions is presented. The effect of inversion carriers on the channel’s potential is considered in presented model. Using this analytical model, the characteristics of EJ-CSG are investigated in terms of surface potential and electric field distribution, threshold voltage roll-off, and DIBL. Results show that the application of electrically induced S/D extensions to the cylindrical surrounding-gate MOSFET will successfully suppress the hot-carrier effects, threshold voltage roll-off, and DIBL. It is also revealed that a moderate side-gate bias voltage, a small gate oxide thickness, and a small silicon channel radius are needed to improve device characteristics. The derived analytical model is verified by its good agreement with the three-dimensional numerical device simulator ISE.     

异质栅全耗尽型应变硅 SOI MOSFET二维解析模型*

本文首次并建立了异质栅全耗尽型应变Si SOI (DMG SSOI) MOSFET的二维表面势沿沟道变化的模型．并对该结构的MOSFET的短沟道效应SCE (short channel effect),热载流子效应HCE(hot carrier effect),漏致势垒降低DIBL (drain induced barrier lowering)和载流子传输效率进行了研究．该模型中考虑以下参数：金属栅长,金属栅的功函数,漏电压和Ge在驰豫SiGe中的摩尔组分．结果表明沟道区的表面势引进了阶梯分布,正是这个阶梯分布的表面势抑制了SCE,HCE和DIBL．同时,应变硅和SOI(silicon-on-insulator)结构都能提高载流子的传输效率,特别是应变硅能提高载流子的传输效率．此外阈值电压模型能者正确表明阈值电压随栅长比率L2/L1减小或应变Si膜中Ge摩尔组分的降低而升高．数值模拟器ISE验证了该模型的正确性．     

A threshold voltage model for short-channel MOSFETs taking into account the varying depth of channel depletion layers around the source and drain

In this paper, an analytical model for threshold voltage of short-channel MOSFETs is presented. For such devices, the depletion regions due to source/drain junctions occupy a large portion of the channel, and hence are very important for accurate modeling. The proposed threshold voltage model is based on a realistic physically-based model for the depletion layer depth along the channel that takes into account its variation due to the source and drain junctions. With this, the unrealistic assumption of a constant depletion layer depth has been removed, resulting in an accurate prediction of the threshold voltage. The proposed model can predict the drain induced barrier lowering (DIBL) effect and hence, the threshold voltage roll-off characteristics quite accurately. The model predictions are verified against the 2-D numerical device simulator, DESSIS of ISE TCAD.     

Two-dimensional threshold voltage analytical modes of DMG strained-silicon-on-insulator MOSFETs

For the first time, a simple and accurate two-dimensional analytical model for the surface potential variation along the channel in fully depleted dual-material gate strained-Si-on-insulator (DMG SSOI) MOSFETs is developed. We investigate the improved short channel effect (SCE), hot carrier effect (HCE), drain-induced barrier-lowering (DIBL) and carrier transport efficiency for the novel structure MOSFET. The analytical model takes into account the effects of different metal gate lengths, work functions, the drain bias and Ge mole fraction in the relaxed SiGe buffer. The surface potential in the channel region exhibits a step potential, which can suppress SCE, HCE and DIBL. Also, strained-Si and SOI structure can improve the carrier transport efficiency, with strained-Si being particularly effective. Further,the threshold voltage model correctly predicts a "rollup" in threshold voltage with decreasing channel length ratios or Ge mole fraction in the relaxed SiGe buffer. The validity of the two-dimensional analytical model is verified using numerical simulations.     

Two-dimensional analytical modeling of fully depleted DMG SOI MOSFET and evidence for diminished SCEs

A two-dimensional (2-D) analytical model for the surface potential variation along the channel in fully depleted dual-material gate silicon-on-insulator MOSFETs is developed to investigate the short-channel effects (SCEs). Our model includes the effects of the source/drain and body doping concentrations, the lengths of the gate metals and their work functions, applied drain and substrate biases, the thickness of the gate and buried oxide and also the silicon thin film. We demonstrate that the surface potential in the channel region exhibits a step function that ensures the screening of the drain potential variation by the gate near the drain resulting in suppressed SCEs like the hot-carrier effect and drain-induced barrier-lowering (DIBL). The model is extended to find an expression for the threshold voltage in the submicrometer regime, which predicts a desirable "rollup" in the threshold voltage with decreasing channel lengths. The accuracy of the results obtained using our analytical model is verified using 2-D numerical simulations.     

Modeling of ultrathin double-gate nMOS/SOI transistors

An analytical model valid near and below threshold is derived for double-gate nMOS/SOI devices. The model is based on Poisson's equation, containing both the doping impurity charges and the electron concentration. An original assumption of the constant difference between surface and mid-film potentials is successfully introduced. The model provides explicit expressions of the threshold voltage and threshold surface potential, which may no longer be assumed to be pinned at the limit of strong inversion, and demonstrates the nearly ideal subthreshold slope of ultrathin double-gate SOI transistors. Very good agreement with numerical simulations is observed. Throughout the paper we give an insight into weak inversion mechanisms occurring in thin double-gate structures     

一种新的Halo掺杂圆柱围栅MOSFET阈值电压解析模型

通过在圆柱坐标系中精确求解泊松方程,建立了全新的Halo掺杂圆柱围栅MOSFET静电势,电场以及阈值电压的解析模型。与采用抛物线电势近似法得到的解析模型相比,当沟道半径远大于氧化层厚度时,新模型更为精确。模型还考虑了Halo区掺杂浓度、氧化层厚度以及沟道半径对器件阈值电压特性的影响。结果表明,采用中等程度的halo区掺杂浓度、较薄的栅氧化层以及较小的沟道半径可以有效改善器件的阈值电压特性。解析模型与三维数值模拟软件ISE所得结果高度吻合。