An Efficient Test Data Compression Technique Based on Codes

提出了一种新的测试数据压缩/解压缩的算法,称为混合游程编码,它充分考虑了测试数据的压缩率、相应硬件解码电路的开销以及总的测试时间.该算法是基于变长-变长的编码方式,即把不同游程长度的字串映射成不同长度的代码字,可以得到一个很好的压缩率.同时为了进一步提高压缩率,还提出了一种不确定位填充方法和测试向量的排序算法,在编码压缩前对测试数据进行相应的预处理.另外,混合游程编码的研究过程中充分考虑到了硬件解码电路的设计,可以使硬件开销尽可能小,并减少总的测试时间.最后,ISCAS 89 benchmark电路的实验结果证明了所提算法的有效性.     

应用混合游程编码的SOC测试数据压缩方法

本文提出了一种有效的基于游程编码的测试数据压缩/解压缩的算法:混合游程编码,它具有压缩率高和相应解码电路硬件开销小的突出特点.另外,由于编码算法的压缩率和测试数据中不确定位的填充策略有很大的关系,所以为了进一步提高测试压缩编码效率,本文还提出一种不确定位的迭代排序填充算法.理论分析和对部分ISCAS 89 benchmark电路的实验结果证明了混合游程编码和迭代排序填充算法的有效性.     

一种用于测试数据压缩的自适应EFDR编码方法

该文提出一种用于测试数据压缩的自适应EFDR(Extended Frequency-Directed Run-length)编码方法。该方法以EFDR编码为基础,增加了一个用于表示后缀与前缀编码长度差值的参数N,对测试集中的每个测试向量,根据其游程分布情况,选择最合适的N值进行编码,提高了编码效率。在解码方面,编码后的码字经过简单的数学运算即可恢复得到原测试数据的游程长度,且不同N值下的编码码字均可使用相同的解码电路来解码,因此解码电路具有较小的硬件开销。对ISCAS-89部分标准电路的实验结果表明,该方法的平均压缩率达到69.87%,较原EFDR编码方法提高了4.07%。     

双游程编码的无关位填充算法

双游程编码是集成电路测试数据压缩的一种重要方法,可分为无关位填充和游程编码压缩两个步骤.现有文献大都着重在第二步,提出了各种不同的编码压缩算法,但是对于第一步的无关位填充算法都不够重视,损失了一定的潜在压缩率.本文首先分析了无关位填充对于测试数据压缩率的重要性,并提出了一种新颖的双游程编码的无关位填充算法,可以适用于不同的编码方法,从而得到更高的测试数据压缩率.该算法可以与多种双游程编码算法结合使用,对解码器的硬件结构和芯片实现流程没有任何的影响.在ISCAS89的基准电路的实验表明,对于主流的双游程编码算法,结合该无关位填充算法后能提高了6%-9%的测试数据压缩率.     

一种低开销的压缩解压缩方法

针对LED大屏幕显示信息特点,深入分析RLE编码算法.改进游程长度编码模型,并结合Golomb码优势,提出了基于Golomb码的混合游程编码方法;其中分析了任意概率分布下Golomb码的结构,推导出任意给定阶数m和概率分布下的统一编码算法;最后给出了实现解码的硬件电路.通过对不同压缩方式比较,证明本文方法是一种低开销的、简便的、压缩效率高的方法.     

基于VSPTIDR编码压缩的测试资源划分方法

提出了一种有效的新型测试数据压缩编码——VSPTIDR编码,该编码方法只需对编码字进行移位操作即可得到相应的游程长度,在测试集中0的概率p满足p≥0.92时,能取得比FDR编码更高的压缩率。该编码方法的解码器也较FDR编码的解码器简单、易实现且能有效节省硬件开销。这一系列改进降低了芯片的测试和制造成本,从而也就降低了芯片的整体成本。     

基于变游程编码的测试数据压缩算法

基于IP核的设计思想推动了SOC设计技术的发展,却使SOC的测试数据成几何级数增长.针对这一问题,本文提出了一种有效的测试数据压缩算法——变游程(Variable-Run-Length)编码算法来减少测试数据量、降低测试成本.该算法编码时同时考虑游程0和游程1两种游程,大大减小了测试数据中长度较短游程的数量,提高了编码效率.理论分析和实验数据表明,变游程编码能取得较同类编码算法更高的压缩效率,能够显著减少测试时间、降低测试功耗和测试成本.     

一种混合定变长虚拟块游程编码的测试数据压缩方案

 文章提出了一种混合定变长虚拟块游程编码的测试数据压缩方案,该方案将测试向量级联后分块,首先在块内找一位或最大一位表示,再对块内不能一位表示的剩下位进行游程编码,这样减少了游程编码的数据量,从而突破了传统游程编码方法受原始测试数据量的限制.对ISCAS 89部分标准电路的实验结果显示,本文提出的方案在压缩效率明显优于类似的压缩方法,如Golomb码、FDR码、VIHC码、v9C码等.     

应用Variable-Tail编码压缩的测试资源划分方法

测试资源划分是降低测试成本的一种有效方法.本文提出了一种新的有效的对测试数据进行压缩的编码:Variable-Tail编码,并构建了基于该编码的测试资源划分方案.文章的理论分析和实验研究表明了采用Variable-Tail编码能取得比Golomb编码更高的压缩率,针对多种模式下的测试向量均能提供很好的压缩效果,解码器的硬件也较易实现.文章还提出了一种整合不确定位动态赋值的测试向量排序算法,该算法可以进一步提高测试压缩率.文章最后用实验数据验证了所提编码和排序算法的高效性.     

SOC测试数据的编码压缩技术

文章介绍了一种基于测试向量集的压缩／解压缩方法，目的在于弥补SOC测试中,测试设备存储容量不足的问题，分析了三种不同的编码方案，并从压缩率和解码电路的规模对它们作了比较，得出了使用Golomb编码来进行测试向量压缩／解压缩是简单而又行之有效的方法的结论。文章还给出了一个有效的最小海明距离排序算法，大大的提高了测试数据的压缩率。     

A new scheme of test data compression based on equal-run-length coding (ERLC)

A new scheme of test data compression based on run-length, namely equal-run-length coding (ERLC) is presented. It is based on both types of runs of 0's and 1's and explores the relationship between two consecutive runs. It uses a shorter codeword to represent the whole second run of two equal length consecutive runs. A scheme for filling the don't-care bits is proposed to maximize the number of consecutive equal-length runs. Compared with other already known schemes, the proposed scheme achieves higher compression ratio with low area overhead. The merits of the proposed algorithm are experimentally verified on the larger examples of the ISCAS89 benchmark circuits.     

An Efficient Compatibility-Based Test Data Compression and Its Decoder Architecture

Test data compression is an effective methodology for reducing test data volume and testing time. A novel compatibility-based test data compression method is presented in this paper. With the high compression efficiency of extended frequency-directed run length coding algorithm, the proposed method groups the test vectors that have least incompatible bits and amalgamates them into a single vector by assigning 1 or 0 to unspecified bits and c to incompatible bits. Three runs of 1, 0 and c can be encoded simultaneously. In addition, the corresponding decoder architecture with low hardware overhead has been developed. To evaluate the effectiveness of the proposed approach, in experiments, it is applied to the International Symposium on Circuits and Systems’ benchmark circuits. The experiments results show that the proposed algorithm gets a higher compression ratio than the conventional algorithms.     

MICRO: a new hybrid test data compression/decompression scheme

To overcome the limitation of the automatic test equipment (ATE), test data compression/decompression schemes become a more important issue of testing for a system-on-chip (SoC). In order to alleviate the limitation of previous works, a new hybrid test data compression/decompression scheme for an SoC is developed. The new scheme is based on analyzing the factors that influence test parameters: compression ratio and hardware overhead. To improve compression ratio, the proposed scheme, called the Modified Input reduction and CompRessing One block (MICRO), uses the modified input reduction, the one block compression, a novel mapping, and reordering algorithms. Unlike previous approaches using the cyclic scan register architecture, the proposed scheme is to compress original test data and to decompress the compressed test data without the cyclic scan register architecture. Therefore, the proposed scheme leads to high-compression ratio with low-hardware overhead. Experimental results on ISCAS '89 and ITC '99 benchmark circuits prove the efficiency of the new method.     

Split variable-length input Huffman code with application to test data compression for embedded cores in SOCs

In this article, a run length encoding-based test data compression technique has been addressed. The scheme performs Huffman coding on different parts of the test data file separately. It has been observed that up to a 6% improvement in compression ratio and a 29% improvement in test application time can be achieved sacrificing only about 6.5% of the decoder area. We have compared our results with the other contemporary works reported in the literature. It has been observed that for most of the cases, our scheme produces a better compression ratio and that the area requirements are much less.     

Modified Selective Huffman Coding for Optimization of Test Data Compression,Test Application Time and Area Overhead

A compression-decompression scheme, Modified Selective Huffman (MS-Huffman) scheme based on Huffman code is proposed in this paper. This scheme aims at optimization of the parameters that influence the test cost reduction: the compression ratio, on-chip decoder area overhead and overall test application time. Theoretically, it is proved that the proposed scheme gives the better test data compression compared to very recently proposed encoding schemes for any test set. It is clearly demonstrated with a large number of experimental results that the proposed scheme improves the test data compression, reduces overall test application time and on-chip area overhead compared to other Huffman code based schemes.     

A Power Efficient Test Data Compression Method for SoC using Alternating Statistical Run-Length Coding

A power efficient System-on-a-Chip test data compression method using alternating statistical run-length coding is proposed. To effectively reduce test power dissipation, the test set is firstly preprocessed by 2D reordering scheme. To further improve the compression ratio, 4 m partitioning of the runs and a smart filling of the don’t care bits provide the nice results, and alternating statistical run-length coding scheme is developed to encode the preprocessed test set. In addition, a simple decoder is obtained which consumed a little area overhead. The benchmark circuits verify the proposed power efficient coding method well. Experimental results show it obtains a high compression ratio, low scan-in test power dissipation and little extra area overhead during System-on-a-Chip scan testing.     

Synchronization overhead in SOC compressed test

Test data compression is an enabling technology for low-cost test. Compression schemes however, require communication between the system under test and the automated test equipment. This communication, referred to in this paper as synchronization overhead, may hinder the effective deployment of this new test technology for core-based systems-on-chip. This paper analyzes the sources of synchronization overhead and discusses the different tradeoffs, such as area overhead, test time and automatic test equipment extensions. A novel scalable and programmable on-chip distribution architecture is proposed, which addresses the synchronization overhead problem and facilitates the use of low cost testers for manufacturing test. The design of the proposed architecture is introduced in a generic framework, and the implementation issues (including the test controller and test set preparation) have been considered for a particular case.     

A Non-Scan Approach to DFT for Controllers Achieving 100% Fault Efficiency

This paper presents a non-scan design-for-testability method for controllers that are synthesized from FSMs (Finite State Machines). The proposed method can achieve complete fault efficiency: test patterns for a combinational circuit of a controller are applied to the controller using state transitions of the FSM. In the proposed method, at-speed test application can be performed and the test application time is shorter than previous methods. Moreover, experimental results show the area overhead is low.