应变硅薄膜的厚度对材料迁移率的影响

用化学气相沉积方法在SiC/Si上外延生长了应变硅薄膜.扫描电子显微镜方法显示所得样品具有明显的Si/SiC/Si三层结构,喇曼散射光谱和X射线衍射测量结果表明外延的Si薄膜存在应变.Hall效应测量证明相比于相同浓度的体Si材料应变Si薄膜具有较高的霍尔迁移率;但随着应变硅层厚度的增加,霍尔迁移率下降,这应与薄膜中应变减小和失配位错有关.     

应变硅薄膜的厚度对材料迁移率的影响

用化学气相沉积方法在SiC/Si上外延生长了应变硅薄膜.扫描电子显微镜方法显示所得样品具有明显的Si/SiC/Si三层结构,喇曼散射光谱和X射线衍射测量结果表明外延的Si薄膜存在应变.Hall效应测量证明相比于相同浓度的体Si材料应变Si薄膜具有较高的霍尔迁移率;但随着应变硅层厚度的增加,霍尔迁移率下降,这应与薄膜中应变减小和失配位错有关.     

厚表层Si柔性绝缘衬底上SiC薄膜的外延生长

利用LPCVD方法,在厚表层Si(SOL≈0.5μm)柔性绝缘衬底(SOI)(001)上外延生长出了可与硅衬底上外延晶体质量相比拟的SiC/SOI,表明SOI是一种很有潜力的柔性衬底. Raman 光谱结果表明SiC/SOI外延层比SiC/Si外延层有更大的残存应力,对此从理论上进行了解释.利用X射线衍射(XRD)、原子力显微镜(AFM)、扫描电镜(SEM)和喇曼散射光谱(RAM)技术研究了外延材料的晶体结构、界面性质和应变情况.     

厚表层Si柔性绝缘衬底上SiC薄膜的外延生长

利用LPCVD方法,在厚表层Si(SOL≈0.5μm)柔性绝缘衬底(SOI)(001)上外延生长出了可与硅衬底上外延晶体质量相比拟的SiC/SOI,表明SOI是一种很有潜力的柔性衬底.Raman光谱结果表明SiC/SOI外延层比SiC/Si外延层有更大的残存应力,对此从理论上进行了解释.利用X射线衍射(XRD)、原子力显微镜(AFM)、扫描电镜(SEM)和喇曼散射光谱(RAM)技术研究了外延材料的晶体结构、界面性质和应变情况     

聚焦离子束在外延生长氮化镓薄膜失配位错研究中的应用

氮化镓具有直接能量带隙(3.4eV)适合用作短波长发光器件,具有非常广泛的应用前景[1]。氮化镓薄膜(厚度约为μm量级)的制备一般均采用异质处延生长的方法。由于受到衬底材料的限制(常用的衬底为三氧化二铝,单晶硅,砷化镓等),使衬底材料与外延薄膜在晶体结构和物理性质方面有所差异,如晶胞参数的不同和热膨胀系数的差异。这些差异在外延生长的薄膜中引起失配应力和应变。当外延薄膜的厚度达到临界厚度时,外延薄膜中的失配应力和应变均达到极大值。继续外延生长超过临界厚度时,就会在外延薄膜中引入失配位错来释放失配应力,降低失配能量。失配…     

SIMOX薄膜材料的红外光谱特性和薄膜厚度的非破坏性测量方法

报道了SOI材料薄膜厚度的非破坏性快速测量方法,详细地研究了SIMOx材料的红外吸收光谱特性,求出了特征峰对应的吸收系数.提出利用红外吸收光谱测量SIMOX绝缘埋层厚度的非破坏性方法,并根据离子注入原理计算出表面硅层的厚度.SIMOX薄膜的表层硅和绝缘埋层的厚度是SOI电路设计时最重要的两个参数,提供的非破坏性测量方法,测量误差小于5％.在SIMOX材料开发利用、批量生产中,用此方法可及时方便地检测SIMOX薄膜的表层硅和绝缘埋层的厚度,随时调整注入能量和剂量.     

薄层SOS薄膜材料外延生长及其器件应用

亚微米CMOS/SOS器件发展对高质量的100-200纳米厚度的薄层SOS薄膜提出了更高的要求.实验证实;采用CVD方法生长的原生SOS薄膜的晶体质量可以通过固相外延工艺得到明显改进.该工艺包括:硅离子自注入和热退火.X射线双晶衍射和器件电学测量表明:多晶化的SOS薄膜固相外延生长导致硅外延层晶体质量改进和载流子迁移率提高.固相外延改进的薄层SOS薄膜材料能够应用于先进的CMOS电路.     

SIMOX薄膜材料的红外光谱特性和薄膜厚度的非破坏性测量方法

报道了 SOI材料薄膜厚度的非破坏性快速测量方法 ,详细地研究了 SIMOX材料的红外吸收光谱特性 ,求出了特征峰对应的吸收系数 .提出利用红外吸收光谱测量 SIMOX绝缘埋层厚度的非破坏性方法 ,并根据离子注入原理计算出表面硅层的厚度 .SIMOX薄膜的表层硅和绝缘埋层的厚度是 SOI电路设计时最重要的两个参数 ,提供的非破坏性测量方法 ,测量误差小于5% .在 SIMOX材料开发利用、批量生产中 ,用此方法可及时方便地检测 SIMOX薄膜的表层硅和绝缘埋层的厚度 ,随时调整注入能量和剂量     

Effect of Lattice Mismatch on Luminescence of ZnO/Si Hetero-Structure

研究了ZnO薄膜中应力对发光的影响.实验样品为ZnO体单晶、在Si基片上直接生长的ZnO薄膜以及通过SiC过渡层在Si基片上生长的ZnO薄膜.测量了这三种样品的X射线衍射图形、喇曼光谱和光致发光光谱.由X射线衍射图形可以看出,由于SiC过渡层缓解了ZnO与Si之间的晶格失配,使得通过SiC过渡层在Si上生长的ZnO薄膜的结晶质量好于直接在Si上生长的ZnO薄膜的质量.进一步通过喇曼谱测量发现,与ZnO体单晶相比,直接在Si上生长的ZnO薄膜的E2(high)峰红移1.9cm-1,根据喇曼谱峰位移与应力的关系可以推出薄膜中存在0.4GPa的张应力;而通过SiC过渡层在Si上生长的ZnO薄膜的E2(high)峰红移0.9cm-1,对应着0.2GPa的张应力.对照X射线衍射图形的结果可以看出,薄膜中张应力的大小与薄膜的结晶质量密切相关,表明张应力来源于外延层和基片间的晶格失配,晶格失配越大,外延层中产生的张应力越大.有无SiC过渡层的两种薄膜样品的PL光谱中都存在紫外和绿光两种谱带,随样品热处理时氧气分压增加,两种样品都出现绿光增强的相似的变化规律,但有SiC过渡层的样品的变化幅度较小.这一结果说明,绿色发光中心与薄膜的质量,也就是与薄膜中存在的张应力大小有关.在以往研究中得出的非故意掺杂ZnO薄膜的绿色发光中心来源于氧反位缺陷(Ozn),文中研究的结果正好可以解释氧反位缺陷形成的原因.由于薄膜中存在张应力,使得样品的能量升高,其结果必然会产生缺陷来释放张应力,以便降低系统能量.而氧离子半径大于锌离子半径,氧替位锌有利于释放张应力,也就是说,在存在张应力的情况下,Ozn的形成能降低.这一结果进一步证明Si上生长的ZnO薄膜中的绿色发光中心与氧反位缺陷有关.     

应力对ZnO/Si异质结构的光致发光的影响

研究了ZnO薄膜中应力对发光的影响.实验样品为ZnO体单晶、在Si基片上直接生长的ZnO薄膜以及通过SiC过渡层在Si基片上生长的ZnO薄膜.测量了这三种样品的X射线衍射图形、喇曼光谱和光致发光光谱.由X射线衍射图形可以看出,由于SiC过渡层缓解了ZnO与Si之间的晶格失配,使得通过SiC过渡层在Si上生长的ZnO薄膜的结晶质量好于直接在Si上生长的ZnO薄膜的质量.进一步通过喇曼谱测量发现,与ZnO体单晶相比,直接在Si上生长的ZnO薄膜的E2(high)峰红移1.9cm-1,根据喇曼谱峰位移与应力的关系可以推出薄膜中存在0.4GPa的张应力;而通过SiC过渡层在Si上生长的ZnO薄膜的E2(high)峰红移0.9cm-1,对应着0.2GPa的张应力.对照X射线衍射图形的结果可以看出,薄膜中张应力的大小与薄膜的结晶质量密切相关,表明张应力来源于外延层和基片间的晶格失配,晶格失配越大,外延层中产生的张应力越大.有无SiC过渡层的两种薄膜样品的PL光谱中都存在紫外和绿光两种谱带,随样品热处理时氧气分压增加,两种样品都出现绿光增强的相似的变化规律,但有SiC过渡层的样品的变化幅度较小.这一结果说明,绿色发光中心与薄膜的质量,也就是与薄膜中存在的张应力大小有关.在以往研究中得出的非故意掺杂ZnO薄膜的绿色发光中心来源于氧反位缺陷(Ozn),文中研究的结果正好可以解释氧反位缺陷形成的原因.由于薄膜中存在张应力,使得样品的能量升高,其结果必然会产生缺陷来释放张应力,以便降低系统能量.而氧离子半径大于锌离子半径,氧替位锌有利于释放张应力,也就是说,在存在张应力的情况下,Ozn的形成能降低.这一结果进一步证明Si上生长的ZnO薄膜中的绿色发光中心与氧反位缺陷有关.     

Effect of Silicon-on-Insulator Substrate on Residual Strain in 3C-SiC Films

One group of SiC films are grown on silicon-on-insulator (SOI) substrates with a series of silicon-over-layer thickness.Raman scattering spectroscopy measurement clearly indicates that a systematic trend of residual stress reduction as the silicon over-layer thickness decreases for the SOI substrates.Strain relaxation in the SiC epilayer is explained by force balance approach and near coincidence lattice model.     

Growth and characterization of GaN thin films on SiC SOI substrates

SiC semiconductor-on-insulator (SOI) structures have been investigated as substrates for the growth of GaN films. The SiC SOI was obtained through the conversion of Si SOI wafers by reaction with propane and H₂. (111) SiC SOI have been produced by this carbonization process at temperatures ranging from 1200 to 1300°C. X-ray diffraction (XRD) and infrared spectroscopy (FTIR) are used to chart the conversion of the Si layer to SiC. Under our conditions, growth time of 3 min at 1250°C is sufficient to completely convert a 1000? layer. XRD of the SiC SOI reveals a single SiC peak at 2θ = 35.7° corresponding to the (111) reflection, with a corrected full width at half-maximum (FWHM) of ~590±90 arc-sec. Infrared spectroscopy of SiC SOI structures obtained under optimum carboniza-tion conditions exhibited a sharp absorption peak produced by the Si-C bond at 795 cm⁻¹, with FWHM of ∼ 20–25 cm⁻¹. Metalorganic CVD growth of GaN on the (111) SiC SOI was carried out with trimethylgallium and NH₃. The growth of a thin (≤200?), low temperature (500°C) GaN buffer layer was followed by the growth of a thick (∼2 μm) layer at 1050°C. Optimum surface morphology was obtained for zero buffer layer. XRD indicates highly oriented hexagonal GaN, with FWHM of the (0002) peak of ~360±90 arc-sec. Under high power excitation, the 300°K photoluminescence (PL) spectrum of GaN films exhibits a strong near band-edge peak (at λ_p~371 nm, with FWHM = 100–150 meV) and very weak yellow emission. Under low power excitation, the 370 nm PL emission from the GaN/SiC SOI structure increases rapidly with SiC carbonization temperature, while the yellow band (∼550–620 nm) correspondingly decreases.     

Integrated sensor and electronic circuits in fully depleted SOItechnology for high-temperature applications

The electrical characteristics of devices and circuits realized in CMOS technology on silicon-on-insulator (SOI) substrates and operated at elevated temperatures are presented and compared with results obtained using other materials (bulk Si, GaAs, SiC). It is demonstrated that fully depleted CMOS on SOI is the most suitable process for the realization of complex electronic circuits to be operated in high-temperature environments, up to more than 300°C     

Comparison of hole mobility in LOCOS-isolated thin-film SOIp-channel MOSFET's fabricated on various SOI substrates

The hole mobility of LOCOS-isolated thin-film silicon-on-insulator (SOI) p-channel MOSFET's fabricated on SOI substrates with different buried oxide thickness has been investigated. Two types of SOI wafers are used as a substrate: (1) SIMOX wafer with 100-nm buried oxide and (2) bonded SOI wafer with 100-nm buried oxide. Thin-film SOI p-MOSFET's fabricated on SIMOX wafer have hole mobility that is about 10% higher than that on bonded SOI wafer. This is caused by the difference in the stress under which the silicon film is after gate oxidation process. This increased hole mobility leads to the improved propagation delay time by about 10%     

发展中的SiCOI技术

SiCOI技术是SiC材料与SOI技术结合而形成的一种新的微电子技术，它的产生与发展不仅推动SIC半导体技术的发展，还将弥补SI SOI技术应用的局限性，并将在高温、高频、大功率、抗辐射等电子学领域得到应用的发展。文章介绍了近年来SiCOI技术的最新进展和简要评述。     

Substrate crosstalk reduction using SOI technology

This work analyzes both by simulations and measurements the substrate crosstalk performances of various Silicon-On-Insulator (SOI) technologies, and compares them to those of normal bulk CMOS process. The influence of various parameters, such as substrate resistivity, buried oxide thickness and distance between devices, is investigated. The use of capacitive guard rings is proposed, and their effectiveness is demonstrated. A simple RC model has been developed to allow a deep understanding of these phenomena as well as to simplify future studies of more complex systems. The superiority of high-resistivity SIMOX substrates over standard SOI and bulk is finally demonstrated     

薄膜厚埋层SOI材料的新制备技术

在结合低剂量注氧隔离(SIMOX)技术和键合技术的基础上,研究了制备薄膜(薄顶层硅膜)厚埋层SOI材料的新技术--注氧键合技术.采用该新技术成功制备出薄膜厚埋层SOI材料,顶层硅厚度130nm,埋氧层厚度lμm,顶层硅厚度均匀性±2%.并分别采用原子力显微镜(AFM)和剖面透射电镜(XTEM)对其表面形貌和结构进行了表征.研究结果表明,SIMOX材料顶层硅通过键合技术转移后仍能够保持其厚度均匀性,且埋氧层和顶层硅之间具有原子级陡峭的分界面,因此注氧键合技术将会是一项有广阔应用前景的SOI制备技术.     

Back gate effects on threshold voltage sensitivity to SOI thicknessin fully-depleted SOI MOSFETs

The dependence of threshold voltage on silicon-on-insulator (SOI) thickness is studied on fully-depleted SOI MOSFETs, and, for this purpose, back-gate oxide thickness and back gate voltage are varied. When the back gate oxide is thinner than the critical thickness dependent on the back gate voltage, the threshold voltage has a minimum in cases where the SOI film thickness is decreased, because of capacitive coupling between the SOI layer and the back gate. This fact suggests that threshold voltage fluctuations due to SOI thickness variations are reduced by controlling the back gate voltage and thinning the back gate oxide     

On the performance of single-gated ultrathin-body SOI Schottky-barrier MOSFETs

The authors study the dependence of the performance of silicon-on-insulator (SOI) Schottky-barrier (SB) MOSFETs on the SOI body thickness and show a performance improvement for decreasing SOI thickness. The inverse subthreshold slopes S extracted from the experiments are compared with simulations and an analytical approximation. Excellent agreement between experiment, simulation, and analytical approximation is found, which shows that S scales approximately as the square root of the gate oxide and the SOI thickness. In addition, the authors study the impact of the SOI thickness on the variation of the threshold voltage V/sub th/ of SOI SB-MOSFETs and find a nonmonotonic behavior of V/sub th/. The results show that to avoid large threshold voltage variations and achieve high-performance devices, the gate oxide thickness should be as small as possible, and the SOI thickness should be /spl sim/ 3 nm.     

漂移区纵向线性掺杂的SOI高压器件研究

随着SOI层厚度的变化,当SOI层的厚度为2μm时,SOI LDMOS器件具有一个最佳的击穿电压.如果漂移区纵向的杂质浓度为线性分布,那么它的纵向电场就会为一个常数,击穿电压会达到最大值,而这种杂质浓度线性分布的漂移区可以通过热扩散得到.采用这种方法制得的SOI LDMOS的纵向击穿电压提高了43%,导通电阻降低了24%,这是因为它的表面浓度更高.