SiGe/Ge/SiGe异质结构中自旋极化输运特性的模拟

利用蒙特卡罗方法对SiGe/Ge/SiGe异质结构的自旋极化输运特性进行了模拟研究．在Ge沟道调制掺杂异质结构形成的二维空穴气中,空穴的自旋进动主要受Rashba自旋轨道相互作用控制．在77～300K的温度范围内,对自旋散射长度、自旋极化率等自旋极化输运特性进行了研究．模拟结果显示,低温和窄宽度沟道有利于减小散射对自旋极化输运的影响,避免自旋极化率衰减,增大自旋散射长度．栅控的漏端电流自旋相关效应使器件跨导增大,并产生负跨导效应．     

SiGe SOI CMOS特性分析与优化设计

基于全耗尽SOI CMOS工艺，建立了具有SiGe沟道的SOI MOS器件结构模型，并利用ISE TCAD器件模拟软件，对SiGe SOl CMOS的电学特性进行模拟分析。结果表明，引入SiGe沟道可极大地提高PMOS的驱动电流和跨导（当Ge组分为0．3时，驱动电流提高39．3％，跨导提高38．4％），CMOS电路的速度显著提高；在一定的Ge总量下，改变Ge的分布，当沟道区呈正向递减式分布时，电路速度最快。     

Ge/SiGe异质结构肖特基源漏MOSFET

制备了氧化铪(HfO2)高k介质栅Si基Ge/SiGe异质结构肖特基源漏场效应晶体管(SB-MOSFET)器件,研究了n型掺杂Si0.16Ge0.84层对器件特性的影响,分析了n型掺杂SiGe层降低器件关态电流的机理。使用UHV CVD沉积系统,采用低温Ge缓冲层技术进行了材料生长,首先在Si衬底上外延Ge缓冲层,随后生长32 nm Si0.16Ge0.84和12 nm Ge,并生长1 nm Si作为钝化层。使用原子力显微镜和X射线衍射对材料形貌和晶体质量进行表征,在源漏区沉积Ni薄膜并退火形成NiGe/Ge肖特基结,制备的p型沟道肖特基源漏MOSFET,其未掺杂Ge/SiGe异质结构MOSFET器件的空穴有效迁移率比相同工艺条件制备的硅器件的高1.5倍,比传统硅器件空穴有效迁移率提高了80%,掺杂器件的空穴有效迁移率与传统硅器件的相当。     

Si/SiGe PMOS器件的模拟优化设计与样品研制

通过理论分析与计算机模拟,给出了以提高跨导为目标的Si/SiGe PMOSFET优化设计方法,包括栅材料的选择、沟道层中Ge组分及其分布曲线的确定、栅氧化层及Si盖帽层厚度的优化和阈值电压的调节,基于此已研制出Si/SiGe PMOSFET器件样品.测试结果表明,当沟道长度为2μm时,Si/SiGe PMOS器件的跨导为45mS/mm(300K)和92mS/mm(77K),而相同结构的全硅器件跨导则为33mS/mm(300K)和39mS/mm(77K).     

应变Si/SiGe沟道功率UMOSFET的模拟分析

提出一种应变Si/SiGe UMOSFET结构,并与Si-UMOSFET器件的电流-电压特性进行比较;对SiGe区域在UMOSFET器件中的不同厚度值进行静态电学仿真。应变Si/SiGe异质结能够有效地提高沟道区载流子的迁移率,增大IDS,降低Vth及器件的Ron;且应变异质结与载流子有效传输沟道距离的大小,对器件的Vth、Isat、V(BR)DSS及电流-电压特性都有较大的影响。因此在满足击穿电压要求的基础上,应变Si/SiGe沟道异质结的UMOSFET相对Si-UMOSFET在I-V特性和Ron方面有较大的改进。     

双应变SiGe/Si异质结CMOS的设计及其电学特性的Medici模拟

本文提出一种沟道长度为0.125 μm的异质结CMOS(HCMOS)器件结构.在该结构中,压应变的SiGe与张应变的Si分别作为异质结PMOS(HPMOS)与异质结NMOS(HNMOS)的沟道材料,且HPMOS与HNMOS为垂直层叠结构;为了精确地模拟该器件的电学特性,修正了应变SiGe与应变Si的空穴与电子的迁移率模型;利用Medici软件对该器件的直流与交流特性,以及输入输出特性进行了模拟与分析.模拟结果表明,相对于体Si CMOS器件,该器件具有更好的电学特性,正确的逻辑功能,且具有更短的延迟时间,同时,采用垂直层叠的结构此类器件还可节省约50%的版图面积,有利于电路的进一步集成.     

基于应变Si/SiGe的CMOS电特性模拟研究

提出了一种应变Si/SiGe异质结CMOS结构,采用张应变Si作n-MOSFET沟道,压应变SiGe作p-MOSFET沟道,n-MOSFET与p-MOSFET采用垂直层叠结构,二者共用一个多晶SiGe栅电极.分析了该结构的电学特性与器件的几何结构参数和材料物理参数的关系,而且还给出了这种器件结构作为反相器的一个应用,模拟了其传输特性.结果表明所设计的垂直层叠共栅结构应变Si/SiGe HCMOS结构合理、器件性能提高.     

一种适合制作CMOS的SiGe PMOSFET

在通常适合于制作埋沟SiGe NMOSFET的Si/弛豫SiGe/应变Si/弛豫SiGe缓冲层/渐变Ge组分层的结构上,制作成功了SiGe PMOSFET.这种SiGe PMOSFET将更容易与SiGe NMOSFET集成,用于实现SiGe CMOS.实验测得这种结构的SiGe PMOSFET在栅压为3.5V时最大饱和跨导比用作对照的Si PMOS提高约2倍,而与常规的应变SiGe沟道的器件相当.     

基区Ge组分分布对SiGe pnp HBT的影响

采用SiGe异质结结构提高pnp晶体管的性能,重点研究了Ge组分在基区的三角形分布对晶体管电流增益β和特征频率fτ的影响。三角形分布,又分为起点为零和不为零两种情况。同时为了消除集电结处SiGe异质结的价带势垒对空穴输运的影响,Ge组分向集电区延伸进一步提高了晶体管的性能。得到最大电流增益β可达150和特征频率fτ可达15GHz的pnp SiGe HBT,可以广泛地应用到通信、微波和射频领域。     

绝缘层上应变SiGe沟道p-MOSFET电学特性模拟分析

利用数值模拟软件ISE TCAD对绝缘层上应变SiGe(SGOI)和Si(SOI)p-MOSFET的电学特性进行了二维数值模拟.计算结果表明,与传统的SOI p-MOSFET相比,SGOI p-MOSFET的漏源饱和电流几乎要高出两倍; 其亚阈值电流要高出1～3个数量级.Ge合金组分作为应变SiGe沟道MOSFET的重要参数,就不同Ge合金组分对SGOI p-MOSFET的电学特性的影响也进行了较为深入的研究.随着Ge合金组分的增大,SGOI p-MOSFET的总体电学性能有所提高.     

SiGe／Si异质结器件

本文综述了国际上ＳｉＧｅ／Ｓｉ异质结器件的发展状况，分析了该器件的结构要理，特点，优越性及制造技术，阐述了该器件的广阔应用和对微电子将产的重大影响。     

GeSi/Si Mach-Zehnder干涉型调制器的研制

基于ＧｅＳｉ合金的等离子体色散效应,研制了一种Ｍａｃｈ－Ｚｅｈｎｄｅｒ干涉型调制器,通过对其损耗和调制特征的测试得到：调制器对１．３μｍ光的插入损耗为６．５ｄＢ,最大调制深度达８５％,相应的π相移调制民压为０．９Ｖ,关断电流和调制区的注入电流密度分别为４０ｍＡ和０．９７ｋＡ／ｃｍ＾２。     

High-performance emitter-up/down SiGe HBT's

The experimental results in this paper provide evidence of high-performance symmetric and emitter-down operation of SiGe-HBT's. SiGe-base transistors were fabricated by using Atmospheric-Pressure Chemical Vapor Deposition (APCVD) for the epitaxial growth of SiGe and Si layers, and a novel self-aligned device structure. Current gains of 2000 and 120, cutoff-frequencies of 64 GHz and 14 GHz, and maximum oscillation frequencies of 23 GHz and 10 GHz have been achieved for emitter-up and emitter-down operation, respectively     

Si/SiGe digital optoelectronic switch

The physical parameters and functional characteristics of a Si/SiGe digital optoelectronic switch are reported. The device is found to have bistable electrical states: a high-impedance (40 kΩ) OFF state connected to a low-impedance (100 Ω) ON state by a regime of negative differential resistance. The switching voltage and holding voltage are measured to be 2.6 and 1.3 V, respectively, and the switching current and holding current are measured to be 500 μA and 1 mA, respectively. These DC characteristics are found to be similar to those measured in double heterostructure optoelectronic switching devices manifested in the AlGaAs/GaAs materials system. The DC characteristics of this Si/SiGe digital optoelectronic switch are also found to be sensitive to optical input and temperature     

Si/SiGe heterostructure MITATT diode

The first experimental results on Si/SiGe heterostructure mixed tunnelling avalanche transit time (MITATT) diodes are reported. The layers are grown by MBE. At 103 GHz a very low noise CW output of 25 mW is obtained. With an optimisation of the design higher output powers with still low noise operation are expected     

Ultra flexible SiGe/Si/Cr nanosprings

The electrical and mechanical properties of Si/SiGe rolled-up nanosprings have been investigated. Micromanipulation has been employed to investigate the mechanical properties. For nanosprings under investigation, a linear dependence between applied force and extention is found until the spring is extended to 91% of its original length, moreover, the springs could be reproducibly extended to more than 180% of their original length. An extremely small spring constant of 0.003 N/m has been determined, which is an order of magnitude smaller than that of the most flexible available atomic force microscope (AFM) cantilever (～10^?2 N/m). Thus, it is expected that these springs can be used as ultra-sensitive force sensors. A simple estimation assuming an imaging resolution of approximately 1 nm is adopted for displacement measurement and reveals that using a nanospring fabricated from a 300 nm wide mesa as a visual-based force sensor, a resolution of 3 pN/nm can be provided. The conductivity of nanospirals was analysed and current densities up to 530 kA/cm² were measured. Structures with metallic wires on top of the mesa structures were successfully employed to activate mechanical movements of the structure.     

高电子迁移率Si/SiGe异质结构:缓解性SiGe缓冲层的影响

在不同类型的部分缓解性SiGe缓冲层上生长了n型调制掺杂Si/SiGe异质结构,采用这一材料系统是为了得到足够大的导带突变。对样品进行了各种测试分析,如二次离子质谱,x光摆动像分析,透射电子显微镜分析,卢瑟福背散射分析和变温霍尔测量。在750℃生长的厚的线性渐变SiGe缓冲层样品中得到了最高的霍尔迁移率为1.5K下173000cm~2V~(-1)s~(-1)。这一层序达到的室温迁移率约为1800cm~2V~(-1)s~(-1)。发现不管是用没有Ge组分渐变的一般缓冲层,还是直接用有源层是调制掺杂SiGe势垒开始以缓解应变了的Si阱层,主要是在低温下霍尔迁移率严重地下降。     

Multiple SiGe/Si layers epitaxy and SiGe selective etching for vertically stacked DRAM

Fifteen periods of Si/Si_0.7Ge_0.3 multilayers(MLs) with various Si Ge thicknesses are grown on a 200 mm Si substrate using reduced pressure chemical vapor deposition(RPCVD). Several methods were utilized to characterize and analyze the ML structures. The high resolution transmission electron microscopy(HRTEM) results show that the ML structure with 20 nm Si_0.7Ge_0.3 features the best crystal quality and no defects are observed. Stacked Si_0.7Ge...     

Si／SiGe／Si HBT的优化设计

给出了常温和低温Ｓｉ／ＳｉＧｅ／ＳｉＨＢＴ的设计原则，并进行了讨论。指出了低温和室温ＨＢＴ设计上的差异。这些原则可用于设计特定要求的Ｓｉ／ＳｉＧｅ／ＳｉＨＢＴ。