Dopant effects on the thermal stability of FUSI NiSi

The thermal stability of fully silicided (FUSI) NiSi with arsenic or boron doping on silicon on insulator (SOI) was investigated. After the stacks were subjected to a typical back-end of line (BEOL) thermal annealing in a N₂ ambient, abnormal oxidation of As doped FUSI NiSi stacks is observed by X-ray photoelectron spectroscopy (XPS), and confirmed by high-resolution transmission electron microscopy (HRTEM). X-ray diffraction (XRD) results show Ni-rich phases like Ni₃Si are formed due to abnormal oxidation of FUSI NiSi. In contrast to As doped stacks, no phase transformation nor abnormal oxidation are observed for B doped stacks under similar annealing. However, backside secondary ion mass spectrometry (SIMS) results indicate B penetration through a 3 nm SiON layer into the Si channel after N₂ annealing for 4 h at 400 °C. There is no evidence for Ni diffusion into the Si channel for B doped stacks. However, Ni penetration into the Si channel is observed for As doped stacks due to the enhancement of abnormal oxidation of FUSI NiSi.     

Effects of Carbon on Schottky Barrier Heights of NiSi Modified by Dopant Segregation

The presence of carbon at the interface between NiSi and Si has been found to participate in the process of modification of effective Schottky barrier heights using the dopant segregation (DS) method. Carbon alone results in an increased $phi_{rm bn}$ from 0.7 to above 0.9 eV. Boron diffusion in NiSi is inhibited by carbon, and no B-DS at the NiSi/Si interface occurs below 600 $^{circ}hbox{C}$. Above this temperature, B-DS at this interface is evident thus keeping $phi_{rm bn}$ high. The presence of interfacial carbon leads to an increased interfacial As concentration resulting in beneficial effects in tuning $phi_{rm bp}$ above 1.0 eV by As-DS.      

0.86-nm CET Gate Stacks With Epitaxial$hboxGd_2hboxO_3$High-$k$Dielectrics and FUSI NiSi Metal Electrodes

In this letter, ultrathin gadolinium oxide$(hboxGd_2hboxO_3)$high-$k$gate dielectrics with complementary-metal-oxide-semiconductor (CMOS)-compatible fully silicided nickel-silicide metal gate electrodes are reported for the first time. MOS capacitors with a$hboxGd_2hboxO_3$thickness of 3.1 nm yield a capacitance equivalent oxide thickness of$ CET = hbox0.86 hboxnm$. The extracted dielectric constant is$k = hbox13-hbox14$. Leakage currents and equivalent oxide thicknesses of this novel gate stack meet the International Technology Roadmap for Semiconductors targets for the near term schedule and beyond.     

Electrical Properties of nMOSFETs Using the NiSi:Yb FUSI Electrode

In this letter, nMOSFETs using a NiSi:Yb fully silicide (FUSI) electrode are demonstrated for the first time. We report that the integration of NiSi:Yb FUSI into our reference n-FETs with the respective SiON / HfSiON gate dielectrics results in a V_t reduction from 0.55/0.52 down to 0.30/0.43 V, without degradation of the gate dielectric integrity, channel interface states, and long channel device mobility     

原位水汽生长栅介质界面态特性和可靠性研究

介绍了基于原位水汽生长工艺的超薄栅介质膜的可靠性研究.通过电荷泵测试.对工艺参数与界面态密度的关系进行了定性的分析,然后通过热载流子退化和经时击穿的测试对原位水汽生长栅介质膜的可靠性进行了研究.通过测试发现,提高生长温度或减小氢气在反应气体中的比重可以获得更好的界面特性和可靠性,原位水汽生长工艺存在进一步提高的空间.     

Stoichiometry dependence of Fermi-level pinning in fully silicided (FUSI) NiSi gate on high-K dielectric

Stoichiometry dependence of Fermi-level pinning in a fully silicided (FUSI) NiSi gate on high-K dielectric is investigated. A higher composition ratio of Si in NiSi shows a higher degree of Fermi-level pinning. It has also been found that there is a critical ratio (C/sub crit/) above which there is no Fermi-level pinning, and the C /sub crit/ depends on the underlying gate dielectric material also.     

Performance Evaluation of Inversion Mode and Junctionless Dual-Material Double-Surrounding Gate Si Nanotube MOSFET for 5-nm Gate Length

Semiconductors - In this work, drain current ID for 5-nm gate length with dual-material (DM) double-surrounding gate (DSG) inversion mode (IM) and junctionless (JL) silicon nanotube (SiNT) MOSFET...     

复合型栅氧化层薄膜双栅MOSFET研究

通过对硅膜中最低电位点电位的修正,得到复合型栅氧化层薄膜双栅MOSFET亚阈值电流模型以及阈值电压模型。利用MEDICI软件,针对薄膜双栅MOSFET,对四种复合型栅氧化层结构DIDG MOSFET(Dual insulator double gate MOSFET)进行了仿真。通过仿真可知:在复合型结构中,随着介电常数差值的增大,薄膜双栅器件的短沟道效应和热载流子效应得到更有效的抑制,同时击穿特性也得到改善。此外在亚阈值区中,亚阈值斜率也可以通过栅氧化层设计进行优化,复合型结构器件的亚阈值斜率更小,性能更优越。     

功率MOSFET器件栅电荷测试与分析

栅电荷是表征功率MOSFET器件动态特性的重要参数之一,其测试结果与时间和频率有关,受分布参数、测试夹具和电路结构等因素影响较大。其参数直接影响器件整体性能,设计不好将导致器件没使用时已击穿甚至损坏,在军用功率MOSFET器件研制生产和使用验收中列为必测参数。随着对MOSFET器件可靠性要求的不断提高,栅电荷的测试重要性凸显。针对目前国内外栅电荷测试现状及存在的问题做了详尽阐述,为国内的栅电荷测试提供一定的参考和指导。     

锗预非晶化注入对镍硅(NiSi)金属栅功函数的影响研究

随着超大规模集成电路技术的发展,CMOS器件的制备过程需要同时引入金属栅和超浅结等新的先进工艺技术,因此各种新工艺的兼容性研究具有重要意义.本文研究了超浅结工艺中使用的锗预非晶化对镍硅(NiSi)金属栅功函数的影响.对具有不同剂量Ge注入的NiSi金属栅MOS电容样品的研究表明,锗预非晶化采用的Ge注入对NiSi金属栅的功函数影响很小(小于0.03eV),而且Ge注入也不会导致氧化层中固定电荷以及氧化层和硅衬底之间界面态的增加.这些结果表明,在自对准的先进CMOS工艺中,NiSi金属栅工艺和锗预非晶化超浅结工艺可以互相兼容.     

凹槽栅MOSFET凹槽拐角的作用与影响研究

短沟道效应是小尺寸ＭＯＳＦＥＴ中很重要的物理效应之一，凹槽栅ＭＯＳＦＥＴ对短沟道效应有很强的抑制能力，通过对凹槽栅ＭＯＳＦＥＴ结构，特性的研究，发现凹槽拐角对凹槽栅ＭＯＳＦＥＴ的阈值电压及特性有着显著的影响，凹槽拐角处的阈值电压决定着整个凹槽栅ＭＯＳＦＥＴ的阈值电压，凹槽拐角的曲率半径凹槽ＭＯＳＦＥＴ一个重要的结构参数，通过对凹槽拐角的曲率半径，源漏结深及沟道掺杂浓度进行优化设计，可使凹槽栅ＭＯＳ     

双掺杂多晶Si栅MOSFET的截止频率研究

在前期对双掺杂多晶Si栅(DDPG)LDMOSFET的电场、阈值电压、电容等特性所作分析的基础上,仍然采用双掺杂多晶Si栅结构,以低掺杂漏/源MOS(LDDMOS)为基础,重点研究了DDPG-LDDMOSFET的截止频率特性.通过MEDICI软件,模拟了栅长、栅氧化层厚度、源漏区结深、衬底掺杂浓度以及温度等关键参数对器件截止频率的影响,并与相同条件下P型单掺杂多晶Si栅(p-SDPG)MOSFET的频率特性进行了比较.仿真结果发现,在栅长90 nm、栅氧厚度2 nm,栅极P,n掺杂浓度均为5×1019cm-3条件下,截止频率由78.74 GHz提高到106.92 GHz,幅度高达35.8%.此结构很好地改善了MOSFET的频率性能,得出的结论对于结构的设计制作和性能优化具有一定的指导作用,在射频领域有很好的应用前景.     

Power MOSFET栅电荷分析及结构改进

本文从驱动电路设计者的角度对MOS器件的输入电容和密勒电容进行了详细分析,并从器件基本原理上,对决定栅电荷的寄生元件在不同的栅电压下对栅电荷的作用进行了系统的阐述.最后总结了当前国际上为降低栅电荷提出的最新MOS器件结构.     

超薄栅介质MOSFET直接隧穿电流自洽解模型

采用自洽解方法求解一维薛定谔方程和二维泊松方程,得到电子的量子化能级和相应的浓度分布,利用MWKB方法计算电子隧穿几率,从而得到不同栅偏置下超薄栅介质MOSFET的直接隧穿电流模型。一维模拟结果与实验数据十分吻合,表明了模型的准确性和实用性。二维模拟结果表明,低栅压下,沟道边缘隧穿电流远大于沟道中心隧穿电流,沟道各处的隧穿电流均大于一维模拟结果;高栅压下,隧穿电流在沟道的分布趋于一致,且逼近一维模拟结果。     

浮动电极对屏蔽栅沟槽型MOSFET特性的影响

提出了在屏蔽栅沟槽型MOSFET(SGT)的沟槽侧壁氧化层中形成浮动电极的结构,通过改善电场分布,优化了特征导通电阻与特征栅漏电容。在传统SGT结构的基础上,仅通过增大外延层掺杂浓度,改变浮动电极的长度和位置以及氧化层厚度,最终得到击穿电压为141.1 V、特征导通电阻为55 mΩ·mm²、特征栅漏电容为4.72 pF·mm^-2的浮动电极结构。与相同结构参数的SGT结构相比,在击穿电压不变的条件下,浮动电极结构的特征导通电阻降低了9.3%,Baliga优值提升了13%,特征栅漏电容降低了28.4%。     

掺杂对CdSe-TFT稳定性影响的研究

利用蒸发和溅射工艺,研究了CdSe-TFT的制作,特别对掺In的CdSe-TFT的电性能进行了研究。实验中观察到CdSe掺In后,TFT的I－V特性明显得到改善,得到了性能稳定的TFT器件,利用半导体掺杂理论对此现象进行了解释。     

栅极电阻对GaN MOSFET瞬态特性的影响研究

为了研究栅极电阻对GaN MOSFET的开关速率和输出特性中出现振荡的影响,首先利用MOSFET的基本公式对其导通和关断时的输出瞬态电流进行了理论推导,然后通过实验平台测试GaN MOSFET的瞬态电流值,且与理论值对比,验证栅极电阻带来的影响。实验结果表明,GaN MOSFET的瞬态电流值实验值与理论值基本吻合,在导通和关断时,GaN MOSFET的输出瞬态电流和输出电流的高频震荡均随栅极电阻的增加而减小。栅极电阻从10 Ω变化到100 Ω时,导通时开关速率上升率占总开关速率上升率的84.7%,关断时开关速率下降率占总开关速率下降率的54.06%。在栅极电阻为10~100 Ω范围内,GaN MOSFET具有较快的开关速度。     

Gate Current Modeling and Optimal Design of Nanoscale Non-Overlapped Gate to Source/Drain MOSFET

In this paper, novel nanoscale MOSFET with Source/Drain-to-Gate Non-overlapped and high-k spacer structure has been demonstrated to reduce the gate leakage current for the first time. The gate leakage behaviour of novel MOSFET structure has been investigated with help of compact analytical model and Sentaurus Simulation. Fringing gate electric field through the dielectric spacer induces inversion layer in the non-overlap region to act as extended S/D region. It is found that optimal Source/Drain-to-Gate Non-overlapped and high-k spacer structure has reduced the gate leakage current to great extent as compared to those of an overlapped structure. Further, the proposed structure had improved off current, subthreshold slope and DIBL characteristic. It is concluded that this structure solves the problem of high leakage current without introducing the extra series resistance.     

MOSFET栅下碰撞电离与击穿研究

研究了场板终端技术对改善 MOSFET栅下电场分布和碰撞电离率的作用 ,结果表明 ,MOSFET在高压应用时 ,漏极靠近表面的 PN结处电场最强 ,决定器件的击穿特性。通过对实验研究与计算机模拟结果的分析 ,表明在不同的栅压下 ,此处场板长度的大小对栅下电场强度有直接的影响 ,合理地控制场板长度能有效地提高器件的击穿电压。     

22nm技术节点异质栅MOSFET的特性研究

研究了22 nm栅长的异质栅MOSFET的特性,利用工艺与器件仿真软件Silvaco,模拟了异质栅MOSFET的阈值电压、亚阈值特性、沟道表面电场及表面势等特性,并与传统的同质栅MOSFET进行比较。分析结果表明,由于异质栅MOSFET的栅极由两种不同功函数的材料组成,因而在两种材料界面附近的表面沟道中增加了一个电场峰值,相应地漏端电场比同质栅MOSFET有所降低,所以在提高沟道载流子输运效率的同时也降低了小尺寸器件的热载流子效应。此外,由于该器件靠近源极的区域对于漏压的变化具有屏蔽作用,从而有效抑制了小尺寸器件的沟道长度调制效应,但是由于其亚阈值特性与同质栅MOSFET相比较差,导致漏致势垒降低效应(DIBL)没有明显改善。