共查询到20条相似文献,搜索用时 15 毫秒
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Sang-Su Ha Jong-Woong Kim Jin-Ho Joo Seung-Boo Jung 《Microelectronic Engineering》2007,84(11):2640-2645
This study was focused on the formation and reliability evaluation of solder joints with different diameters and pitches for flip chip applications. We investigated the interfacial reaction and shear strength between two different solders (Sn-37Pb and Sn-3.0Ag-0.5Cu, in wt.%) and ENIG (Electroless Nickel Immersion Gold) UBM (Under Bump Metallurgy) during multiple reflow. Firstly, we formed the flip chip solder bumps on the Ti/Cu/ENIG metallized Si wafer using a stencil printing method. After reflow, the average solder bump diameters were about 130, 160 and 190 μm, respectively. After multiple reflows, Ni3Sn4 intermetallic compound (IMC) layer formed at the Sn-37Pb solder/ENIG UBM interface. On the other hand, in the case of Sn-3.0Ag-0.5Cu solder, (Cu,Ni)6Sn5 and (Ni,Cu)3Sn4 IMCs were formed at the interface. The shear force of the Pb-free Sn-3.0Ag-0.5Cu flip chip solder bump was higher than that of the conventional Sn-37Pb flip chip solder bump. 相似文献
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Joachim Kloeser Paradiso Coskina Rolf Aschenbrenner Herbert Reichl 《Microelectronics Reliability》2002,42(3):391-398
Area array packages (flip chip, CSP and BGA) require the formation of bumps for the board assembly. Since the established bumping methods need expensive equipment or are limited by the throughput, minimal pitch and yield the industry is currently searching for new and lower cost bumping approaches. In this paper the experimental work of stencil printing to create solder bumps for flip chip and wafer level CSP (CSP-WL) is described in detail.This paper is divided into two parts. In the first part of the paper a low cost wafer bumping process for flip chip applications will be studied in particular. The process is based on an electroless Nickel under bump metallization and solder bumping by stencil printing. The experimental results for this technology will be presented and the limits concerning pitch, reproducibility and bump height will be discussed in detail. The second part of the paper is focused on solder paste printing for wafer-level CSPs. In order to achieve large bumps an optimized printing method will be presented. Additionally advanced stencil design will be shown and the achieved results will be compared with conventional methods. 相似文献
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A new reflow parameter, heating factor (Qη), which is defined as the integral of the measured temperature over the dwell time above liquidus, has been proposed in this report. It can suitably represent the combined effect of both temperature and time in usual reflow process. Relationship between reliability of the micro-ball grid array (micro-BGA) package and heating factor has been discussed . The fatigue failure of micro-BGA solder joints reflowed with different heating factor in nitrogen ambient has been investigated using the bending cycle test. The fatigue lifetime of the micro-BGA assemblies firstly increases and then decreases with increasing heating factor. The greatest lifetime happens at Qη near 500 s °C. The optimal Qη range is between 300 and 750 s °C. In this range, the lifetime of the micro-BGA assemblies is greater than 4500 cycles. SEM micrographs reveal that cracks always initiate at the point of the acute angle where the solder joint joins the PCB pad. 相似文献
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Taguchi experiments are designed and carried out with five critical factors that influence the solder bumping of a 200 mm (8 in) wafer by the stencil printing method. These factors are: paste types, squeeze forces, snap-off heights, aperture shapes, and aspect ratios. They are varied to form a two-level L8 orthogonal array experiment. Analysis of mean (ANOM) and analysis of variance (ANOVA) are used to choose the most influential factors. After fixing the most influential factors, a two-level L4 orthogonal array experiment is followed to optimize the remaining material and process parameters. Important results are summarized in this paper which could be very useful for wafer bumping with the stencil printing method 相似文献
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Olivér Krammer László Milán Molnár László Jakab András Szabó 《Microelectronics Reliability》2012,52(1):235-240
In the mass assembly of today’s electronic circuits, solder paste is first printed onto the surface of the assembly boards through a metal mask called a stencil. The possible surface differences in level on the PWB, e.g. marking stickers or other protruding objects keep the stencil away from the PWB during stencil printing, can cause excessive printed volume of the solder paste, and solder bridges or other soldering failures can occur after reflow soldering. If these differences in level are not too high or they are sufficiently far from the soldering pads in lateral direction, the stencil can bend down to the pad during stencil printing and the volume of the deposited solder paste will be as expected.In our research a Finite Element Model (FEM) was created to investigate the stencil deformation and to determine the necessary distance between the pads and the local differences in level to achieve complete stencil contact to the PWB. A simple deformation measuring set-up was designed and fitted together to experimentally determine the mechanical parameters of the stencil and the squeegee, which were necessary for the FEM. PWB surface differences in level in the range of 0–90 μm and stencil foil thicknesses varying between 75 and 175 μm were inserted into the FEM as geometrical parameters and simulations were executed to calculate the minimum distances which are necessary to achieve perfect stencil contact to the PWB. The FEM was verified by comparing simulation results to experimental results obtained by real stencil printing. 相似文献
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Nonconductive paste (NCP) is becoming an alternative material for chip-on-flexible (COF) substrate, where it is able to achieve
a very fine-pitch interconnection for high resolution products. The application of NCP faces the problem that it is initially
a high viscosity liquid, which easily causes voids in the inter-connection. Voids in the interconnection reduce the mechanical
strength in the joints and create moisture entrapment sites, which shorten the reliable performance of the interconnection.
They were revealed using optical microscopy and nondestructive C-mode scanning acoustic microscopy (C-SAM). This study reveals
the factors involved during process control in order to minimize void entrapment in the interconnection. These parameters
include the following: (a) substrate pretreatment, (b) the speed at which the tool heater descends, (c) bonding force, (d)
bonding temperature, and (e) holding time on the bonding stage. These parameters permitted a modification to the surface,
and also brought chemical reaction and viscosity changes to the NCP during the bonding process, which leads to the minimization
of void formation in the specimen. 相似文献
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I. W. Rangelow F. Shi P. Hudek I. Kostic E. Hammel H. Lschner G. Stengl E. Cekan 《Microelectronic Engineering》1996,30(1-4):257-260
Silicon membranes with 2 μm to 6 μm thickness and ≈ 10×10 mm2 mask field have been fabricated with the help of electrochemical etch stop techniques. The Si foil was coated with 0.3 μm thick PECVD Si3N4. Shaped electron beam lithography was done in ARCH (OCG) positive resist. RIE etching into the nitride layer was done with CHF3/Ar/SF6. Silicon trench etching was based on Cl2/Ar/BCl3 plasma chemistry implementing gas chopping. Ion beam proximity printing of the Silicon stencil mask structures was done with 55 keV Helium ions into 0.4 μm thick AZ PN114 negative resist using the Alpha ion projector of the Society for the Advancements of Microelectronics in Austria in the MIBL (Masked Ion Beam Lithography) mode. Pattern transfer of a mask feature of less than 100 nm diameter (25:1 aspect ratio in the stencil mask) could be demonstrated even for a mask to wafer gap of 1 mm. The prospects of fabricating large area (> 100×100 mm2) Silicon stencil masks for MIBL printing of gate levels for ystems (MEMS) is discussed. 相似文献
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研究了焊膏材料特性、针头外形、点涂高度、滞留时间、回复高度、环境温度、针管内液面高度等对焊膏点涂工艺的影响。结果表明:影响焊膏可点涂性的材料特性主要包括焊球粒度、焊膏黏度和合金体积比;在点涂针头的选择上,尖锥形针头比常规直壁针管的针头更优;点涂高度对点涂焊膏量、点涂焊膏点的形貌、高度和直径均有显著影响,其中点涂焊膏量随点涂高度的增加而增加,变化过程可分为完全堵塞阶段、快速增长阶段和相对稳定阶段;此外,回复高度、环境温度、针管内液面高度均对焊膏点涂有显著影响,而滞留时间对焊膏点涂的影响不明显。 相似文献
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以SnAgCu无铅焊膏铺展性能为主要指标,通过回流焊接实验,对用于助焊剂的17种有机酸活性物质进行了筛选。选取两种性能较好的有机酸配成复合活性物质,并对该活性物质的组成进行优化。用湿热试验测试焊后残留物的腐蚀性。结果表明:以羧基官能团比例为3:7的丁二酸和一元酸A混合物作为活性物质,并添加质量约0.66%的乙醇胺调整酸度,得到了pH值约为3的助焊剂;此助焊剂性能优良,可使焊点铺展率达到84%。使用含有此助焊剂的焊膏,采用回流焊接工艺在PCB板上贴装片式元件,所得焊点光亮饱满,且焊后残留物无腐蚀性,可以实现免清洗。 相似文献
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Electronic second level interconnect reliability characterization by accelerated thermal-cycling (ATC) test for long-term mission profile is costly and high time consuming. In order to reduce test duration, the torsion test was applied using some specific test parameters to reproduce the same failure modes found in accelerated thermal cycling (ATC) test and in the field. In this paper, we present the torsion test parameters definition and two demonstrations of torsion test application to accelerate reliability characterization of second level interconnect. The first application is the comparison between full SnPb (tin–lead) and reballed LF (lead-free) packages using SnPb balls. In the second the reliability of ceramic BGA solder joints using different solder paste volume was evaluated. In both cases, ATC test results were used as reference. The results suggest that torsion test is a valuable test method and can be applied to evaluate the impact of design and process variations in very short time. 相似文献
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Dionysios Manessis Rainer Patzelt Andreas Ostmann Rolf Aschenbrenner Herbert Reichl 《Microelectronics Reliability》2004,44(5):3189-803
Stencil printing remains the technology route of choice for flip chip bumping because of its economical advantages over traditionally costly evaporation and electroplating processes. This paper provides the first research results on stencil printing of 80 and 60 μm pitch peripheral array configurations with Type 7 Sn63/Pb37 solder paste. In specific, the paste particle size ranges from 2 to 11μm with an average particle size of 6.5 μm taken into account for aperture packing considerations. Furthermore, the present study unveils the determining role of stencil design and paste characteristics on the final bumping results. The limitations of stencil design are discussed and guidelines for printing improvement are given. Printing of Type 7 solder paste has yielded promising results. Solder bump deposits of 25 and 42 μm have been demonstrated on 80 μm pitch rectangular and round pads, respectively. Stencil printing challenges at 60 μm pitch peripheral arrays are also discussed. 相似文献
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