Interfacial reaction and joint reliability of fine-pitch flip-chip solder bump using stencil printing method

This study was focused on the formation and reliability evaluation of solder joints with different diameters and pitches for flip chip applications. We investigated the interfacial reaction and shear strength between two different solders (Sn-37Pb and Sn-3.0Ag-0.5Cu, in wt.%) and ENIG (Electroless Nickel Immersion Gold) UBM (Under Bump Metallurgy) during multiple reflow. Firstly, we formed the flip chip solder bumps on the Ti/Cu/ENIG metallized Si wafer using a stencil printing method. After reflow, the average solder bump diameters were about 130, 160 and 190 μm, respectively. After multiple reflows, Ni₃Sn₄ intermetallic compound (IMC) layer formed at the Sn-37Pb solder/ENIG UBM interface. On the other hand, in the case of Sn-3.0Ag-0.5Cu solder, (Cu,Ni)₆Sn₅ and (Ni,Cu)₃Sn₄ IMCs were formed at the interface. The shear force of the Pb-free Sn-3.0Ag-0.5Cu flip chip solder bump was higher than that of the conventional Sn-37Pb flip chip solder bump.     

溶剂对细间距用无铅焊锡膏抗热塌性的影响

焊接后出现桥连、短路是高密度电子组装中经常遇到的问题。通过回流焊接实验和抗热塌性实验,研究了助焊剂中溶剂的复配对焊锡膏抗热塌性的影响。结果表明:四氢糠醇与丙二醇苯醚按质量比3:2复配得到的焊锡膏焊点光亮饱满,铺展率达到84.83%,抗热塌性(150℃)优异。四氢糠醇与聚乙二醇单甲醚250(MPEG250)按质量比1:1复配得到的焊锡膏助焊性良好,焊点铺展率高达86.55%,具有优异的抗热塌性(150℃),并在180℃下仍表现优异,且最小不桥连间距为0.06 mm,满足超细间距条件下的焊接要求。     

Bump formation for flip chip and CSP by solder paste printing

Area array packages (flip chip, CSP and BGA) require the formation of bumps for the board assembly. Since the established bumping methods need expensive equipment or are limited by the throughput, minimal pitch and yield the industry is currently searching for new and lower cost bumping approaches. In this paper the experimental work of stencil printing to create solder bumps for flip chip and wafer level CSP (CSP-WL) is described in detail.This paper is divided into two parts. In the first part of the paper a low cost wafer bumping process for flip chip applications will be studied in particular. The process is based on an electroless Nickel under bump metallization and solder bumping by stencil printing. The experimental results for this technology will be presented and the limits concerning pitch, reproducibility and bump height will be discussed in detail. The second part of the paper is focused on solder paste printing for wafer-level CSPs. In order to achieve large bumps an optimized printing method will be presented. Additionally advanced stencil design will be shown and the achieved results will be compared with conventional methods.     

Study of micro-BGA solder joint reliability

A new reflow parameter, heating factor (Q_η), which is defined as the integral of the measured temperature over the dwell time above liquidus, has been proposed in this report. It can suitably represent the combined effect of both temperature and time in usual reflow process. Relationship between reliability of the micro-ball grid array (micro-BGA) package and heating factor has been discussed . The fatigue failure of micro-BGA solder joints reflowed with different heating factor in nitrogen ambient has been investigated using the bending cycle test. The fatigue lifetime of the micro-BGA assemblies firstly increases and then decreases with increasing heating factor. The greatest lifetime happens at Q_η near 500 s °C. The optimal Q_η range is between 300 and 750 s °C. In this range, the lifetime of the micro-BGA assemblies is greater than 4500 cycles. SEM micrographs reveal that cracks always initiate at the point of the acute angle where the solder joint joins the PCB pad.     

化学镀镍、模版印刷法制备倒扣芯片焊料凸点

回顾了低成本制备芯片上焊料凸点的方法,即化学镀镍制备凸点下金属层、模版印刷焊料,最后回流形成焊料凸点,并综述了该方法的最新研究进展.     

Taguchi design of experiment for wafer bumping by stencil printing

Taguchi experiments are designed and carried out with five critical factors that influence the solder bumping of a 200 mm (8 in) wafer by the stencil printing method. These factors are: paste types, squeeze forces, snap-off heights, aperture shapes, and aspect ratios. They are varied to form a two-level L8 orthogonal array experiment. Analysis of mean (ANOM) and analysis of variance (ANOVA) are used to choose the most influential factors. After fixing the most influential factors, a two-level L4 orthogonal array experiment is followed to optimize the remaining material and process parameters. Important results are summarized in this paper which could be very useful for wafer bumping with the stencil printing method     

Modelling the effect of uneven PWB surface on stencil bending during stencil printing process

In the mass assembly of today’s electronic circuits, solder paste is first printed onto the surface of the assembly boards through a metal mask called a stencil. The possible surface differences in level on the PWB, e.g. marking stickers or other protruding objects keep the stencil away from the PWB during stencil printing, can cause excessive printed volume of the solder paste, and solder bridges or other soldering failures can occur after reflow soldering. If these differences in level are not too high or they are sufficiently far from the soldering pads in lateral direction, the stencil can bend down to the pad during stencil printing and the volume of the deposited solder paste will be as expected.In our research a Finite Element Model (FEM) was created to investigate the stencil deformation and to determine the necessary distance between the pads and the local differences in level to achieve complete stencil contact to the PWB. A simple deformation measuring set-up was designed and fitted together to experimentally determine the mechanical parameters of the stencil and the squeegee, which were necessary for the FEM. PWB surface differences in level in the range of 0–90 μm and stencil foil thicknesses varying between 75 and 175 μm were inserted into the FEM as geometrical parameters and simulations were executed to calculate the minimum distances which are necessary to achieve perfect stencil contact to the PWB. The FEM was verified by comparing simulation results to experimental results obtained by real stencil printing.     

Process optimization to overcome void formation in nonconductive paste interconnections for fine-pitch applications

Nonconductive paste (NCP) is becoming an alternative material for chip-on-flexible (COF) substrate, where it is able to achieve a very fine-pitch interconnection for high resolution products. The application of NCP faces the problem that it is initially a high viscosity liquid, which easily causes voids in the inter-connection. Voids in the interconnection reduce the mechanical strength in the joints and create moisture entrapment sites, which shorten the reliable performance of the interconnection. They were revealed using optical microscopy and nondestructive C-mode scanning acoustic microscopy (C-SAM). This study reveals the factors involved during process control in order to minimize void entrapment in the interconnection. These parameters include the following: (a) substrate pretreatment, (b) the speed at which the tool heater descends, (c) bonding force, (d) bonding temperature, and (e) holding time on the bonding stage. These parameters permitted a modification to the surface, and also brought chemical reaction and viscosity changes to the NCP during the bonding process, which leads to the minimization of void formation in the specimen.     

Silicon stencil masks for masked ion beam lithography proximity printing

Silicon membranes with 2 μm to 6 μm thickness and ≈ 10×10 mm² mask field have been fabricated with the help of electrochemical etch stop techniques. The Si foil was coated with 0.3 μm thick PECVD Si₃N₄. Shaped electron beam lithography was done in ARCH (OCG) positive resist. RIE etching into the nitride layer was done with CHF₃/Ar/SF₆. Silicon trench etching was based on Cl₂/Ar/BCl₃ plasma chemistry implementing gas chopping. Ion beam proximity printing of the Silicon stencil mask structures was done with 55 keV Helium ions into 0.4 μm thick AZ PN114 negative resist using the Alpha ion projector of the Society for the Advancements of Microelectronics in Austria in the MIBL (Masked Ion Beam Lithography) mode. Pattern transfer of a mask feature of less than 100 nm diameter (25:1 aspect ratio in the stencil mask) could be demonstrated even for a mask to wafer gap of 1 mm. The prospects of fabricating large area (> 100×100 mm²) Silicon stencil masks for MIBL printing of gate levels for

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ystems (MEMS) is discussed.     

无铅焊膏用助焊剂研制

对助焊剂的活性组分和其他组分采用正交试验进行筛选,根据工业标准对其进行了焊料铺展面积测试,效果较好的活性剂进行复合处理,对配制出的活性剂溶液加入松香配制成助焊剂进行性能测试.结果表明:当有机酸和三乙醇胺的质量比为12:1,占助焊剂质量分数的13.68％时,溶液的pH值达到3.94,扩展率可达80.06％,钎焊后的焊点光...     

无铅焊膏的设计与展望

分析了无铅焊膏的构成和技术要求。对无铅焊膏用焊粉及助焊剂配方设计的现状进行了讨论,焊粉的成分多为Sn、Ag和Cu,粒度越来越多地采用20μm;助焊剂多为改性松香、有机酸活化剂等。展望了无铅焊膏的研究与发展趋势。     

点涂焊膏的制备工艺及性能研究

使用了润湿力测试和黏度测试的方法来探究点涂焊膏的制备工艺并最终获得性能优异的产品。配合点胶机与空气压缩机的使用,探讨了点涂过程中点涂滞留时间、黏度和点涂压力对点涂量的影响。结果表明:对于黏度、针头内径、点涂滞留时间均固定的点涂焊膏,点涂量随压力的增大而增大,并呈现出拟合程度很好的线性关系。     

焊膏点涂工艺技术研究

研究了焊膏材料特性、针头外形、点涂高度、滞留时间、回复高度、环境温度、针管内液面高度等对焊膏点涂工艺的影响。结果表明:影响焊膏可点涂性的材料特性主要包括焊球粒度、焊膏黏度和合金体积比;在点涂针头的选择上,尖锥形针头比常规直壁针管的针头更优;点涂高度对点涂焊膏量、点涂焊膏点的形貌、高度和直径均有显著影响,其中点涂焊膏量随点涂高度的增加而增加,变化过程可分为完全堵塞阶段、快速增长阶段和相对稳定阶段;此外,回复高度、环境温度、针管内液面高度均对焊膏点涂有显著影响,而滞留时间对焊膏点涂的影响不明显。     

无铅焊膏用无卤素松香型助焊剂的研制

通过筛选试验,调整溶剂、松香和活化剂的含量,确定助焊剂中主要成分的最佳配比。根据国标GB/T9491—2002,测试助焊剂的扩展率、腐蚀性及其他性能,并根据日本工业标准JISZ3198—4—2003进行润湿力测试。结果表明:当助焊剂中有机酸活化剂质量分数为9%、m(水白松香):m(聚合松香)为2:3时,助焊剂具有良好的物理稳定性和润湿性,平均扩展率最高能达到76.00%。焊后铜片无腐蚀,残留物少且成透明膜状。     

SnAgCu无铅焊膏用活性物质研究

以SnAgCu无铅焊膏铺展性能为主要指标,通过回流焊接实验,对用于助焊剂的17种有机酸活性物质进行了筛选。选取两种性能较好的有机酸配成复合活性物质,并对该活性物质的组成进行优化。用湿热试验测试焊后残留物的腐蚀性。结果表明:以羧基官能团比例为3:7的丁二酸和一元酸A混合物作为活性物质,并添加质量约0.66%的乙醇胺调整酸度,得到了pH值约为3的助焊剂;此助焊剂性能优良,可使焊点铺展率达到84%。使用含有此助焊剂的焊膏,采用回流焊接工艺在PCB板上贴装片式元件,所得焊点光亮饱满,且焊后残留物无腐蚀性,可以实现免清洗。     

无铅焊膏用助焊剂的制备与研究

无铅焊膏用助焊剂需要一定的黏性,选择有机酸和有机胺混合作为活性物质,配合一定量的松香配制出一种助焊剂。通过控制助焊剂中松香的含量,降低不挥发物的含量,减少残留物对元器件的腐蚀。依据标准对所配制的助焊剂进行了性能测试,并与一种松香含量较高的助焊剂比较。结果表明:助焊剂的松香含量降低约10%,在260℃焊接后不挥发物含量降低了近6%,黏度较好,无卤化物,无毒,环保,符合焊膏用助焊剂的要求。     

Torsion test applied for reballing and solder paste volume evaluation

Electronic second level interconnect reliability characterization by accelerated thermal-cycling (ATC) test for long-term mission profile is costly and high time consuming. In order to reduce test duration, the torsion test was applied using some specific test parameters to reproduce the same failure modes found in accelerated thermal cycling (ATC) test and in the field. In this paper, we present the torsion test parameters definition and two demonstrations of torsion test application to accelerate reliability characterization of second level interconnect. The first application is the comparison between full SnPb (tin–lead) and reballed LF (lead-free) packages using SnPb balls. In the second the reliability of ceramic BGA solder joints using different solder paste volume was evaluated. In both cases, ATC test results were used as reference. The results suggest that torsion test is a valuable test method and can be applied to evaluate the impact of design and process variations in very short time.     

Technical challenges of stencil printing technology for ultra fine pitch flip chip bumping

Stencil printing remains the technology route of choice for flip chip bumping because of its economical advantages over traditionally costly evaporation and electroplating processes. This paper provides the first research results on stencil printing of 80 and 60 μm pitch peripheral array configurations with Type 7 Sn63/Pb37 solder paste. In specific, the paste particle size ranges from 2 to 11μm with an average particle size of 6.5 μm taken into account for aperture packing considerations. Furthermore, the present study unveils the determining role of stencil design and paste characteristics on the final bumping results. The limitations of stencil design are discussed and guidelines for printing improvement are given. Printing of Type 7 solder paste has yielded promising results. Solder bump deposits of 25 and 42 μm have been demonstrated on 80 μm pitch rectangular and round pads, respectively. Stencil printing challenges at 60 μm pitch peripheral arrays are also discussed.     

SMT无铅电子焊膏活性剂的研究

选择腐蚀性较低的有机酸作为制备无铅电子焊膏活性剂的原料。对五种有机酸进行筛选和复合选取,并进行回流焊接模拟。按国家标准(GB/T9491—2002)对其铺展率、腐蚀性进行了测试。结果表明,选用w(己二酸)为60%和w(丁二酸)为40%的混合酸作为活性剂,具有良好的润湿性和助焊活性,铺展率在87%左右。焊后残留少,腐蚀性弱,焊点饱满光亮,焊层薄而明晰。     

低卤素无铅焊锡膏研制

针对当前高卤素无铅焊锡膏腐蚀性较大的缺点,研制出一种低卤素无铅焊锡膏,并测试其主要性能参数,如黏度、润湿性、卤素含量、坍塌性等。结果表明:该焊锡膏的黏度为195Pa·s,卤素质量分数为0.023%,其他性能符合IPCJ—STD—005等行业要求。