一种高效率的二相位CMOS高压发生器

随着电源电压的不断降低和芯片面积的不断减小，电荷泵的效率已成为MOS电荷泵电路设计过程中最为人们关心的问题之一，由于传统的Dickson MOS电荷泵在每个传输管上都有问值电压的损失，使得它的效率很低，为了解决这一问题，各种电荷泵电路在不断地出现，四相位MOS电荷泵电路自发明以来，得到了广泛的应用，但是它需要产生四个时钟，增大了面积；更为重要的是，由于四相位电荷泵要求在一个周期内提供四个互不重叠的高电平，从而限制了时钟频率的提高。本文在四相位电荷泵的基础上，提出了一种新型的二相位的电荷泵电路，解决了提高效率和增加芯片面积以及时钟频率提升的矛盾。     

Measurement of transfer efficiency of charge-coupled devices

A simple method for measuring the transfer efficiency of charge- coupled devices is described. It is based on the effect of charge pumping in MOS devices and has the advantages that (1) it requires a simple device and simple pulsing circuitry; and (2) the lost charge is evaluated from d.c. measurement.     

Application of charge pumping technique for sub-micron MOSFET characterization

In this paper, charge pumping technique for MOSFET interface characterization will be reviewed. The basic principles of charge pumping technique will be elaborated and its evolution as an excellent tool for a thorough characterization of MOSFET interface properties will be illustrated. Published results regarding the applicability of charge pumping technique for a study of sub-micron MOSFET interface and its degradation under various electrical stress conditions and radiation will be analyzed. The effect of geometric components on charge pumping current as well as the recent reports of single interface trap characterization in sub-micron MOSFETs will be described. The application of charge pumping technique at cryogenic temperatures and in other MOS based devices will also be included.     

Determination of interface trap capture cross sections usingthree-level charge pumping

A modified three-voltage-level charge pumping (CP) technique is described for measuring interface trap parameters in MOSFETs. Charge pumping (CP) is a technique for studying traps at the Si-SiO₂ interface in MOS transistors. In the CP technique, a pulse is applied to the gate of the MOSFET which alternately fills the traps with electrons and holes, thereby causing a recombination current I_cp to flow in the substrate. With this technique, interface trap capture cross sections for both electrons and holes may be determined as a function of trap energy in a single device. It is demonstrated that a modified three-level charge pumping method may be used to determine not only interface trap densities but also to capture cross sections as a function of trap energy. The trap parameters are obtained for both electrons and holes using a single MOSFET     

基于电荷泵技术的MOS器件界面特性测量方法

随着CMOS工艺的发展,栅介质层厚度不断减薄,导致栅漏电流不断增大,这使传统测量界面态的方法应用受到限制。介绍了采用电荷泵技术用于MOS器件Si/SiO2界面特性研究,分别研究了脉冲频率、反偏置电压、脉冲幅值和占空比对泵电流的影响,对突变曲线做了深入的理论分析,指出了需要严格的选择脉冲频率、幅值、反偏置电压和占空比,才能保证测量的准确性。这些探索为电荷泵技术在MOS器件中的界面电荷测量和电荷泵曲线分析提供实验指导和理论依据。     

In-depth exploration of Si-SiO2 interface traps in MOStransistors using the charge pumping technique

It is shown that the charge pumping (CP) technique can be used for extraction of the depth concentration profile of traps situated in the oxide of metal-oxide-semiconductor (MOS) transistors, near and at the Si-SiO₂ interface. The trap density is obtained from the variation of the charge pumping current as a function of frequency, the other measurement parameters being kept constant. The concentration profiles are measured on n and p-channel transistors from several technologies, and on virgin and stressed devices. The results show that the trap concentration decreases rapidly from the Si-SiO₂ interface in the direction of the oxide depth and suggest that it becomes constant at a fraction of a nanometer from the silicon interface. The method easily demonstrates the trap creation due to Fowler-Nordheim stress. The profiles compare favorably with those measured using a new drain-current transient technique. In all cases, the integration of the depth concentration profiles leads to the interface trap densities measured using the conventional charge pumping method     

一种低压改进型MOS电荷泵电路的设计

针对使用标准CMOS技术实现的传统电荷泵输出电压较低的不足,文中提出将基本的电荷转移开关进行改进的MOS电荷泵,在泵送增益增加电路的基础上,通过在泵的输出级增加第3个控制信号来提高电荷泵的电压增益,以得到更高的输出电压,将其作为无线传感器的能量收集电路。仿真结果表明,该改进型电荷泵电路适合于低电压设备,并具有较高的泵送增益。其输出电压在同类电荷泵中最高,在1.5 V电源条件下,可高达8.5 V。     

MOS charge pumps for low-voltage operation

New MOS charge pumps utilizing the charge transfer switches (CTSs) to direct charge flow and generate boosted output voltage are described. Using the internal boosted voltage to backward control the CTS of a previous stage yields charge pumps that are suitable for low-voltage operation. Applying dynamic control to the CTSs can eliminate the reverse charge sharing phenomenon and further improve the voltage pumping gain. The limitation imposed by the diode-configured output stage can be mitigated by pumping it with a clock of enhanced voltage amplitude. Using the new circuit techniques, a 1.2-V-to-3.5-V charge pump and a 2-V-to-16-V charge pump are demonstrated     

Oxide current in MOS transistors operated under charge pumping conditions

The present paper describes an alternative approach for isolating the oxide current from the gate current (GC) and its use for characterizing the bulk oxide in MOS transistors. The method is based on measurements of the gate as well as the substrate currents of MOS transistors pulsed by a train of square wave pulses under charge pumping conditions.The measurements are done on various experimental devices and different gate and drain/source voltage biasing. The GC has been measured and was found to be of typical behavior when it is plotted with respect to the gate voltage. Moreover, the gate and substrate currents are found to be of complementary shapes when plotted with respect to gate voltage. This behavior is made useful in studying and characterizing the oxide and the interface of MOS transistors.     

MOS器件界面态与陷阱电荷分离方法研究

对MOS结构器件．要分离由辐射效应引起的界面态电荷与氧化层陷阱电荷的方法有根多种．如中电带压法、电荷泵法和双晶体管法就是目前比较常用、有效的方法,分析了这些方法的优点和局限性。     

Observation of near-interface oxide traps with the charge-pumpingtechnique

In studies of MOS devices with the charge pumping technique, the authors have encountered a low-frequency increase in the charge recombined per cycle, which they attribute to the charging and discharging of traps located within a tunneling distance of the Si-SiO ₂ interface, i.e., near-interface oxide traps. MOS devices subjected to ionizing radiation as well as ultrathin tunnel oxide polysilicon-oxide-nitride-oxide-silicon (SONOS) nonvolatile memory devices possess a high density of near-interface oxide traps. When the charge recombined per cycle is examined as a function of frequency, a breakpoint is observed at a particular frequency with an inverse equivalent to a trap-to-trap tunneling time constant     

Tunneling component suppression in charge pumping measurement and reliability study for high-k gated MOSFETs

Although charge pumping (CP) is a powerful technique to measure the energy and spatial distributions of interface trap and oxide trap in MOS devices, the parasitic gate leakage current in it is the bottleneck. A CP method was modified and applied to high-k gate dielectric in this work to separate the CP current from the parasitic tunneling component in MOS devices. The stress-induced variations of electrical parameters in high-k gated MOS devices were investigated and the physical mechanism was studied by the modified CP technique. The stress-induced trap generation for devices with HfO₂-dominated high-k gate dielectrics is like mobile defect; while that with SiO₂-dominated ones is similar to the near-interface/border trap.     

Spectroscopic charge pumping: A new procedure for measuringinterface trap distributions on MOS transistors

An approach to the application of the charge pumping technique is proposed as a tool for the measurement of interface trap energy distributions in small area MOS transistors. The new approach is spectroscopic in nature, i.e., only one energy window is defined, and forced to move through the bandgap by changing the sample temperature. This method has the advantages of addressing a larger part of the bandgap as compared to the classical approach, of reducing the complication in the processing of the data, and of yielding information about the hole and electron capture cross sections separately. Experiments performed on both n-channel and p-channel MOS transistors reveal that, in the temperature (energy) range studied, the interface-trap distribution is slowly varying with energy and that the trap capture cross section is nearly constant over energy and temperature     

Determination of spatial surface state density distribution in MOS and SIMOS transistors after channel hot electron injection

The charge pumping technique has been adapted for the determination of the spatial distribution of the interface state density in the channel region of short channel MOS or SIMOS transistors. This spatial distribution is shown to be modified by channel hot electron injection and provides information on the location and width of the injection region.     

Hot-carrier degradation behavior of N- and P-channel MOSFET's underdynamic operation conditions

An in-depth study of the dynamic hot-carrier degradation behavior of N- and P-channel MOS transistors was performed based on the change of charge pumping and I-V characteristics. It is shown that for transistors with channel lengths ranging from 2 to 0.5 μm and frequencies up to 100 MHz the degradation under dynamic stress can completely be described as a quasi-static degradation, provided all static degradation effects are taken into account in the appropriate way. This means that the influence of post-stress effects and charge buildup or charge detrapping have to be considered     

The use of charge pumping currents to measure surface state densities in MOS transistors

A method is described for determining the surface-state density at the oxide interface in the channel of an MOS transistor from the charge pumping current flowing to the substrate when gate pulses are applied. From this simple measurement the surface state density can be determined as a function of gate voltage and if a quasi-static C-V characteristic is also measured for the gate of the transistor then the voltage distribution can be converted into an energy distribution.Representative results obtained on a set of commercial transistors show a large increase in the surface-state density near the middle of the band-gap after negative-bias thermal-stressing.     

Correlation of the leakage current and charge pumping in silicon oninsulator gate-controlled diodes

The leakage and charge pumping currents were measured in gate-controlled MOS p-i-n diodes fabricated on thin SIMOX substrates. The efficiencies of the techniques as well as their complementary features are analyzed for various experimental conditions. The interface properties of device-grade SIMOX wafers are characterized and shown to be compatible with VLSI requirements. Special interface coupling effects, which occur only in fully depleted SOI devices and modify the conventional signature of charge pumping and leakage current, are thoroughly investigated     

An evaluation of MOS interface-trap charge pump as an ultralow constant-current generator

Explores the MOS interface-trap charge-pump as an ultralow constant-current generator for analog CMOS applications. Charge pumping techniques in general are more suitable than conventional continuous-time techniques for ultralow current generation because the linear controllability of current by frequency is maintained regardless of the level of current. An interface-trap pump has the same property but the minimum charge it puts out per cycle is at least two orders of magnitude smaller than that of a switched-capacitor charge pump. This helps generate the same current more accurately at a much higher frequency with a much smaller filter capacitance. The paper presents a simplified model of the terminal characteristics of the interface-trap pump and an evaluation of its performance as a stand-alone current generator. Cascoding and complementary pumping are introduced as measures of performance improvement. Temperature sensitivity, pulse feedthrough, controllability, matching, reliability, and trimming issues are addressed. Transconductor circuits built with the charge pump are presented and experimentally evaluated.     

Characterization of ultra-thin SiO2 by capacitance-voltage and charge pumping measurements

In this paper, we present results on electrical measurements of ultra thin SiO₂ layers (from 3.5 nm down to 1.7 nm), used as gate dielectric in metal-oxide-semiconductors (MOS) devices. Capacitance-voltage (C-V) measurements and simulations on MOS capacitors have been used for extracting the electrical oxide thickness. The SiO₂/Si interface and oxide quality have been analyzed by charge pumping (CP) measurements. The mean interface traps density is measured by 2-level CP, and the energy distribution within the semiconductor bandgap of these traps are investigated by 3-level charge pumping measurements. A comparison of the energy distribution of the SiO₂/Si interface traps is made using classical and quantum simulations to extract the surface potential as a function of the gate signal. When the gate oxide thickness <3.5 nm, we prove that it is mandatory to take into account the quantum effects to obtain a more accurate energy distribution of the SiO₂/Si interface traps. We also explain the increase of the apparent interface traps density measured by 2-levels CP with the increase of the oxide thickness, for transistors made from the same technological process.     

The influence of stud bumping stress on device degradation in scaled MOSFETs

This paper presents the effect of area bumping on device degradation in scaled metal-oxide-semiconductor field-effect transistors (MOSFETs). We have investigated the gate channel length dependence of g_m degradation after stud bumping above the MOSFETs and changes in the charge pumping currents for those devices. The von Mises’s equivalent stress is used to simulate the distribution of mechanical stress at the gate edges. From the relationship between the distribution of the von Mises’s equivalent stress and the change in the charge pumping currents after stud bumping, we show that stress concentrates within 0.1 μm of the gate edges. Furthermore, by estimating the amount of increased interface-state density we predicted that stud bumping stress greatly influences the device degradation of scaled MOS devices.