忆阻在混沌电路中的应用综述

忆阻是被认为是除电阻、电容、电感外的第四种基本电路元件.具有记忆功能的非线性电阻.作为基本元件的忆阻器出现,必将导致电子电路的结构体系、原理、设计理论的变革,并促进电子行业新的应用领域的发展.本文从忆阻在混沌系统中的应用来介绍忆阻的应用现状.先介绍忆阻特性和原理,然后引入忆阻器应用在混沌领域的研究成果以及电路仿真忆阻电路.     

忆阻器存储研究与展望

随着信息呈现爆炸式增长,而CMOS的工艺尺寸逐步接近其理论极限尺寸,新型纳米级存储器件的需求日趋迫切.忆阻器被认为具有替代动态随机存储器,适应海量存储的巨大潜力.在综述忆阻器与忆阻系统概念的产生与发展的基础上,讨论忆阻器作为存储单元的特性,综述了忆阻器的阻变存储结构以及相对应的读写方法.在总结分析目前研究存在问题的基础上,探讨了今后的研究方向.     

基于改进忆阻器的高通滤波器设计与仿真

针对传统的忆阻器模型存在不能很好地与HP实验室提出的忆阻器物理模型中忆阻器的阻值变化特点相符的问题,提出了一种改进的带有阈值电压的忆阻器模型,该模型能很好地模拟忆阻器的"激活"现象,其特性与HP实验室的忆阻器物理模型相符;基于该改进模型设计了一种高通滤波器电路,该电路通过改变忆阻器阻值控制电路的输出信号来改变忆阻器的阻值,从而实现了滤波器截止频率的调节。SPICE仿真结果验证了设计的正确性。     

基于MNIST的忆阻神经网络稳定性研究

为了探究忆阻器的稳定性问题对忆阻神经网络性能的影响,基于等效电阻拓扑结构的忆阻器模型,搭建了一个将忆阻器作为突触的BP神经网络,并利用MNIST数据集对该网络进行训练和测试。忆阻器的稳定性问题通过设置忆阻器参数波动来模拟,最终发现忆阻器一定程度内的性能波动会促进神经网络的收敛,但波动过大则会降低网络的收敛速度。为了表征波动的临界程度,测得了基于忆阻器模型的各参数的最大波动范围,并进一步计算出忆阻器件工艺层次参量的取值范围,为忆阻神经网络硬件化中忆阻器件的工艺制造和选用提供了参考。     

忆阻细胞神经网络在车牌定位中的应用

将新型的电路元件忆阻器与传统细胞神经网络相结合,构建出体积小、功耗低、计算速度快的忆阻细胞神经网络。用该网络实现对车牌图像定位的预处理,对应的计算机仿真结果验证了方案的有效性。提出的忆阻细胞神经网络将提高硬件电路实现的集成度,同时也有利于车牌识别速度和效率的提高。     

基于忆阻器的连续学习混沌神经网络

忆阻器具有独特的记忆功能和连续可变的电导状态,在人工智能与神经网络等研究领域具有巨大的应用优势.详细推导了忆阻器的电荷控制模型,将纳米忆阻器与具有智能信息处理能力的混沌神经网络相结合,提出了一种新型的基于忆阻器的连续学习混沌神经网络模型.利用忆阻器可直接实现网络中繁多的反馈与迭代,即完成外部输入对神经元及神经元之间相互作用的时空总和.提出的忆阻连续学习混沌神经网络可以实现对已知模式和未知模式的区分,并能对未知模式进行自动学习和记忆.给出的计算机仿真验证了方案的可行性.由于忆阻器具有纳米级尺寸和自动的记忆能力,该方案有望大大简化混沌神经网络结构.     

约束重编程单元数量的忆阻器阵列闭环重映射算法

忆阻器阵列能够有效地加速神经网络中的矩阵运算,但会受到老化的影响,导致忆阻器阵列计算精度不满足要求.为了继续使用忆阻器阵列,提出一种基于重编程忆阻单元数量约束的闭环重映射算法.首先根据忆阻器阵列的老化分布得出行偏差矩阵;然后以行偏差矩阵中的最小值为起始点开始映射,直至重映射关系形成闭环;通过在映射过程中设置行偏差约束,使得重映射后的行偏差总和尽可能小,达到提高计算精度的目的;通过对重编程单元数量进行约束,尽可能减少需要重新编程的忆阻单元数量,减轻重编程造成的忆阻器阵列老化.在Pytorch上采用MINST数据集进行仿真测试的实验结果表明,所提算法不仅能够有效地提高忆阻器阵列的计算精度,而且与国际上同类方法相比,在达到相同计算精度的前提下,最多可以减少75.43%的重编程单元数.     

面向电压降的忆阻神经网络精度优化EI北大核心CSCD

由于忆阻器交叉阵列自身的模拟特性可高效实现乘累加运算,因此,它被广泛用于构建神经形态计算系统的硬件加速器.然而,纳米线电阻的存在,会引起忆阻器与纳米线构成的电阻网络出现电压降问题,导致忆阻器阵列的输出信号损失而影响神经网络的精度.分析忆阻器电压降与忆阻器状态、位置,输出电流和输出位置的关系,通过稀疏映射优化电压降,并采用输出补偿进一步提高输出精度.仿真实验的结果表明,该方法可以有效地解决电压降引起的问题,忆阻神经网络在手写数字数据集MNIST的识别率达到95.8%,较优化前提升了33.5%.     

忆阻器模拟电路及其低通滤波电路研究

设计一个具有斜8字型伏安特性的忆阻器模拟电路模型,并将此模型应用于构建低通滤波电路。进行Multisim仿真并制作了相应的实物电路,仿真和实验结果表明该电路模型可以正确模拟忆阻器的特性,由其构建的忆阻低通滤波电路具有时变特性。     

忆阻器的温度效应改进模型及其仿生神经突触传递

突触传递是温度敏感的,由于缺乏温度依赖性的突触电导分析模型,无法在神经系统建模时包括温度效应.忆阻器因其阻值连续可变和纳米尺寸的优势,被广泛认为可以模拟生物突触.本文通过改进忆阻保留值和考虑温度对离子迁移和扩散的影响,提出一种新的氧化钨忆阻器模型,此模型更加符合忆阻器的实际行为特性.首先,改进的数学模型不仅具有原模型的功能,同时可以拟合忆阻器的实际遗忘规律.另外,将此忆阻器作为生物突触耦合两个相同的HH神经元,能够体现温度对突触传递的影响,即温度上升引起氧空位迁移和扩散速率发生变化,导致忆阻器电导变化速率加快,进一步影响兴奋性突触后膜电位幅值和放电次数,而相关仿真结果与神经生理实验现象相符.本文的工作表明,改进的氧化钨忆阻器模型更适合作为仿生突触应用到神经形态系统中,将为指导忆阻器的设计制造工艺以提高其仿生突触性能提供参考,也为研究温度对突触传递的影响提供了一种新思路.     

Filament formation in lithium niobate memristors supports neuromorphic programming capability

Memristor crossbars are capable of implementing learning algorithms in a much more energy and area efficient manner compared to traditional systems. However, the programmable nature of memristor crossbars must first be explored on a smaller scale to see which memristor device structures are most suitable for applications in reconfigurable computing. In this paper, we demonstrate the programmability of memristor devices with filamentary switching based on LiNbO₃, a new resistive switching oxide. We show that a range of resistance values can be set within these memristor devices using a pulse train for programming. We also show that a neuromorphic crossbar containing eight memristors was capable of correctly implementing an OR function. This work demonstrates that lithium niobate memristors are strong candidates for use in neuromorphic computing.

     

Choosing Between Two Classification Learning Algorithms Based on Calibrated Balanced $$5\times 2$$ Cross-Validated F-Test

Ion-channel variability has critical effect on the spike initiation and propagation in nervous system. Noise can play a constructive role leading to increased reliability or regularity of neuronal firing and spike propagation in the nervous system. In this paper we show that memristors can be considered as an electronic analogous of the Hodgkin–Huxley ion channels not only in terms of threshold switching effect but also in terms of stochastic behavior. In other words, memristor can also implement stochastic version of Hodgkin–Huxley equation. Switching effect in memristive devices is thermodynamically driven, which is stochastic in nature. We show that if the intrinsic stochastic behavior of memristor is taken into account, memristor based neuristor can also implement stochastic version of Hodgkin–Huxley axon model in generation of action potential. Ion channel variability in neurons can be modeled by intrinsic stochastic behavior of memristor. We incorporate noise in the memristor model by adding white Gaussian noise to the deterministic part of dynamical state evolution function of the memristor. We study the reliability of spike timing for spike train generated by memristor based neuristor in which the noise included memristor model is used. Also, the reliability of spike propagation along thin axons is discussed. A series connection of neuristors can be used as an axon in which neuristor acts as a node of Ranvier on an axon. Probabilistic nature of spike propagation on thin axons can be modeled using neuristor in which the variability nature of memristor is included.     

交错并联技术在无损电阻中的应用

无损电阻由于开关元件的存在而产生很大的电流脉冲,其等效电阻也是时变的,这严重限制了无损电阻的应用.为了降低由于开关元件的存在而造成的脉冲电流,改善无损电阻的特性,以工作在不连续导通模态下Buck-Boost变换器为具体研究对象,分析了无损电阻的建模原理,并给出了带低通滤波器的Buck-Boost变换器的无损电阻模型,将新近几年在电力电子领域比较活跃的交错并联技术引入到无损电阻,用以改善无损电阻的特性.仿真实验验证了方案的可行性,说明了交错并联技术对无损电阻的集成化和实用化有很大的促进作用.     

Reduction 93.7% time and power consumption using a memristor-based imprecise gradient update algorithm

The conventional computing system with the architecture of von Neumann has greatly benefited our humans for past decades, while it is also suffered from low efficiency due to the separation between a memory block and a processing unit. Memristor, which is an emerging electron device with the capability of data storage and processing information simultaneously, can be employed to construct a bioinspired neuromorphic computing system. Simulation as one of the most powerful methods to obtain the optimizing result for the memristor-based neuromorphic network has been extensively focused to realize the high precision calculation. It becomes very difficult because the pulse-to-pulse (P2P) model is limited by the updating process. The memristor-based multi-layer Perceptron (MLP) network online training generally presents a low accuracy. Therefore, an efficiency training schedual is urgently desired to improve the accuracy. Based on the resistive switching behavior observed in the Ag/TiOx/F-doped SnO₂ memristor, the weight update by the P2P model enables the MLP network online training in the low accuracy memristor with high performance. The low bits MLP optimized by a novel weight update schedual can realize high precision identification and classification. By that, the time and power consumption of memristor can be largely reduced. The experiment result illustrates that the high accuracy of 90.82% and 95.44% can be obtained at the first and final epoch of the MNIST handwritten digital datasets, respectively. Importantly, the number of the weight update, and the online training time and power consumption can be reduced by 81% and 93.7%, respectively. The scheme provides high precision, low power consumption, and fast convergence solution for the in-situ training of the imprecise memristor-based neuromorphic network.

     

忆阻及其应用研究综述

忆阻由蔡少棠教授从对称性角度预言提出,自惠普实验室2008年制作出第一款忆阻开始, 其已成为自动化等相关领域最热门研究方向之一. 本文回顾了忆阻的起源,探讨了忆阻的分类及其制造技术,分析了忆阻的多个数学模型和仿真模型以及仿真模型的实现方法, 总结了忆阻在人工神经网络、保密通信、存储器、模拟电路、人工智能计算机、生物行为模拟等方面的研究现状, 并对其应用前景进行展望.     

Analog memristive memory with applications in audio signal processing

Since the development of the HP memristor, much attention has been paid to studies of memris- tive devices and applications, particularly memristor-based nonvolatile semiconductor memory. Owing to its unique properties, theoretically, one could restart a memristor-based computer immediately without the need for reloading the data. Further, current memories are mainly binary and can store only ones and zeros, whereas memristors have multilevel states, which means a single memristor unit can replace many binary transistors and realize higher-density memory. It is believed that memristors can also implement analog storage besides binary and multilevel information memory. In this paper, an implementation scheme for analog memristive memory is considered. A charge-controlled memristor model is derived and the corresponding SPICE model is constructed. Special write and read operations are demonstrated through numerical analysis and circuit simulations. In addition, an audio analog record/play system using a memristor crossbar array is designed. This system can provide great storage capacity （long recording time） and high audio quality with a simple small circuit structure. A series of computer simulations and analyses verify the effectiveness of the proposed scheme.     

基于FPGA模拟的阻变神经网络加速器评估方法

基于阻变器件的存算一体神经网络加速器需在架构设计初期进行仿真评估,确保神经网络精度符合设计要求,但传统阻变神经网络加速器的软件模拟器运行速度较慢,难以应对大规模网络的架构评估需求。为加快仿真评估速度,设计一种基于现场可编程门阵列（FPGA）模拟的阻变神经网络加速器评估方法,分析现有阻变神经网络加速器的架构通用性,利用FPGA资源的高度并行性和运行时指令驱动的灵活模拟方式,通过硬件资源的分时复用实现多层次存算一体架构和指令集的功能模拟及主流神经网络的快速性能评估。实验结果表明,针对不同规模的忆阻器阵列和深度神经网络,该评估方法相比MNSIM和DNN NeuroSim软件模拟器运行速度分别提升了40.0~252.9倍和194.7~234.2倍。