GaAs DCFL超高速集成电路研究

直接耦合场效应逻辑（ＤＣＦＬ）具有简单的结构、良好的速度／功耗性能，是ＧａＡｓＦＥＴＬＳＩ电路中一种重要的逻辑形式。传统Ｅ／Ｄ型ＤＣＦＬ电路具有较低的成品率和较差的温度特性，本文研究了改进的Ｅ／Ｅ型ＤＣＦＬ电路。对Ｅ／Ｄ、Ｅ／Ｅ型ＤＣＦＬ电路的直流、瞬态及温度特性进行了分析、模拟和比较，Ｅ／Ｅ逻辑具有良好的高温性能。经优化设计，最后制作出单门延迟约１００ｐｓ、单门功耗约１ｍＷ的Ｅ／Ｄ和Ｅ／Ｅ型ＤＣＦＬ电路，且Ｅ／Ｅ型电路较Ｅ／Ｄ型电路具有更高的成品率。     

10 K-gate GaAs JFET sea of gates

The first GaAs 10 K-gate sea of gates has been successfully fabricated using junction FETs (JFETs) with a gate length of 0.5 μm. A basic cell is designed to comprise both a direct coupled FET logic (DCFL) four-NOR circuit and a source coupled FET logic (SCFL) inverter circuit with an identical enhancement-type JFET. Each input and output level is designed to be compatible with Si emitter-coupled-logic (ECL), CMOS, and transistor-transistor-logic (TTL) levels. Unloaded and loaded DCFL gate delays are 21 and 180 ps/gate with power consumption of 0.4 and 0.5 mW/gate, respectively. The toggle frequency of the T-type flip-flop is 3.9 and 4.4 GHz for DCFL and SCFL, respectively     

8 Gb/s 8:1 multiplexer and 1:8 demultiplexer IC's using GaAs DCFLcircuit

High-speed 8:1 multiplexer and 1:8 demultiplexer ICs composed of GaAs direct-coupled FET logic (DCFL) have been designed and fabricated. The ICs were designed with a tree-type architecture and using memory-cell-type flip-flops (MCFFs). Self-aligned GaAs MESFETs with a gate length of 0.5 μm were used in these ICs. The propagation delay time of the DCFL inverter was 19.0 ps/gate. Both ICs operated up to 8 Gb/s with power dissipations of 1.5 W for the multiplexer and 1.9 W for the demultiplexer at a single power supply voltage of 2.0 V. These ICs are applicable for multigigabit lightwave communication systems     

A 6.5-ns GaAs 20×20-b parallel multiplier with 67-ps gatedelay

The performance and yield of LSI circuits have been characterized over a wide variation in processing parameters and power supply voltage, and over the military temperature range using 4×4-, 8×8-, 12×12-, 16×16-, and 20×20-b multipliers. These parallel array multipliers with carry-save adder architecture have been implemented in low-power GaAs enhancement/depletion (E/D) direct-coupled FET logic (DCFL). The circuits were fabricated with a multifunction self-aligned gate process, which features a buried p-layer for high yield and manufacturability. Worst-case multiplication times ranging from 870 ps (51 ps/gate) for the 4×4-b, to 6.48 ns (67 ps/ gate) for the 20×20-b multiplier were obtained, with the fastest extracted gate delays yet reported for LSI circuits. The 20×20-b multiplier, with 18573 active devices (4902 logic gates), shows a wafer-probe yield as high as 61% on the best-yielding wafers. It is concluded that the E/D DCFL family is capable of providing LSI circuits operating over a wide variation in power-supply voltage and over the full military temperature range     

Submicrometer insulated-gate inverted-structure HEMT for high-speed large-logic-swing DCFL gate

Application of insulated-gate inverted-structure HEMT (I²-HEMT) to the enhancement/depletion (E/D) type direct-coupled FET logic circuits has been investigated. Superior electric characteristics were attained in a submicrometer-gate FET and ring oscillator. The threshold voltage shift with a reduction of gate length from 1.2 to 0.7 µm was as small as -0.05 V at 300 K. Drain conductances were very small and were 2.0 and 3.6 mS/mm at 300 and 77K, respectively. Gate leakage current was small enough even at a gate voltage of + 1.4 V both at 300 and 77 K, and a logic swing of larger than 1.2 V was achieved using a DCFL inverter. A 21-stage E/D-type DCFL ring oscillator with an 0.8-µm gate length showed a minimum gate delay of as small as 18.0 ps at a low power dissipation of 520 µW/gate at 77 K. High-speed and large logic-swing characteristics of the I²-HEMT DCFL circuits are accomplished by forming an undoped AlGaAs layer as a gate insulator on the inverted-structure HEMT structure.     

GaAs trickle transistor dynamic logic

A GaAs dynamic logic gate is proposed which uses a trickle transistor to compensate for leakage from the precharged node. This trickle transistor dynamic logic (TTDL) circuit is configured as a domino logic gate and a differential cascode voltage switch logic (CVSL) gate. Delay chains were implemented in a 1-μm GaAs enhancement/depletion (E/D) process where the depletion-mode FETs (DFETs) and the enhancement-mode FETs (EFETs) have threshold voltages of -0.6 and 0.15 V, respectively, in order to obtain an experimental characterization of these gates. In addition, the TTDL gates were used to implement a 4-b carry-lookahead adder. The adder has a critical delay of 0.8 ns and a power dissipation of 130 mW     

New insulated-gate inverted structure AlGaAs/GaAs/n-AlGaAs HEMT ring oscillator

Inverted-structure high electron mobility transistors with insulated-gate structure, i.e. AlGaAs/GaAs/n-AlGaAs, have been successfully applied to E/D-type DCFL ring oscillators. High transconductance of 280 mS/mm was obtained at 77 K in an enhancement-mode FET with 0.8 ?m gate length. Gate leakage current was small enough even at a gate voltage of +1.4 V both at 300 K and 77 K, and a high logic swing of more than 1 V was achieved using a DCFL inverter. A 21-stage ring oscillator showed a minimum gate delay as small as 18.0 ps with power dissipation of 520 ?W/gate at 77 K.     

GaAs two-phase dynamic FET logic: a low-power logic family for VLSI

An extremely low-power, high-density GaAs logic family is described. Two-phase dynamic FET logic (TDFL) provides all the standard logic functions (NOT, NAND, NOR), and it operates from two nonoverlapping clocks and a single supply. TDFL gates are shown to operate above 750 MHz with an extremely low power dissipation of only 44 nW/MHz gate. TDFL is self-latching, lending itself to highly efficient pipelined architectures, and it is implemented with a standard enhancement/depletion (E/D)-mode MESFET foundry process. Finally, TDFL is directly compatible with static direct-coupled FET logic (DCFL), making its introduction into high-speed systems very straightforward     

Advantages of metallic-amorphous-Silicon-gate FET's in GaAs LSI applications

A Schottky barrier as high as 1 V is obtained for contact between a ternary amorphous film, a-Si-Ge-B, and an n-type GaAs crystal. A metallic-amorphous-silicon-gate FET (MASFET) was made using the amorphous film as a gate contact. GaAs MASFET characteristics are superior to GaAs MESFET characteristics in application to LSI's with a DCFL configuration because the DCFL circuits with the GaAs MASFET's provide a logic level as high as 0.94 V and widen the circuit operation margin. Full operation is obtained from a 1 Kword × 2 bit SRAM with GaAs MASFET's, which is considered to be mainly due to the wide operation margin. The measured propagation delay time of the DCFL inverter is 34 ps at supply voltageV_{DD} = 1.5V and power consumption of 1.9 mW/gate.     

GaAs split phase dynamic logic

A novel GaAs dynamic logic gate: split phase dynamic logic (SPDL) is presented in this paper. The logic gate, derived from CMOS domino circuits, uses a split phase inverter to increase output voltage swing and a self-biased transistor to compensate for leakage loss. Compared with current GaAs dynamic logic designs, it offers several distinct advantages including small propagation delay, large output swing, low power dissipation and high process tolerance. The logic gate can be made directly compatible with direct-coupled FET logic (DCFL) and buffered FET logic (BFL) allowing flexible design for a variety of high speed digital applications. Four-bit carry lookahead adders using SPDL were fabricated in a 1 μm non-self aligned GaAs MESFET technology and the critical delays were found to be of the order of 500 ps     

Fast feedthrough logic: a high performance logic family for GaAs

A GaAs dynamic logic family using the feedthrough evaluation concept is presented in this paper. Feedthrough logic (FTL) allows the outputs to be partially generated before the input signals arrive. A modified version of this logic, where the function and its complement are implemented in a differential structure, is also introduced. In an FTL gate, the logic outputs are reset to low during the high phase of the clock and evaluated during the low phase of the clock. Resetting to low alleviates the problems of charge sharing and leakage current associated with the other GaAs dynamic logic families. FTL logic functions can be cascaded in a domino-like fashion without a need for the intervening inverters. We employ this novel concept to design several arithmetic circuits. We compare a 4-bit ripple carry adder in FTL with the other published works in terms of device count, area, delay, clock rate and power consumption. The results demonstrate that FTL is the simplest, the fastest, and consumes least power. In addition, our FTL design compares very well with the standard CMOS technology. FTL gates are fully compatible with direct coupled field-effect transistor logic (DCFL), and therefore, can be included in a DCFL standard cell library for improving cell-based ASIC performance. To match the high-speed of the FTL combinational blocks, we present a single-ended latch for pipelining the FTL blocks. Comparisons with the other published results demonstrate the superior performance of our dynamic latch.     

GaAs IC“与或非”逻辑DCFL单元模拟器及优化设计

报道了高速GaAsIC“与或非”逻辑直接耦合逻辑（DCFL）单元电路特性模拟器及应用贪心算法进行电路工艺及几何尺寸优化设计。模拟器及优化设计方法对于研制大规模GaAsIC具有意义。     

PCFL3: a low-power, high-speed, single-ended logic family

This paper presents a new low-power, high-speed, single-ended logic family called PCFL3. Its operation is based on a bootstrapping technique, used in NMOS. It is fully compatible with direct coupled field-effect transistor logic (DCFL) and two-phase dynamic FET logic (TDFL). PCFL3 is implemented with a standard enhancement/depletion-mode MESFET process and provides all the standard logic functions (NOT, NOR, NAND). Using enhancement-mode FETs only, PCFL3 benefits from good process variation immunity and good noise margins. Measurement results on a ring oscillator are reported. The current consumption of an inverter is reduced by about 53% compared to the DCFL, and the speed is increased by about 50%     

Folded gate—A novel logic gate structure

We propose a new logic gate structure which consists of two semiconducting layers separated by an insulator. The input electrode is a rectifying contact to the top conducting layer which acts as a channel of a switching field-effect transistor. The bottom conductive layer serves as a load. The conducting layers are connected and capacitively coupled. The top layer acts as a gate for the load element whereas the bottom layer acts as a second gate for the top conductive channel. This "folded" gate is a majority-carrier device which may be implemented using different technologies and materials. It allows a CMOS-like operation with a very low power consumption in the stable states, speed comparable or higher then the speed of conventional direct-coupled field-effect transistor logic (DCFL), and a larger voltage swing.     

A 40-ps high electron mobility transistor 4.1 K gate array

A high-electron mobility transistor (HEMT) 4.1 K-gate array has been developed, using a selective dry etching process and a MBE (molecular-beam epitaxy) growth technology. The circuit design uses direct-coupled FET logic (DCFL). The chip contains 4096 NOR gates, each with a 0.8-μm gate length, and measures 6.3 mm×4.8 mm. A basic gate delay of 40 ps has been achieved. A 16×16-bit parallel multiplier, used to test this array, has a multiplication time of 4.1 ns at 300 K, where the power dissipation is 6.2 W     

High frequency divider circuits using ion-implanted GaAs MESFET's

A single clock master-slave frequency divider circuit was designed and fabricated using GaAs MESFET's in the direct-coupled FET logic (DCFL) circuit architecture. At room temperature, the maximum operating frequency was 6.2 GHz at a power consumption of 3.5 mW/gate. The complete divider circuit and buffer amplifier was realized in a 65 × 165 µm²area. The MESFET's were fabricated using Si ion implantion directly into GaAs wafers and used a self-aligned recessed gate. The nominal gatelength was 0.6 µm. Corresponding fabricated ring oscillator circuits showed minimum gate delays of 18.5 ps at 3.1 mW/gate for fan-out of one at 300 K and 15.2 ps at 3.5 mW/gate at 77 K.     

Gallium arsenide finds a new niche

The use of a very-large-scale integrated GaAs circuits for applications where high speed at room temperatures is needed, such as in computers or telecommunications, is examined. The advantages and disadvantages of a logic family called direct-coupled FET logic (DCFL) which couples the speed of GaAs with a significantly lower power dissipation than any other alternative are discussed. Material, fabrication, and packaging concerns associated with DCFL are considered. Some GaAs devices being produced in volume, at rates of several hundred a month, are described. The potential impact of these devices on the computer and telecommunications markets is addressed     

Modeling frequency dependence of GaAs MESFET characteristics

We present a new method of modeling the output conductance dispersion of GaAs MESFET's. High frequency model parameters are extracted and then used to model high frequency output conductance over a wide range of bias conditions. The model is then used to simulate and analyze the effect of output conductance dispersion on the performance of DCFL and SCFL logic gates. Whereas the DCFL performance is not significantly affected by the high frequency effects, the noise margin of SCFL decreases by almost a factor of 30% above 100 kHz, with an associated decrease in the voltage swing and gate delay     

Power model for DCFL family

A model to estimate power consumption in GaAs direct coupled FET logic (DCFL) family, which is based on sensitivity computations, is reported. Comparisons against SPICE simulations show errors smaller than 5% in power consumption estimation, while CPU time is reduced by more than two orders of magnitude     

High-speed DCFL circuits with very shallow junction GaAs JFETs

High-speed DCFL (direct-coupled FET logic) circuits implemented with advanced GaAs enhancement-mode J-FETs are discussed. A divide-by-four static frequency divider operates at up to 6 GHz with a power consumption of 20 mW/flip-flop. A high channel concentration of more than 1×10¹⁸ cm^-3 together with a very shallow junction depth of less than 30 nm for the p⁺-gate results in a transconductance as high as 340 mS/mm at a gate length of 0.8 μm. Open-tube diffusion of Zn using diethylzinc and arsine makes it possible to control a very shallow p⁺-layer less than 10 nm thick. The propagation delay time, as measured with a ring oscillator, was 22 ps/gate with a power consumption of 0.42 mW/gate