高K栅堆叠结构MOSFET器件阈值电压不稳定度的半经验解析模型

A semi-empirical analytic model for the threshold voltage instability of MOSFET is derived from the Shockley-Read-Hall (SRH) statistics in this paper to account for the transient charging effects in a MOSFET high-k gate stack. Starting from the single energy level and single trap assumption, an analytical expression of the filled trap density in terms of the dynamic time is derived from the SRH statistics. The semi-empirical analytic model of the threshold voltage instability is developed based on the MOSFET device physics between the threshold voltage and the induced trap density. The obtained model is also verified by the extensive experimental data of the trapping and de-trapping stress from the different high k gate configuration.     

A semi-empirical analytic model for threshold voltage instability in MOSFETs with high-k gate stacks

n the threshold voltage and the induced trap density. The obtained model is also verified by extensive experimental data of trapping and de-trapping stress from different high-k gate configurations.     

Schottky-barrier S/D MOSFETs with high-k gate dielectrics and metal-gate electrode

This letter presents a low-temperature process to fabricate Schottky-barrier silicide source/drain transistors (SSDTs) with high-/spl kappa/ gate dielectric and metal gate. For p-channel SSDTs (P-SSDT) using PtSi sourece/drain (S/D) , excellent electrical performance of I/sub on//I/sub off//spl sim/10/sup 7/-10/sup 8/ and subthreshold slope of 66 mV/dec have been achieved. For n-channel SSDTs (N-SSDTs) using DySi/sub 2-x/ S/D , I/sub on//I/sub off/ can reach /spl sim/10/sup 5/ at V/sub ds/ of 0.2 V with two subthreshold slopes of 80 and 340 mV/dec. The low-temperature process relaxes the thermal budget of high-/spl kappa/ dielectric and metal-gate materials to be used in the future generation CMOS technology.     

Threshold voltage model for deep-submicrometer MOSFETs

The threshold voltage, V_th, of lightly doped drain (LDD) and non-LDD MOSFETs with effective channel lengths down to the deep-submicrometer range has been investigated. Experimental data show that in the very-short-channel-length range, the previously reported exponential dependence on channel length and the linear dependence on drain voltage no longer hold true. A simple quasi-two-dimensional model is used, taking into account the effects of gate oxide thickness, source/drain junction depth, and channel doping, to describe the accelerated V_th on channel length due to their lower drain-substrate junction built-in potentials. LDD devices also show less V_th dependence on drain voltage because the LDD region reduces the effective drain voltage. Based on consideration of the short-channel effects, the minimum acceptable length is determined     

A finite weakest-link model of lifetime distribution of high-k gate dielectrics under unipolar AC voltage stress

This paper presents a new probability distribution function for the breakdown lifetime of high-k gate dielectrics under unipolar AC voltage stress. This function is derived from a finite weakest-link model, where the gate oxide layer is considered to consist of many potential breakdown cells. Each potential breakdown cell is modeled as a series coupling of several subcells, which is analogous to the fiber-bundle model for the strength statistics of structures. The present model indicates that the type of lifetime distribution varies with the gate area and the dependence of the mean lifetime on the gate area deviates from the classical Weibull scaling law. It is shown that the model agrees well with the observed lifetime histograms of HfO₂ based gate dielectrics under unipolar AC voltage stress.     

Threshold voltage model for deep-submicron fully depleted SOI MOSFETs with back gate substrate induced surface potential effects

A simple analytical threshold voltage model for short-channel fully depleted SOI MOSFETs has been derived. The model is based on the analytical solution of the two-dimensional potential distribution in the silicon film (front silicon), which is taken as the sum of the long-channel solution to the Poisson's equation and the short-channel solution to the Laplace equation, and the solution of the Poisson's equation in the silicon substrate (back silicon). The proposed model accounts for the effects of the back gate substrate induced surface potential at the buried oxide-substrate interface which contributed an additional 15–30% reduction in the threshold voltage for the devices used in this work. Conditions on the back gate supply voltage range are determined upon which the surface potential at the buried oxide-substrate interface is accumulated, depleted, or inverted. The short-channel associated drain induced barrier lowering effects are also included in the model. The model predications are in close agreement with PISCES simulation results. The equivalence between the present model and previously reported models is proven. The proposed model is suitable for use in circuit simulation tools such as Spice.     

Reliability issues in submicron MOSFETs with oxynitride gate dielectrics

A review of critical reliability issues in submicron MOSFETs with oxynitride gate dielectrics is presented. We have focussed our attention on: substrate and gate currents in short channel MOSFETs, hot carrier induced MOSFET degradation under DC and AC stress, gate-induced drain leakage current and its enhancement due to stress, neutral trap generation due to electrical stress and degradation of analog MOSFET parameters. We have also discussed the problems of radiation induced neutral trap generation and boron penetration through the gate dielectric, which arise due to the advanced processing techniques utilized in submicron MOSFET processing. It is concluded that the use of oxynitride gate dielectrics can effectively solve several reliability issues encountered in scaling down MOSFETs to submicron dimensions.     

Mobility measurement and degradation mechanisms of MOSFETs made with ultrathin high-k dielectrics

Accurate measurements and degradation mechanisms of the channel mobility for MOSFETs with HfO/sub 2/ as the gate dielectric have been systematically studied in this paper. The error in mobility extraction caused by a high density of interface traps for a MOSFET with high-k gate dielectric has been analyzed, and a new method to correct this error has been proposed. Other sources of error in mobility extraction, including channel resistance, gate leakage current, and contact resistance for a MOSFET with ultrathin high-k dielectric have also been investigated and reported in this paper. Based on the accurately measured channel mobility, we have analyzed the degradation mechanisms of channel mobility for a MOSFET with HfO/sub 2/ as the gate dielectric. The mobility degradation due to Coulomb scattering arising from interface trapped charges, and that due to remote soft optical phonon scattering are discussed.     

Off-state gate current in n-channel MOSFETs with nitrided oxidegate dielectrics

The authors report on the off-state gate current (I_g ) characteristics of n-channel MOSFETs using thin nitrided oxide (NO) gate dielectrics prepared by rapid thermal nitridation at 1150°C for 10-300 s. New phenomena observed in NO devices are a significant I_g at drain voltages as low as 4 V and an I_g injection efficiency reaching 0.8, as compared to 8.5 V and 10^-7 in SiO₂ devices with gate dielectrics of the same thickness. Based on the drain bias and temperature dependence, it is proposed that I_g in MOSFETs with heavily nitrided oxide gate dielectrics arises from hot-hole injection, and the enhancement of gate current injection is due to the lowering of valence-band barrier height for hole emission at the NO/Si interface. The enhanced gate current injection may cause accelerated device degradation in MOSFETs. However, it also presents potential for device applications such as EPROM erasure     

A PNPN tunnel field-effect transistor with high-k gate and Iow-k fringe dielectrics

A PNPN tunnel field effect transistor(TFET) with a high-k gate dielectric and a low-k fringe dielectric is introduced.The effects of the gate and fringe electric fields on the TFET’s performance were investigated through two-dimensional simulations.The results showed that a high gate dielectric constant is preferable for enhancing the gate control over the channel,while a low fringe dielectric constant is useful to increase the band-to-band tunneling probability.The TFET device with the proposed structure has good switching characteristics,enhanced on-state current,and high process tolerance.It is suitable for low-power applications and could become a potential substitute in next-generation complementary metal-oxide-semiconductor technology.     

非晶ErAlO高k栅介质薄膜的制备及性能研究

采用射频磁控溅射法在p型Si(100)衬底上成功制备了非晶Er2O3-Al2O3(ErAlO)栅介质复合氧化物薄膜。研究了ErAlO薄膜的结构及电学特性。XRD测量显示,ErAlO薄膜具有良好的热稳定性,样品经过900℃氧气氛退火30 min后仍保持非晶态结构。AFM照片显示,其表面粗糙度小于0.2 nm,平整度良好。ErAlO栅MOS结构在氧分压为1%时,薄膜的有效相对介电常数为9.5,外加偏压(Vg)为–1 V时样品的漏电流密度为7.5×10–3 A/cm2。非晶ErAlO薄膜是一种很有希望取代SiO2的新型高k栅介质候选材料。     

Threshold voltage of small-geometry Si MOSFETs

This paper uses an accurate, three-dimensional geometrical model for calculation of the threshold voltage of short-channel and narrow-width (small-geometry) silicon MOSFETs. The model expresses the threshold voltage as a function of channel length, channel width, source- and drain-junction depth, backgate bias, drain voltage, gate-oxide thickness and substrate doping concentration. The model also predicts the backgate and drain voltages for punch-through to occur for small-geometry MOSFETs.     

Short-channel MOSFETs with oxynitride gate dielectrics fabricated using multiple rapid thermal processing

Short-channel MOSFETs with superior thin gate dielectrics have been successfully fabricated using multiple reactive rapid thermal processing of thermal oxides. The gate dielectrics are produced by rapid thermal nitridation (RTN) of thin thermal oxides in pure NH/sub 3/ ambient followed by rapid thermal reoxidation (RTO) in O/sub 2/ ambient. Devices fabricated with RTO/RTN gate dielectrics exhibit improved hot electron induced degradation compared to those fabricated with pure oxides. In addition, the subthreshold leakage current level of RTO/RTN devices is as good as for standard oxide devices.<>     

Temperature dependent model for threshold voltage and subthreshold slope of strained-Si channel MOSFETs with a polysilicon gate

We present a temperature dependent model for the threshold voltage V_t and subthreshold slope S of strained-Si channel MOSFETs and validate it with reported experimental data for a wide range of temperature, channel doping concentration, oxide thickness and strain value. Such model includes the effect of lattice strain on material, temperature dependent effective mass of carriers, interface-trapped charge density and bandgap narrowing due to heavy channel doping. Also considered are polydepletion effects, carrier localization effect in the ultra-thin channel and quantum-mechanical effects. Our investigation reveals that the threshold voltage reduces linearly with increasing temperature whereas the subthreshold slope increases. In addition V_t is found to be sensitive to strain while S is weakly dependent on strain. Moreover, the channel doping concentration influences both V_t and S, and also the rate of change of V_t with temperature. Furthermore, S decreases for a lightly doped channel particularly at lower temperatures.     

Threshold voltage control in NiSi-gated MOSFETs through SIIS

Complete gate silicidation has recently been demonstrated as an excellent technique for the integration of metal gates into MOSFETs. From the various silicide gate materials NiSi has been shown to be the most scalable. In this paper, a versatile method for controlling the workfunction of an NiSi gate is presented. This method relies on doping the poly-Si with various impurities prior to silicidation. The effect of various impurities including B, P, As, Sb, In, and Al is described. The segregation of the impurities from the poly-Si to the silicide interface during the silicidation step is found to cause the NiSi workfunction shift. The effect of the segregated impurities on gate capacitance, mobility, local workfunction stability, and adhesion is studied.     

Carrier separation analysis for clarifying carrier conduction and degradation mechanisms in high-k stack gate dielectrics

The carrier conduction and the degradation mechanism in n⁺gate p-channel metal-insulator-semiconductor field-effect-transistors with HfAlO_X (Hf: 60 at.%, Al: 40 at.%)/SiO₂ dielectric layers have been investigated using carrier separation method. Since gate current depends on substrate bias and both electron and hole currents are independent of temperature over the range of 25–150 °C, the conduction mechanism for both currents is controlled by a tunneling process. As the interfacial SiO₂ layer (IL) thickness increases in a fixed high-k layer thickness (T_high-k), a dominant carrier in the leakage current changes from hole to electron around 2.2-nm-thick IL. This is due to an asymmetric barrier height for electrons and holes at the SiO₂/Si interface. On the contrary, in the case of a fixed IL thickness of 1.3 nm, the hole current is dominant in the leakage current, regardless of T_high-k. It is shown that the dominant carrier in the leakage current depends on the structure of the high-k stack. Both electron and hole currents for the stress-induced-leakage-current (SILC) state increase slightly relative to the initial currents, which means that the trap generation in the high-k stack occurs near both the conduction band edge of n⁺poly-Si gate and the valence band edge of Si substrate. The electron current at soft breakdown (SBD) state dramatically increases over that for the SILC state, while the hole currents for both the SILC state and SBD are almost the same. This indicates that the defect sites generated in the high-k stack after SBD are located at energies near the conduction band edge of n⁺poly-Si gate. Both the defect generation rate and the defect size in the HfAlO_X/SiO₂ stacks are large compared with those in SiO₂. It is inferred that, in high-k dielectric stack, the defect generation mainly occurs in the high-k side rather than the IL side, and the defect size larger than the case of SiO₂ could be related to a larger dielectric constant of the high-k layer.     

Threshold voltage adjustable process for self-aligned gate GaAs JFET

A self-aligned GaAs JFET process, allowing threshold voltage adjustment after gate metallisation, has been developed. Zn-doped tungsten silicide was used as the gate metallisation, which also acts as the source of Zn diffusion for the p-junction gate. The threshold voltage was adjusted by repeated short thermal pulses in a lamp annealer at 550°C. The process has the potential to solve the most difficult task of threshold voltage control necessary for achieving high yield in LSI fabrication.     

Effects of deuterium anneal on MOSFETs with HfO/sub 2/ gate dielectrics

The effects of high-temperature (600/spl deg/C) anneal in a dilute deuterium (N/sub 2/ : D/sub 2/= 96 : 4) atmosphere was first investigated and evaluated in comparison to high-temperature forming gas (N/sub 2/ : H/sub 2/= 96 : 4) anneal (600/spl deg/C) and nonanneal samples. The high-temperature deuterium anneal was as effective as the forming gas anneal in improving MOSCAP and MOSFET characteristics such as the C-V curve, drain current, subthreshold swing, and carrier mobility. These can be attributed to the improved interface quality by D/sub 2/ atoms. However, unlike the forming gas anneal, the deuterium anneal provided the hafnium oxide (HfO/sub 2/) gate dielectric MOSFET with better reliability characteristics such as threshold voltage (V/sub T/) stability under high voltage stress.     

Influences of structure around gate-edge on high electric field strength in MISFETs with high-k gate dielectrics

In this paper, dependences of electric field strength around gate-edge in gate dielectrics of MISFETs with high-k gate dielectrics on design parameters are studied. It is newly found that locations of sidewall/gate dielectric interfaces relative to gate electrode edges are critical to electric field strength of high-k MISFETs. Electric field can be as high as 4 MV/cm, which could have large influences on the yield of large scale integrated circuits (LSIs) with high-k gate dielectrics. An explanation of this phenomenon is given by considering discontinuity in electric field at interfaces between two materials with different dielectric constants. It is clarified that an electrical potential of side and top surfaces of gate dielectrics is strongly affected by the discontinuity of electric field strength at interfaces. As a result, electric field strength around gate electrode edges critically depends on locations of sidewall/gate dielectrics interfaces relative to gate electrode edges. Based on the physical considerations, a structure, in which gate sidewalls are also made of high-k materials, is studied from the viewpoint of electric field strength around gate electrode edges. It is shown that this structure effectively suppresses electric field strength around gate edges.