Effect of microwave radiation on the properties of Ta2O5–Si microstructures

The paper presents results of the effect of microwave irradiation at room temperature on the properties of thin layers of tantalum pentoxide deposited on Si by rf sputtering. Electrical characterization is performed in conjunction with Auger electron spectroscopy and atomic force microscopy. Among exposure times used (1; 5; 10 s), treatment of about 5 s shows the best promise as an annealing step––an improvement of number of parameters of the system Ta₂O₅–Si is established (dielectric constant and surface morphology; stoichiometry and microstructure of both the bulk oxide and the interfacial transition region; electrical characteristics in terms of oxide charge density, leakage current and breakdown fields). At the same time the microwave irradiation is not accompanied by crystalization effects in Ta₂O₅ and/or additional oxidation of Si substrate. It is concluded that the short-time microwave irradiation can be used as an annealing process for Ta₂O₅–Si microstructures and it has a potential to replace the high-temperature annealing processes for high-k insulators.     

Thermal Ta2O5––alternative to SiO2 for storage capacitor application

Tantalum pentoxide thin layers (10–100 nm) obtained by thermal oxidation of rf sputtered Ta films on Si have been investigated with respect of their dielectric, structural and electric properties. It is established that stoichiometric Ta₂O₅ detected at the surface of the layers is reduced to tantalum suboxides in their depth. The oxide parameters are discussed in terms of a presence of an unavoidable ultrathin SiO₂ between Si and Ta₂O₅ and bond defects in both the oxide and the interface transition region. Conditions which guarantee obtaining high quality tantalum oxide with a dielectric constant of 32–35 and a leakage current less than 10⁻⁷–10⁻⁸ A/cm² at 1.5 V (SiO₂ equivalent thickness of 2.5–3 nm) are established. These specifications make the layers obtained suitable alternative to SiO₂ for high density DRAMs application.     

Improvement of gate dielectric reliability for p+poly MOS devices using remote PECVD top nitride deposition on ultra-thin (2.4–6 nm) gate oxides

Dual layer dielectrics have been formed by remote PECVD deposition of ultra-thin (0.4–1.2 nm) nitrides onto thin thermal oxides grown on n-type Si(100) substrates. Activation of boron-implanted p+ polycrystalline silicon gate electrodes was accomplished by a high temperature anneal, 1–4 min at 1000°C. Boron penetration through the dielectric film to the n-type substrate was investigated by performing a quasi-static C–V analysis and monitoring the flatband voltage shift. Boron penetration was effectively stopped by a 0.8 nm nitride film, and partially stopped by a 0.4 nm nitride film. In addition, the charge to breakdown as monitored by the Q_bd value to 50% cumulative failure was highest for the device with the 0.8 nm top nitride, and decreased significantly in the thermal oxide. However there were essentially no differences in the mid-gap interface state densities, D_it, between oxide and nitride/oxide gate dielectric structures with Al gate. It is concluded that the 0.8 nm of plasma nitride was sufficient to block boron atom out-diffusion from a heavily implanted p+ poly-silicon gate electrode under the conditions of an aggressive implant activation anneal to improve the dielectric reliability.     

Sol–gel MgO thin films for insulation on SiC

Silicon carbide (SiC) is a wide bandgap semiconductor suitable for high-voltage, high-power, and high-temperature devices from DC to microwave frequencies. However, the marketing of advanced SiC power devices remains limited due to performance limitation of the SiO₂ dielectric among other issues. Indeed, SiO₂ has a dielectric constant 2.5 times lower than SiC, which means that at critical field for breakdown in SiC, the electric field in the adjoining SiO₂ becomes too high for reliable operation. This suppresses the main advantage of using SiC power devices if the ten times higher breakdown field for SiC in comparison to Si cannot be exploited. Therefore, alternative dielectrics having a dielectric constant higher or in the same order as SiC (ε_r≈10) should be used to reduce the electrical field in the insulator. Among alternative dielectrics to silicon dioxide (SiO₂), magnesium oxide (MgO) seems to be a good candidate regarding its bulk properties: large bandgap, high thermal conductivity and stability, and a suitable dielectric constant (ε_r≈10). In order to evaluate such a promising candidate, the sol–gel process appears to be a convenient route to elaborate this kind of coatings. By selecting an appropriate precursor solution and optimizing the curing conditions of the films, MgO films could be obtained under various crystallization states: non-oriented or preferred [1 1 1] orientation. MIM structures have been used to investigate the insulating properties of the sol–gel MgO films. The dielectric strength of the films was found to be microstructure–dependent, and reached 3 to 8 MV/cm at room temperature. Leakage currents were measured from 150 up to 250 °C, with values less than 10⁻⁵ A/cm² at 1 MV/cm.     

Atomic-layer-deposited silicon-nitride/SiO2 stack––a highly potential gate dielectrics for advanced CMOS technology

An extremely thin (2 monolayers) silicon nitride layer has been deposited on thermally grown SiO₂ by an atomic-layer-deposition (ALD) technique and used as gate dielectrics in metal–oxide–semiconductor (MOS) devices. The stack dielectrics having equivalent oxide thickness (T_eq=2.2 nm) efficiently reduce the boron diffusion from p⁺ poly-Si gate without the pile up of nitrogen atoms at the SiO₂/Si interface. The ALD silicon nitride is thermally stable and has very flat surface on SiO₂ especially in the thin (<0.5 nm) thickness region.An improvement has been obtained in the reliability of the ALD silicon-nitride/SiO₂ stack gate dielectrics compared with those of conventional SiO₂ dielectrics of identical thickness. An interesting feature of soft breakdown free phenomena has been observed only in the proposed stack gate dielectrics. Possible breakdown mechanisms are discussed and a model has been proposed based on the concept of localized physical damages which induce the formation of conductive filaments near both the poly-Si/SiO₂ and SiO₂/Si-substrate interfaces for the SiO₂ gate dielectrics and only near the SiO₂/Si-substrate interface for the stack gate dielectrics.Employing annealing in NH₃ at a moderate temperature of 550 °C after the ALD of silicon nitride on SiO₂, further reliability improvement has been achieved, which exhibits low bulk trap density and low trap generation rate in comparison with the stack dielectrics without NH₃ annealing.Because of the excellent thickness controllability and good electronic properties, the ALD silicon nitride on a thin gate oxide will fulfill the severe requirements for the ultrathin stack gate dielectrics for sub-0.1 μm complementary MOS (CMOS) transistors.     

Study of dc conduction mechanisms in dysprosium–manganese oxide insulator thin films grown on Si substrates

Samples of amorphous and crystalline (Dy–Mn) oxide thin films have been prepared on Si(p) substrates. The crystal structure of the oxide film annealed under different conditions was investigated by the X-ray diffraction method (XRD). The percentage weight composition of the compound-oxide films was determined by the X-ray fluorescence (XRF) spectroscopy method. It was observed that Dy oxide and Mn oxide prevent each other to crystallize alone or making a solid solution even at 600 °C, but a compound of DyMnO₃ was formed through the solid-state reaction at T > 800 °C. Samples in form of Al/oxide/Si MOS structures were characterised by measuring their capacitance as a function of gate voltage C(V_g) in order to determine the fixed and interface charge densities as well as the oxide voltage in terms of gate voltage. The total surface charge density was in the device-grade of 10¹⁰–10¹¹ cm⁻². The dc measurements at room temperature show that the main mechanism controlling the current flow is the Richardson–Schottky (RS) mechanism. The parameters of the RS model like the field lowering coefficients and the dynamic relative permittivity were determined. The leakage current density of the samples was studied as a function of temperature in a range of (293–380 K). It was observed that the temperature dependence of crystalline (Dy–Mn) oxide films has a property that higher temperature reduces the current, which may be important in the application in circuits that operate under extreme conditions. Thermal activation energies of electrical conduction were determined.     

dc-Conduction mechanism in lanthanum–manganese oxide films grown on p-Si substrate

Thin films of (La–Mn) double oxide were prepared on p-Si substrates for electrical investigations. The samples have been characterised by X-ray fluorescence (XRF) and X-ray diffraction (XRD) methods. The XRF spectrum was used to determine the weight fraction ratio of Mn to La in the prepared samples. The XRD study shows the formation of grains of LaMnO₃ compound through a solid-state reaction for annealing at 800 °C. Samples used to study the electrical characteristics of the prepared films were constructed in form of a metal–oxide–Si MOS structures. Those MOS structures were characterised by the measuring their capacitance as a function of gate voltage C(V_g) in order to determine the oxide charge density Q_ox, the surface density of states D_it at the oxide/Si interface, and to extract the oxide voltage in terms of gate voltage. The extracted dielectric constant of the double oxide film is lower than that of pure La₂O₃ film and larger than that of pure Mn₂O₃ film, but the formation of LaMnO₃ grains by a solid-state reaction at 800 °C increases the relative permittivity to 11.5. These experimental conclusions might be useful to be used in the field of Si-oxide alternative technique. The leakage dc current density vs. oxide field J(E_ox) relationship for crystalline films follow the mechanism of Richardson–Schottky (RS), from which the field-lowering coefficient and the dynamic relative permittivity were determined. Nevertheless, the leakage current density measured in a temperature range of (293–363 K) was not controlled by the RS mechanism. It was observed that the temperature dependence of the leakage current in crystalline (La–Mn) oxide insulating films has metallic-like temperature behaviour, which might be important in the technical applications.     

A new empirical extrapolation method for time-dependent dielectric breakdown reliability projections of thin SiO2 and nitride–oxide dielectrics

The results of an investigation of time-dependent dielectric breakdown (TDDB) of thin gate oxide and nitride–oxide (N–O) films are presented for a wide range of fields and temperatures. It was found that TDDB of both gate oxide and N–O films followed a power-law dependence of mean value of average leakage current (I_avg). An empirical extrapolation model using average leakage current as a major parameter was proposed based on experimental results. This proposed lifetime model has been successful to predict dielectric reliability. It could continuously fit the entire breakdown data from both wafer level and module level stress. The extrapolation from wafer level data to module data was excellent. The power of current versus TDDB showed exponential dependence on oxide thickness. This proposed TDDB projection methodology also worked for N–O films with an abrupt current increase in the I–V curve at a certain voltage well below the breakdown voltage, while the conventional models clearly failed to fit all data from this region. The observation of TDDB dependence of the current may open a new window for oxide lifetime projections and provide some insights into the nature of oxide breakdown and its implications for reliability studies.     

Electrical characterisation of Si3N4/SiO2 double layers on p-type 6H–SiC

MNOS, MNS and MOS devices have been fabricated on p-type 6H–SiC substrates without epitaxial layers. They have been characterised using high frequency CV, GV, and IV measurements. The high frequency CV characteristics of p-type 6H–SiC MNOS structures indicate a very similar interface quality to p-type 6H–SiC MOS devices. A lower effective fixed insulator charge Q_I is found in MNOS devices with a higher oxide thickness x_ox. An x_ox of 10 nm is effective in avoiding charge instability. The effective fixed insulator charge Q_I can be modified in the 10 nm oxide SiC MNOS devices by injecting carriers into the nitride. Similar leakage current characteristics compared to p-type 6H–SiC MNS structures have been found for p-type 6H–SiC MNOS devices, but the SiO₂/Si₃N₄ insulator current is lower, particularly for positive electric fields. At the oxide breakdown limit (−10 MV/cm), Poole–Frenkel conduction is observed in the nitride for negative electric fields due to direct tunnelling of holes into the nitride.     

An investigation of surface state capture cross-sections for metal–oxide–semiconductor field-effect transistors using HfO2 gate dielectrics

MOSFETs and MOSCs incorporating HfO₂ gate dielectrics were fabricated. The I_DS–V_DS, I_DS–V_GS, gated-diode and C–V characteristics were investigated. The subthreshold swing and the interface trap density were obtained. The surface recombination velocity and the minority carrier lifetime in the field-induced depletion region measured from the gated diodes were about 2.73 × 10³ cm/s and 1.63 × 10⁻⁶ s, respectively. The effective capture cross section of surface state was determined to be 1.6 × 10⁻¹⁵ cm² using the gated-diode technique in comparison with the subthreshold swing measurement. A comparison with conventional MOSFETs using SiO₂ gate oxide was also made.     

Effects of the electrical stress on the conduction characteristics of metal gate/MgO/InP stacks

The degradation dynamics and post-breakdown current–voltage (I–V) characteristics of magnesium oxide (MgO) layers grown on n and p-type indium phosphide (InP) substrates subjected to electrical stress were investigated. We show that the current–time (I–t) characteristics during degradation can be described by a power-law model I(t) = I₀t^−α, where I₀ and α are constants. It is reported that the leakage current associated with the soft breakdown (SBD) failure mode follows the typical voltage dependence I = aV^b, where a and b are constants, for both injection polarities but in a wider voltage range compared with the SiO₂/Si system. It is also shown that the hard breakdown (HBD) current is remarkably high, involving large ON–OFF fluctuations that resemble the phenomenon of resistive switching previously observed in a wide variety of metal oxides.     

Time-dependent dielectric breakdown of SiO2 films in a wide electric field range

We have performed time dependent dielectric breakdown measurement of SiO₂ films in the electric field (E_OX) range 7–13.5 MV/cm and evaluated the electric field dependence of intrinsic lifetime, using both area and temperature dependences of oxide lifetime. We have evaluated the electric field dependence of time to breakdown (t_BD) below 125°C, because the activation energy of intrinsic lifetime changes at 125°C t_BD of 7.1 and 9.6 nm oxides is not proportional to exp(E_OX) but proportional to exp(1/E_OX). This suggests that the breakdown mechanism of 9.6 and 7.1 nm oxides is the same and adheres to the anode hole injection model. However, the breakdown mechanism of 4.0 nm oxides is not the same as that of 7.1 and 9.6 nm oxides. The slope of log(t_BD) versus 1/E_OX plot in 4.0 nm oxide increases with decreasing oxide fields. The intrinsic lifetime in the positive gate bias decreases with increasing oxide thicknesses in the range of electric fields employed in the present experiment.     

Extracting the relative dielectric constant for “high-κ layers” from CV measurements – Errors and error propagation

The paper pursues an investigation of the errors associated with the extraction of the dielectric constant (i.e., κ value) from capacitance–voltage measurements on metal oxide semiconductor capacitors. The existence of a transition layer between the high-κ dielectric and the silicon substrate is a factor that affects – in general – the assessment of the electrical data, as well as the extraction of κ. A methodology which accounts for this transition layer and the errors related to other parameters involved in the κ value extraction is presented; moreover, we apply this methodology to experimental CV results on HfO₂/SiO_x/Si structures produced in different conditions.     

Stress induced gate–drain leakage current in ultra-thin gate oxide

Ultra-thin gate oxide reliability, in large area MOSFETs, can be monitored by measuring the gate current when the substrate is depleted. When the channel length is scaled down, the tunneling current associated with the source/drain extension region (SDE) to the gate–overlap regions can dominate the gate current. In N-MOSFETs, as a function of the negative gate voltage two components of the gate–drain leakage current should be considered, the first for V_FB < V_G < 0 V and the second for V_G < V_FB. These components are studied in this work before and after voltage stresses. The aim of this work is to see whether this gate–drain current can be used to monitor the oxide degradation above or near the source and/or drain extension region in N-MOSFETs. It is important because the most serious circuit-killing breakdown occurs above or near the drain (or source) extension region. Finally, we show that it is necessary, before explaining the gate LVSILC curves obtained after stresses on short-channel devices, to verify which is the dominate current at low voltage.     

High temperature characterization of high-κ dielectrics on SiC

We have fabricated thin catalytic metal–insulator–silicon carbide based structure with palladium (Pd) gates using TiO₂ as the dielectric. The temperature stability of the capacitor is of critical importance for use in the fabrication of electronics for deployment in extreme environments. We have evaluated the response to temperatures in excess of 450 °C in air and observed that the characteristics are stable. Results of high temperature characterization are presented here with extraction of interface state density up to 650 °C. The results show that at temperatures below 400 °C the capacitors are stable, with a density of interface traps of approximately 6×10¹¹ cm² eV⁻¹. Above this temperature the C–V and G–V characteristics show the influence of a second set of traps, with a density around 1×10¹³ cm² eV⁻¹, which is close to that observed for slow states near the conduction band edge. The study of breakdown field as a function of temperature shows two distinct regions, below 300 °C where the breakdown voltage has a strong temperature dependence and above 300, where it is weaker. We hypothesize that the oxide layer dominates the breakdown voltage at low temperature and the TiO₂ layer above 300 °C. These results at high temperatures confirms the suitability of the Pd/TiO₂/SiO₂/SiC capacitor structure for stable operation in high temperature environments.     

Full-band tunneling in high-κ dielectric MOS structures

High-κ oxides such as ZrO₂ and HfO₂ have attracted great interest, due to their physical properties, suitable to replacement of SiO₂ as gate dielectric materials. In this work, we investigate the tunneling properties of ZrO₂ and HfO₂ high-κ oxides, by applying quantum mechanical methods that include the full-band structure of Si and oxide materials. Semiempirical sp³s*d tight-binding parameters have been determined to reproduce ab initio band dispersions. Transmission coefficients and tunneling current have been calculated for Si/ZrO₂/Si and Si/HfO₂/Si MOS structures, showing a very low gate leakage current in comparison to SiO₂-based structures with equivalent oxide thickness.     

Modeling the silicon–hafnia interface

We report first-principles calculations of the structure and electronic properties of several different silicon–hafnia interfaces. The structures have been obtained by growing HfO_x layers of different stoichiometry on Si(1 0 0) and by repeated annealing of the system using molecular dynamics. The interfaces are characterised via their electronic and geometric properties. Moreover, electronic transport through the interfaces has been calculated using finite-element-based Green's function methods. We find that oxygen always diffuses towards the interface to form a silicon dioxide layer. This results in the formation of dangling Hf bonds in the oxide, saturated by either Hf diffusion or formation of Hf–Si bonds. The generally poor performance of the interfaces suggests that it is important to stabilise the system with respect to oxygen lattice diffusion.     

Electrical properties of metal–HfO2–silicon system measured from metal–insulator–semiconductor capacitors and metal–insulator–semiconductor field–effect transistors using HfO2 gate dielectric

Metal–insulator–semiconductor (MIS) capacitors and metal–insulator–semiconductor field effect transistors (MISFETs) incorporating HfO₂ gate dielectrics were fabricated using RF magnetron sputtering. In this work, the essential structures and electrical properties of HfO₂ thin film were examined. The leakage current measured from MIS capacitors depends on the sputtering gas mixture and the annealing temperature. The best condition to achieve the lowest leakage current is to perform the annealing at 500 °C with a mixture of 50% N₂ and 50% O₂ gas ratio. Aluminum is used as the top electrode. The Al/HfO₂ and the HfO₂/Si barrier heights extracted from Schottky emission are 1.02 eV and 0.94 eV, respectively. An Al/HfO₂/Si energy band diagram is proposed based on these results.     

Cleaning and Doping of Silicon in a BF3Plasma during Fabrication of Ohmic Contacts

The formation of reliable ohmic contacts to silicon is considered. Silicon surface cleaning, contact window doping, and molybdenum application by cathode sputtering in the BF₃atmosphere are carried out in a single vacuum cycle. A model of semiconductor–plasma and dielectric–plasma contacts under stationary discharge conditions is discussed. It is shown that the rates of processes with the participation of charged particles on p-Si and n-Si surfaces substantially differ. The resistivity of Mo-n ⁺Si and Mo-p ⁺Si contacts is the least when the molybdenum films are applied by sputtering in the Ar + (10–15) vol% BF₃atmosphere.     

Large area tunnel oxide passivated rear contact n‐type Si solar cells with 21.2% efficiency

This paper reports on the implementation of carrier‐selective tunnel oxide passivated rear contact for high‐efficiency screen‐printed large area n‐type front junction crystalline Si solar cells. It is shown that the tunnel oxide grown in nitric acid at room temperature (25°C) and capped with n⁺ polysilicon layer provides excellent rear contact passivation with implied open‐circuit voltage iV_oc of 714 mV and saturation current density J_0b′ of 10.3 fA/cm² for the back surface field region. The durability of this passivation scheme is also investigated for a back‐end high temperature process. In combination with an ion‐implanted Al₂O₃‐passivated boron emitter and screen‐printed front metal grids, this passivated rear contact enabled 21.2% efficient front junction Si solar cells on 239 cm² commercial grade n‐type Czochralski wafers. Copyright © 2016 John Wiley & Sons, Ltd.