Low-voltage organic ferroelectric field effect transistors using Langmuir–Schaefer films of poly(vinylidene fluoride-trifluororethylene)

Langmuir–Schaefer transfer was used to fabricate ultrathin films of ferroelectric copolymer, poly(vinylidene fluoride-trifluoroethylene) (70–30 mol%), for non-volatile memory application at low operating voltage. Increasing the number of transferred monolayers up to 10 led to improved film crystallinity in the “in-plane” direction, which reduced surface roughness of the semicrystalline film. Treatment of the substrate surface by plasma results in different film coverage which was subsequently found to be governed by interaction of the deposited film and surface condition. Localized ferroelectric switching was substantially attained using piezo-force tip at 10 V on 10-monolayer films. Integrating this film as a dielectric layer into organic capacitor and field effect transistor yields a reasonably good leakage current (<10^?7 A/cm²) with hysteresis in capacitance and drain current with ON/OFF ratio of 10³ for organic ferroelectric memory application at significantly reduced operating voltage of |15| V.     

Hybrid dual gate ferroelectric memory for multilevel information storage

Here, we report hybrid organic/inorganic ferroelectric memory with multilevel information storage using transparent p-type SnO semiconductor and ferroelectric P(VDF-TrFE) polymer. The dual gate devices include a top ferroelectric field-effect transistor (FeFET) and a bottom thin-film transistor (TFT). The devices are all fabricated at low temperatures (∼200 °C), and demonstrate excellent performance with high hole mobility of 2.7 cm² V⁻¹ s⁻¹, large memory window of ∼18 V, and a low sub-threshold swing ∼−4 V dec⁻¹. The channel conductance of the bottom-TFT and the top-FeFET can be controlled independently by the bottom and top gates, respectively. The results demonstrate multilevel nonvolatile information storage using ferroelectric memory devices with good retention characteristics.     

A flexible polymer memory device

A flexible polymer memory device is demonstrated in a sandwich structure of polypyrrole/P6FBEu/Au. Conductance switching at a voltage of about 4 V, with an ON/OFF current ratio up to 200, was observed in this flexible memory device. At the low-conductivity state, current density–voltage (J–V) characteristics of the device were dominated by a charge injection current. At the high conductivity state, J–V characteristics were dominated by a space-charge-limited current. Both the ON and OFF states are stable up to 10⁶ read cycles at a read voltage of 1 V. The device can be used as a write-once read-many-times (WORM) memory with good electronic stability.     

Low-voltage organic thin film transistors with hydrophobic aluminum nitride film as gate insulator

This paper reports on the low-voltage (<5 V) pentacene-based organic thin film transistors (OTFTs) with a hydrophobic aluminum nitride (AlN) gate-dielectric. In this work, a thin (about 50 nm), smooth (roughness about 0.18 nm) and low-leakage AlN gate dielectric is obtained and characterized. The AlN film is hydrophobic and the surface free energy is similar to the organic or the polymer films. The demonstrated AlN–OTFTs were operated at a low-voltage (3–5 V). A low-threshold voltage (−2 V) and an extremely low-subthreshold swing (∼170 mV/dec) were also obtained. Under low-voltage operating conditions, the on/off current ratio exceeded 10⁶, and the field effect mobility was mobility was 1.67 cm²/V s.     

Characterization of an Au/n-Si photovoltaic structure with an organic thin film

We demonstrate that a copper(II) organic complex can control the electrical characteristics of conventional Au/n-Si metal–semiconductor (MS) contacts. We investigated the electronic and photovoltaic properties of a Cu(II) complex/n-Si heterojunction diode. The ideality factor n and barrier height Φ_b of the diode were 2.22 and 0.736 eV, respectively. An ideality factor greater than unity indicates that the diode exhibits non-ideal current–voltage behavior. This behavior results from the effect of series resistance and the presence of an interfacial layer. The series resistance and barrier height determined using Norde’s method were 6.7 kΩ and 0.77 eV, respectively. The device showed photovoltaic behavior, with a maximum open-circuit voltage of 0.24 V and a short circuit current of 1.7 μA under light of 8 mW/cm².     

Polymeric gate dielectric interlayer of cross-linkable poly(styrene-r-methylmethacrylate) copolymer for ferroelectric PVDF-TrFE field effect transistor memory

A new polymeric gate dielectric interlayer of a cross-linkable poly(styrene-random-methylmethacrylate) copolymer is introduced with a good thermal and chemical resistance in bottom gate Ferroelectric Field Effect Transistor (FeFET) memory with pentacene active layer and ferroelectric poly(vinylidene fluoride-co-trifluoroethylene) (PVDF-TrFE) one. A thin uniform PVDF-TrFE film was successfully formed with well defined ferroelectric microdomains on an interlayer. Thickness of the interlayer turns out to be one of the most important factors for controlling gate leakage current which is supposed to be minimized for high ON/OFF bistability of a FeFET memory. An interlayer inserted between gate electrode and PVDF-TrFE layer significantly reduces gate leakage current, leading to source–drain OFF current of approximately 10^?11 A in particular when its thickness becomes greater than approximately 25 nm. A reliable FeFET device shows a clockwise I-V hysteresis with drain current bistablility of 10³ at ±40 V gate voltage.     

Ferroelectric random access memory based on one-transistor–one-capacitor structure for flexible electronics

We have demonstrated a low temperature process for a ferroelectric non-volatile random access memory cell based on a one-transistor–one-capacitor (1T1C) structure for application in flexible electronics. The n-channel thin film transistors (TFTs) and ferroelectric capacitors (FeCaps) are fabricated using cadmium sulfide (CdS) as the semiconductor and poly(vinylidene fluoride-trifluoroethylene) [P(VDF-TrFE)] copolymer as the ferroelectric material, respectively. The maximum processing temperature for the TFTs is 100 °C and 120 °C for the FeCaps. The TFT shows excellent access control of the FeCap in the 1T1C memory cell, and the stored polarization signals are undisturbed when the TFT is off. The fabricated 1T1C memory cell was also evaluated in a FRAM circuit. The memory window on the bit line was demonstrated as 2.3 V, based on the 1T1C memory cell with a TFT having dimensions of 80 μm/5 μm (W/L) and a FeCap with an area of 0.2 × 10^?3 cm² using a bit line capacitor of 1 nF pre-charged at 17.2 V. The 1T1C memory cell is fabricated using photolithographic processes, allowing the integration with other circuit components for flexible electronics systems.     

Electrical and photovoltaic properties of SnSe/Si heterojunction

Thin film of SnSe is deposited on n-Si single crystal to fabricate a p-SnSe/n-Si heterojunction photovoltaic cell. Electrical and photoelectrical properties have been studied by the current density–voltage (J–V) and capacitance–voltage (C–V) measurements at different temperatures. The fabricated cell exhibited rectifying characteristics with a rectification ratio of 131 at ±1 V. At low voltages (V<0.55 V), the dark forward current density is controlled by the multi-step tunneling mechanism. While at a relatively high voltage (V>0.55 V), a space charge-limited-conduction mechanism is observed with trap concentration of 2.3×10²¹ cm⁻³. The C–V measurements showed that the junction is of abrupt nature with built-in voltage of 0.62 V which decreases with temperature by a gradient of 2.83×10⁻³ V/K. The cell also exhibited strong photovoltaic characteristics with an open-circuit voltage of 425 mV, a short-circuit current density of 17.23 mA cm⁻² and a power conversion efficiency of 6.44%. These parameters have been estimated at room temperature and under light illumination provided by a halogen lamp with an input power density of 50 mW cm⁻².     

Enhanced organic ferroelectric field effect transistor characteristics with strained poly(vinylidene fluoride-trifluoroethylene) dielectric

Poly(vinylidene fluoride-trifluoroethylene) (70–30 mol%) was used as the functional dielectric layer in organic ferroelectric field effect transistors (FeFET) for non-volatile memory applications. Thin P(VDF-TrFE) film samples spin-coated on metallized plastic substrates were stretch-annealed to attain a topographically flat-grain structure and greatly reduce the surface roughness and current leakage of semi-crystalline copolymer film, while enhancing the preferred β-phase of the ferroelectric films. Resultant ferroelectric properties (P_R = |10| μC/cm², E_C = |50| MV/m) for samples simultaneously stretched (50–70% strain) and heated below the Curie transition (70 ^oC) were comparable to those resulting from high temperature annealing (>140 ^oC). The observed enhancements by heating and stretching were studied by vibration spectroscopy and showed mutual complementary effects of both processes. Organic FeFET fabricated by thermal evaporating pentacene on the smooth P(VDF-TrFE) films showed substantial improvement of semiconductor grain growth and enhanced electrical characteristics with promising non-volatile memory functionality.     

Electrical properties of Π-conjugated Fe-TPP molecular solar cell device

A heterojunction device of Au/Fe-TPP/n-Si/Al was assembled by thermally evaporated deposition. The dark current density–voltage characteristics of device were investigated. Results showed a rectification behavior. Measurements of thermo electric power confirm that Fe-TPP thin film behaves as p-type semiconductors. Electronic parameters such as barrier height, diode ideality factor, series resistance, shunt resistance were found to be 0.83 eV, 1.5, 7 × 10⁵ Ω and 2 × 10¹⁰ Ω, respectively. The Au/Fe-TPP/n-Si/Al device indicates a photovoltaic behavior with an open circuit voltage V_oc of 0.52 V, short circuit current I_sc of 2.22 × 10^?6 A, fill factor FF of 0.49 and conversion efficiency 1.13% under white light illumination power 50 W/m².     

Electrical characterization of inorganic-on-organic diode based InP and poly(3,4-ethylenedioxithiophene)/poly(styrenesulfonate) (PEDOT:PSS)

The electronic properties of metal–organic semiconductor-inorganic semiconductor diode between InP and poly(3,4-ethylenedioxithiophene)/poly(styrenesulfonate) (PEDOT:PSS) polymeric organic semiconductor film have been investigated via current–voltage and capacitance–voltage methods. The Al/PEDOT:PSS/p-InP contact exhibits a rectification behavior with the barrier height value of 0.98 eV and with the ideality factor value of 2.6 obtained from their forward bias current voltage (I–V) characteristics at the room temperature greater than the conventional Al/p-InP (0.83 eV, n = 1.13). This increase in barrier height and ideality factor can be attributed to PEDOT:PSS film formed at Al/p-InP interface.     

Interfacial layer material derived from dialkylviologen and sol–gel chemistry for polymer solar cells

Sol–gel processible organosilicate material based on dialkylviologen (1,1-(bis-trimethoxysilane)-[4,4′]bipyridium dibromide (bis-trimethoxypropylsilane)-yl-viologen, PV-Si) was synthesized and used as an interfacial layer material for polymer solar cells based on poly(3-hexylthiophene): [6,6]-phenyl-C₆₁-butyric acid methyl ester (P3HT:PCBM). PV-Si is very good soluble in polar protic solvents because of two pyrinium bromide salts and PV-Si pre-polymer can be easily prepared by sol–gel chemistry under the mild acidic conditions. From the ultraviolet spectroscopy (UPS) study, the reduction of the work function of Al and ITO is observed by the formation of interface dipole, which is induced by the thin film of thermally cured PV-Si pre-polymer (cPV-Si) at 180 °C. The open circuit voltage (V_oc) of conventional type polymer solar cell (CPSC) with a structure of ITO/active layer (P3HT:PCBM)/cPV-Si(<5 nm)/Al is 0.58 V, which is higher than the CPSC without cPV-Si (0.55 V). This indicates that the favorable interface dipole is generated by the thin film of cPV-Si. Besides, the power conversion efficiency (PCE) of CPSC with cPV-Si reaches at 2.90%, which is higher than that of the device without cPV-Si (2.69%). Surprisingly, the PCE and the short circuit current (J_sc) of inverted type polymer solar cell (IPSC) with a structure of ITO/cPV-Si (<5 nm)/active layer/WO₃/Ag are 2.83% and ?9.19 mA/cm², respectively, which are higher than those of the device with ZnO (2.51% and ?8.63 mA/cm²) as an electron transporting/injecting layer. This is due to that the work function of ITO is also reduced by the formation of interface dipole. The IPSC with cPV-Si as an interfacial layer (IFL) shows very good rectification and a contact property as well. From the results, the thin layer of cPV-Si is potential material for an IFL for either CPSC or IPSC. Especially, ZnO can be replaced by cPV-Si because of their improved device performances and pretty low processing temperature.     

Influences of embossing technology on Pb(Zr0.3,Ti0.7)O3 ferroelectric thin film

The ferroelectric random access memory (FRAM) which uses ferroelectric thin film as memory material is considered to be a candidate for the next generation memory application. In this work, we apply nano-embossing technology to fabricate Pb(Zr_0.3,Ti_0.7)O₃ (PZT) ferroelectric thin film nanostructures and investigate the influence of the patterning process on the material and ferroelectric properties by using SEM, XRD and Precision Ferroelectric Tester. Embossing process has been optimized for embossing depth and pattern profile. It was found that embossing will result in (1 0 0) preferred orientation of the PZT thin film. The electrical characteristics of patterned and un-patterned PZT films have been also studied for comparison.     

Electrical,photovoltaic and photosensitivity characteristics of p-ZnTe:N/CdTe:Mg/n-CdTe:I/GaAs for photodiode applications

In this work, heterojunctions of p-ZnTe:N/CdTe:Mg/n-CdTe:I/GaAs for photovoltaic and photodiode application were grown epitaxially by using molecular beam system. Current-voltage profile of the heterojunction device was studied in dark and under various illumination intensities. The obtained photocurrent is found to depend on the light intensity. The main heterojunction parameters, such as shunt and series resistances, the barrier height and the ideality factor were extracted from the current-voltage profile using diverse methods at ambient temperature. Values of the barrier height and the series resistance were obtained from Cheung's functions. A large value of the series resistance causes the non-ideal characteristics of current–voltage measurements. The study of the current-voltage characteristics of high voltage region suggests a predominant space charge limited mechanism. Moderate values of short circuit current and open circuit voltage were obtained through a light intensity of 140 mW/cm², a current and voltages of 0.336 mA and 370 mV, respectively. The high photosensitivity and responsivity for the current under illumination condition suggests that the prepared heterojunction device could be employed as a photodiode sensor.     

Potentiality of trap charge effects and SiON induced interface defects in a-Si3N4/SiON based MIS structure for resistive NVM device

Potential application of amorphous silicon nitride (a-Si₃N₄)/silicon oxy-nitride (SiON) film has been demonstrated as resistive non-volatile memory (NVM) device by studying the Al/Si₃N₄/SiON/p-Si metal–insulator–semiconductor (MIS) structure. The existence of several deep trap states was revealed by the photoluminescence characterizations. The bipolar resistive switching operation of this device was investigated by current–voltage measurements whereas the trap charge effect was studied in detail by hysteresis behavior of frequency dependent capacitance–voltage characteristics. A memory window of 4.6 V was found with the interface trap density being 6.4 × 10¹¹ cm⁻² eV⁻¹. Excellent charge retention characteristics have been observed for the said MIS structure enabling it to be used as a reliable non-volatile resistive memory device.     

Ferroelectric transistor memory arrays on flexible foils

In this paper, we successfully fabricated and operated passive matrix P(VDF–TrFE) transistor arrays, i.e. memory arrays in which no pass-transistors or other additional electronic components are used. Because of the smaller cell, a higher integration density is possible. We demonstrate arrays up to a size of 16 × 16, processed on thin (25 μm) poly(ethylene naphthalate) substrates, using Indium–Gallium–Zinc–Oxide (IGZO) as the semiconductor and 200 nm-thick P(VDF–TrFE) as a ferroelectric gate dielectric. The memory transistors have remnant current modulations of ～10⁵ with a retention time of more than 12 days. They can be switched in less than 1 μs at operating voltages of 25 V. Switching speed is strongly decreased with decreasing voltage: at ～10 V the transistors do not switch within 10 s. This difference in switching speed of more than 4 orders in magnitude when changing the electric field by a factor of only 2.5 makes these memories robust towards disturb voltages, and forms the basis of integration of these transistors in passive matrix-addressable transistor arrays that contains only one (memory) transistor per cell. It is shown that with current technology and memory characteristics it is possible to scale up the array size in the future.     

Synthesis and photovoltaic properties of new small molecules with rhodanine derivative as the end-capped blocks

Two new acceptor–donor–acceptor (A–D–A) type small molecules DCAO3TIDT and DCNR3TIDT, with 4,4,9,9-tetrakis(4-(dodecyloxy)phenyl)-4,9-dihydro-s-indaceno-[1,2-b:5,6-b′]dithiophene (IDT) as the core group and 2-ethylhexyl cyanoacetate (CAO) and 2-(1,1-dicyanomethylene)-3-octyl rhodanine (CNR) as different end-capped blocks, have been designed and synthesized. Both of them have been employed as donor for solution-processed bulk hetero-junction (BHJ) organic solar cells (OSCs). The two compounds showed deep highest occupied molecular orbital (HOMO) energy levels (∼−5.30 eV) and strong absorption. The DCAO3TIDT and DCNR3TIDT with PC₇₁BM as acceptor based BHJ solar cell devices showed short circuit current density (J_sc) of 6.93 mA/cm² and 8.59 mA/cm², power conversion efficiency (PCE) of 3.34% and 4.27%, respectively, and with almost same open-circuit voltage (∼0.93 V), under the illumination of AM 1.5 G, 100 mW/cm². The high J_sc for DCNR3TIDT could result from its wider and red-shifted absorption than that of DCAO3TIDT, which was probably induced by the end-capped block rhodanine derivative. The results demonstrate that the end group would be taken into full account when designing new solution-processed small molecules, which is an important factor to determine their photovoltaic properties.     

Understanding the role of organic polar solvent induced nanoscale morphology and electrical evolutions of P3HT:PCBM composite film

We investigated the effect of organic polar solvent on the properties of [6,6]-phenyl-C₇₁-butyric acid methyl ester (PCBM) films and poly(3-hexylthiophene) (P3HT):PCBM blend films employed as active layer in organic photovoltaic. The nanoscale morphology and the electrical characteristics of the P3HT:PCBM film can be controlled through organic polar solvent exposure, which exhibited with a short-circuit current density of 8.64 mA/cm², an open circuit voltage of 0.63 V, and a power conversion efficiency of 3.29% under AM 1.5 illumination with a light intensity of 100 mW/cm². By exposing the active layer films to organic polar solvent a favorable phase separation in the P3HT:PCBM films is obtained. The improved power conversion efficiency can be to the high conductivity and high surface area of the P3HT:PCBM layer treated with organic polar solvent.     

In-plane electrical bistability of photochromic diarylethene/Cu composite film

Electrical bistability is an essential property for memory devices. We report here the in-plane electrical bistability of photochromic diarylethene (DAE)/Cu composite film, which is prepared by Cu vapor deposition on the DAE surface with a low glass-transition temperature. The low-current level around 10⁻⁸ A was switched to a high-current level of ca. 10⁻⁴ A at a low threshold voltage (V_th) in the first voltage sweep. Once this switching occurred, the high-current level was kept in the second voltage sweep, and electrical bistability was achieved for the in-plane current. V_th was distributed in a wide range of voltages (0.5–10 V), and the colored sample obtained by the UV irradiation showed a relatively higher V_th than the colorless sample. The highest ON–OFF ratio in current was ca. 10⁶. The origin of the bistability attributed to the electrical breakdown in the insulated lines that was consisted of DAE in Cu film. The in-plane bistability of the DAE/Cu composite film has good retention time (>60 min) and readout-cycle endurance (>10⁶ cycles), indicating that it is suitable for write-once organic semiconductor memory characteristics.     

Ultra-thin alumina layer encapsulation of bulk heterojunction organic photovoltaics for enhanced device lifetime

Successful organic photovoltaic (OPV) device fabrication is contingent on selecting an effective encapsulation barrier layer to preserve device functionality by inhibiting atmosphere-induced degradation. In this work, ultra-thin AlO_x layers are deposited by atomic layer deposition (ALD) to encapsulate pre-fabricated OPV devices. A summary of ALD recipe effects (temperature, cycling time, and number of cycles) on AlO_x film growth and device longevity is presented. First, AlO_x film growth on the hydrophobic OPV surface is shown to occur by a 3D island growth mechanism with distinct nucleation and cluster growth regions before coalescence of a complete encapsulation layer with a thickness ⩾7 nm by 500 cycles. Encapsulated device performance testing further demonstrates that reducing ALD processing temperature to 100 °C minimizes OPV phase segregation and surface oxidation loss mechanisms as evidenced by improved short circuit current and fill factor retention when compared with the conventional 140–150 °C range. Ultra-thin AlO_x encapsulation by ALD provides significant device lifetime enhancement (∼30% device efficiency after 2000 h of air exposure), which is well beyond other ALD-based encapsulation works reported in the literature. Furthermore, the interfacial bonding strength at the OPV–AlO_x interface is shown to play a crucial role in determining film failure mode and therefore, directly impacts ultimate device lifetime.