Low operational voltage and high performance organic field effect memory transistor with solution processed graphene oxide charge storage media

Low voltage organic field effect memory transistors are demonstrated by adapting a hybrid gate dielectric and a solution processed graphene oxide charge trap layer. The hybrid gate dielectric is composed of aluminum oxide (AlO_x) and [8-(11-phenoxy-undecyloxy)-octyl]phosphonic acid (PhO-19-PA) plays an important role of both preventing leakage current from gate electrode and providing an appropriate surface energy to allow for uniform spin-casting of graphene oxide (GO). The hybrid gate dielectric has a breakdown voltage greater than 6 V and capacitance of 0.47 μF/cm². Graphene oxide charge trap layer is spin-cast on top of the hybrid dielectric and has a resulting thickness of approximately 9 nm. The final device structure is Au/Pentacene/PMMA/GO/PhO-19-PA/AlO_x/Al. The memory transistors clearly showed a large hysteresis with a memory window of around 2 V under an applied gate bias from 4 V to −5 V. The stored charge within the graphene oxide charge trap layer was measured to be 2.9 × 10¹² cm⁻². The low voltage memory transistor operated well under constant applied gate voltage and time with varying programming times (pulse duration) and voltage pulses (pulse amplitude). In addition, the drain current (I_ds) after programming and erasing remained in their pristine state after 10⁴ s and are expected to be retained for more than one year.     

Electrically erasable and reprogrammable read-only memory using the n-channel SIMOS one-transistor cell

The stacked-gate injection MOS transistor (SIMOS) uses a control gate stacked on the floating gate for selection of the cell during reading, programming, and erasure. Programming is achieved by the injection of hot electrons from the channel into the floating gate, resulting in a large upward shift in threshold voltage. In both states, operation is in the enhancement mode. Electrical erasure can be performed by injection of hot holes from an avalanche breakdown at the source-substrate junction and by Fowler-Nordheim electron injection from the floating gate to the source. Because the floating gate can be charged positively during the erasure, part of the channel is not covered by the floating gate, and in this way the enhancement mode of the SIMOS transistor after erasure is guaranteed. In a matrix array, the memory cell consists of the SIMOS transistor only. Decoders, read amplifiers, etc., can be integrated on the same substrate. Erasure can be performed as a block, or word-by-word. Different disturb effects on memory cells during programming and erasure are discussed. The cell area of the SIMOS memory is 850 µm². The photograph of a fully decoded 8192-bit SIMOS memory chip is presented.     

Conjugated Polymer Nanoparticles as Nano Floating Gate Electrets for High Performance Nonvolatile Organic Transistor Memory Devices

A molecular nano‐floating gate (NFG) of pentacene‐based transistor memory devices is developed using conjugated polymer nanoparticles (CPN) as the discrete trapping sites embedded in an insulating polymer, poly (methacrylic acid) (PMAA). The nanoparticles of polyfluorene (PF) and poly(fluorene‐alt‐benzo[2,1,3]thiadiazole (PFBT) with average diameters of around 50–70 nm are used as charge‐trapping sites, while hydrophilic PMAA serves as a matrix and a tunneling layer. By inserting PF nanoparticles as the floating gate, the transistor memory device reveals a controllable threshold voltage shift, indicating effectively electron‐trapping by the PF CPN. The electron‐storage capability can be further improved using the PFBT‐based NFG since their lower unoccupied molecular orbital level is beneficial for stabilization of the trapped charges, leading a large memory window (35 V), retention time longer than 10⁴ s with a high ON/OFF ratio of >10⁴. In addition, the memory device performance using conjugated polymer nanoparticle NFG is much higher than that of the corresponding polymer blend thin films of PF/polystyrene. It suggests that the discrete polymer nanoparticles can be effectively covered by the tunneling layer, PMAA, to achieve the superior memory characteristics.     

A two-transistor SIMOS EAROM cell

A new, electrically alterable, nonvolatile memory cell, consisting of a floating gate memory transistor and an access transistor, has been developed using the self-aligned n-channel stacked-gate injection-type MOS (SIMOS) technique. Programming is achieved by two mechanisms: channel injection of hot electrons and field emission. Analysis of experimental data shows that the contribution of the field emission mechanism to programming is significantly high when the memory device operates in the depletion mode. Erase occurs via field emission of electrons from the floating gate through a thin oxide thermally grown on monosilicon to an n/SUP +/-diffusion area placed outside the channel region of the memory transistor. This additional floating gate/n/SUP +/-diffusion overlap is also utilized to increase the programming efficiency by applying a voltage to the n/SUP +/-diffusion terminal in addition to the gate and the drain voltage. This voltage is shown to have a strong influence on the two programming mechanisms. Memory retention compares favorably with that of the most advanced electrically programmable, read-only memory (EPROM) devices. Endurance is limited by charge trapping in the thin erase oxide to approximately 10000 write/erase cycles.     

Stabilization of space charge polarization in ion-dispersed gate dielectric layer of organic transistors by ultraviolet illumination for write-once read-many memory

In this work, a new type organic field effect transistor (OFET) based write-once read-many memory (WORM) device was developed. The device uses an ultraviolet (UV) cross-linkable matrix polymer mixed with ionic compounds to form an ion-dispersed gate dielectric layer. Under an applied gate voltage bias, migration of cations and anions in opposite directions forms space charge polarization in the gate dielectric layer, resulting in change of the electrical characteristics. It is shown that, with UV illumination to cross-link the matrix polymer, the formed space charge polarization can be stabilized. Therefore, the OFET can be operated as a WORM with the applied voltage bias to define the polarization and in turn the stored data, and the UV illumination to stabilize the stored data.     

Controllable Shifts in Threshold Voltage of Top‐Gate Polymer Field‐Effect Transistors for Applications in Organic Nano Floating Gate Memory

Organic field‐effect transistor (FET) memory is an emerging technology with the potential to realize light‐weight, low‐cost, flexible charge storage media. Here, solution‐processed poly[9,9‐dioctylfluorenyl‐2,7‐diyl]‐co‐(bithiophene)] (F8T2) nano floating gate memory (NFGM) with a top‐gate/bottom‐contact device configuration is reported. A reversible shift in the threshold voltage (V_Th) and reliable memory characteristics was achieved by the incorporation of thin Au nanoparticles (NPs) as charge storage sites for negative charges (electrons) at the interface between polystyrene and cross‐linked poly(4‐vinylphenol). The F8T2 NFGM showed relatively high field‐effect mobility (µ_FET) (0.02 cm² V^?1 s^?1) for an amorphous semiconducting polymer with a large memory window (ca. 30 V), a high on/off ratio (more than 10⁴) during writing and erasing with an operation voltage of 80 V of gate bias in a relatively short timescale (less than 1 s), and a retention time of a few hours. This top‐gated polymer NFGM could be used as an organic transistor memory element for organic flash memory.     

Electrically alterable avalanche-injection-type MOS READ-ONLY memory with stacked-gate structure

Design theory and experimental results of the WRITE and ERASE properties of a rewritable and nonvolatile avalanche-injection-type memory are reported. The memory transistor has the stacked-gate structure of a floating gate and a control gate. The threshold-voltage shift of the transistor due to injected charge is controlled by applied potential on the control gate which reduces the avalanche breakdown voltage of the drain junction and accelerates electron injection into the floating gate. The writing time is about 20 µs for a single transistor and is less than 5 s for a fully decoded 2048-bit memory with appropriate duty cycles of programming pulses. Erasure of the memory is accomplished either by ultraviolet light irradiation onto the floating gate or by electric field emission of electrons from the floating gate to the control gate. Electrical erasing is theoretically analyzed and successfully compared with experimental results on the 2K bit memory. Memory retention is also investigated and a charge-escaping model is proposed.     

An 8192-bit electrically alterable ROM employing a one-transistor cell with floating gate

Describes a fully decoded, TTL compatible, electrically alterable, 8-kbit MOS ROM using a two-level n-channel polysilicon gate process. The memory cell consists of a single transistor with stacked gate structure where the floating gate covers only one part of the channel and is extended to an erase overlap of the source diffusion region off the channel. Programming in typically 100 ms/word is achieved by injection of hot electrons from the short channel (3.5 /spl mu/m) into the floating gate. Electrical block erasure is performed by Fowler-Nordheim emission of electrons from the floating gate. To avoid excessive avalanche breakdown currents during erasure 40 nm-50 nm oxides at the erase overlap and a voltage ramp are used. The memory operates with standard voltages (/spl plusmn/5 V, +12 V), during read, program and erase operation, a single pulsed high voltage (+26 V) for programming, and an erase voltage ramp of +35 V maximum. Typical access time is 250 ns.     

Organic field-effect transistors and memory elements using deoxyribonucleic acid (DNA) gate dielectric

Deoxyribonucleic acid (DNA) bio-polymers derived from fish waste products are employed as gate dielectric in n-type methanofullerene as well as p-type pentacene based organic field-effect transistors working at low voltage levels and low gate leakage currents. Based on the large hysteresis in the transfer characteristics, operation of the transistor as a non-volatile memory element is shown. Practically hysteresis free operation of DNA based transistors is obtained at low voltage levels by adding an additional aluminium oxide blocking layer between the organic semiconductor and the DNA gate dielectric.     

N-type polymeric organic flash memory device: Effect of reduced graphene oxide floating gate

In this paper, n type nonvolatile memory devices were fabricated by implanting a bilayer (rGO sheets/Au NP) floating gates, using n-type polymer semiconductor, poly {[N, N′ bis (2octyldodecyl) - naphthalene-1, 4, 5, 8 - bis (dicarboximide)-2,6-diyl] – alt - 5,5′ - (2, 2′ bithiophene)} [P(NDI2OD-T2)n]. In the developed organic field effect transistor memory devices, electrons are trapped/detrapped in rGO sheet/Au NP's nano-floating gates by controlling the charge carrier density in the active layer through back gate bias control. The devices showed interesting non-volatile memory properties with a large memory window of ∼34 V, a programming-reading-erasing cycling endurance of 103 times and most importantly, an improved retention time characteristics estimated by extrapolation (longer than the technological requirement of commercial memory devices (>10 years)). This approach provides a great potential for fabricating high-performances organic nano-floating gate memory devices and opens up a new way for the development of next-generation non-volatile memory devices.     

Large‐Area Schottky Barrier Transistors Based on Vertically Stacked Graphene–Metal Oxide Heterostructures

The fabrication of all‐transparent flexible vertical Schottky barrier (SB) transistors and logic gates based on graphene–metal oxide–metal heterostructures and ion gel gate dielectrics is demonstrated. The vertical SB transistor structure is formed by (i) vertically sandwiching a solution‐processed indium‐gallium‐zinc‐oxide (IGZO) semiconductor layer between graphene (source) and metallic (drain) electrodes and (ii) employing a separate coplanar gate electrode bridged with a vertical channel through an ion gel. The channel current is modulated by tuning the Schottky barrier height across the graphene–IGZO junction under an applied external gate bias. The ion gel gate dielectric with high specific capacitance enables modulation of the Schottky barrier height at the graphene–IGZO junction over 0.87 eV using a voltage below 2 V. The resulting vertical devices show high current densities (18.9 A cm^?2) and on–off current ratios (>10⁴) at low voltages. The simple structure of the unit transistor enables the successful fabrication of low‐power logic gates based on device assemblies, such as the NOT, NAND, and NOR gates, prepared on a flexible substrate. The facile, large‐area, and room‐temperature deposition of both semiconducting metal oxide and gate insulators integrates with transparent and flexible graphene opens up new opportunities for realizing graphene‐based future electronics.     

Silicon-on-insulator nanotransistors with two independent gates

The results of numerical simulation of electrical characteristics of silicon-on-insulator MOSFET nanotransistors with two independent gates are reported. The cases of grounded and floating bases with the surface recombination of charge carriers either disregarded or taken into account are considered. It is shown that, at specified design parameters (gate length 50–100 nm, thickness of silicon layer 25–50 nm), one can vary the transistor’s threshold voltage by 0.45 V, reduce the transistor current in the off state by seven orders of magnitude, and decrease the subthreshold slope of the gate characteristics to 60 mV/decade by varying the voltage applied to the second gate. Suppression of the short-channel effects in the transistors under consideration depends on a number of parameters (listed in order of decreasing effect): the gate material, the lifetime of charge carriers (for floating or grounded base), the thickness of the top silicon layer, the voltage applied to the additional gate, and the channel length.     

液晶栅介质场效应晶体管及突触行为模拟

采用液晶E7作为栅介质,聚异靛蓝噻吩乙烯噻吩(PII-TVT)作为半导体,利用光刻/蚀刻技术制备了漏极-源极-栅极(D-S-G)共面的有机场效应晶体管器件,并测试了晶体管性能,对液晶作为栅介质应用于有机场效应晶体管进行研究。实验结果表明,器件表现出比较特别的晶体管性能,开关比达到10~3。通过光学显微镜观察发现,施加栅极电压后液晶发生形变,表明栅极电压对电极上的液晶分子的取向排列有较大影响。在施加脉冲栅压时,沟道电流随着脉冲栅压时间的延长而增强。利用液晶分子在电场下发生极化和迟滞作用,可一定程度上模拟突触的刺激时间依赖性。     

Fatigue phenomena of FTMIS memory transistors

Two operation modes of long endurance and their fatigue properties are described for a nonvolatile charge storage memory device which employs a floating silicon gate tunnel injection MIS (FTMIS) structure. The device is composed of an n-channel metal gate field effect transistor with a floating gate over tunnelable (20-35 Å) SiO2. The floating gate consists of highly resistive polycrystalline Si grains. Gate oxidation isolates each poly-Si grain, resulting in a structure of islands. This improves retention characteristics. The primary feature of these devices is that no fatigue phenomena are observed for 2 × 10¹²cycles continuous write-erase operation in the conventional operation mode. In addition, it is possible both to write and erase in the other operation mode with only positive pulses to the gate electrode. Furthermore, stored data is retained more than one year without any external power supply. Therefore the device is an excellent candidate for nonvolatile RAM applications as a semiconductor memory device.     

基于标准CMOS工艺的新型pH值传感器

基于0.6μmCMOS工艺设计了一种新型的pH值传感器。多晶硅和双层金属电极形成复合的悬浮栅结构,Si3N4钝化层作为敏感层。传感单元为W/L=500μm/20μm的PMOS管,其阈值电压随溶液pH值线性变化,并通过恒定PMOS管源漏电压和源漏电流控制电路转换成PMOS管源电压线性输出。PMOS管源电压线性输出范围达到4.6V,很好满足在不同pH值溶液中测试的要求。采用波长396nm紫外灯管照射来消除浮栅上电荷,增大阈值电压并有效调整溶液栅电压线性区工作范围。紫外照射后溶液栅电压可偏置在0V,减少溶液中噪声影响。CMOSpH值传感器的平均灵敏度为35.8mV/pH。     

Nonvolatile Ferroelectric P(VDF‐TrFE) Memory Transistors Based on Inkjet‐Printed Organic Semiconductor

Nonvolatile ferroelectric poly(vinylidene fluoride‐co‐trifluoroethylene) memory based on an organic thin‐film transistor with inkjet‐printed dodecyl‐substituted thienylenevinylene‐thiophene copolymer (PC12TV12T) as the active layer is developed. The memory window is 4.5 V with a gate voltage sweep of ?12.5 V to 12.5 V. The field effect mobility, on/off ratio, and gate leakage current are 0.1 cm²/Vs, 10⁵, and 10^?10 A, respectively. Although the retention behaviors should be improved and optimized, the obtained characteristics are very promising for future flexible electronics.     

Voltage-readable nonvolatile memory cell with programmable ferroelectric multistates in organic inverter configuration

We demonstrate a voltage-readable nonvolatile memory cell with programmable ferroelectric multistates in an organic inverter configuration. The intermediate memory states of a ferroelectric gate insulator, varying with the magnitude of the programming voltage, allow the multilevels of the drain current at zero gate-source voltage in a ferroelectric organic field-effect transistor (OFET). The current output from the ferroelectric memory is directly converted into the voltage-readable output in a zero-gate load inverter configuration where both a driving paraelectric OFET having a paraelectric buffer layer and a load ferroelectric OFET are monolithically integrated in a single substrate. The multilevel voltage-readable output characteristics are obtained from the ferroelectric multistates as a function of the programming voltage.     

Tunnel field-effect transistors with graphene channels

The lack of an OFF-state has been the main obstacle to the application of graphene-based transistors in digital circuits. Recently vertical graphene tunnel field-effect transistors with a low OFF-state current have been reported; however, they exhibited a relatively weak effect of gate voltage on channel conductivity. We propose a novel lateral tunnel graphene transistor with the channel conductivity effectively controlled by the gate voltage and the subthreshold slope approaching the thermionic limit. The proposed transistor has a semiconductor (dielectric) tunnel gap in the channel operated by gate and exhibits both high ON-state current inherent to graphene channels and low OFF-state current inherent to semiconductor channels.     

Role of tunneling layer in graphene-oxide based organic nonvolatile memory transistors

This paper demonstrates non-volatile memory transistor using solution processable graphene oxide (GO) as charge storage nodes in the configuration, p⁺⁺Si/SiO₂/GO/Tunneling layer/Pentacene/Au. The tunneling layers are polymethylmethacrylate (PMMA) and polyvinylphenol (PVP). GO film could be deposited as single layered flakes with a uniform distribution using spin coating technique. The devices with PMMA as charge tunneling layer exhibited higher mobility and on/off ratio than PVP based devices. The devices show a large positive threshold voltage shift (∼24 V for PMMA and ∼15 V for PVP) from initial value during programming at gate voltage of +80 V kept for 10 s. The transfer curves can be restored approximately to its initial condition by applying an erasing voltage of −30 V for 10 s for both the devices. Since such a large shift is not observed without GO layer, we consider that memory effect was due to electron trapping in GO. Further, retention of the initial memory window was measured to be 63% and 37% after 3000 s for PMMA and PVP based devices, respectively.     

A side-wall transfer-transistor cell (SWATT cell) for highlyreliable multi-level NAND EEPROMs

A multi-level NAND Flash memory cell, using a new Side-WAll Transfer-Transistor (SWATT) structure, has been developed for a high performance and low bit cost Flash EEPROM. With the SWATT cell, a relatively wide threshold voltage (V_th) distribution of about 1.1 V is sufficient for a 4-level memory cell in contrast to a narrow 0.6 V distribution that is required for a conventional 4-level NAND cell. The key technology that allows this wide V_th distribution is the Transfer Transistor which is located at the side wall of the Shallow Trench Isolation (STI) region and is connected in parallel with the floating gate transistor. During read, the Transfer Transistors of the unselected cells (connected in series with the selected cell) function as pass transistors. So, even if the V_th of the unselected floating gate transistor is higher than the control gate voltage, the unselected cell will be in the ON state. As a result, the V_th distribution of the floating gate transistor can be wider and the programming can be faster because the number of program/verify cycles can be reduced. Furthermore, the SWATT cell results in a very small cell size of 0.57 μm² for a 0.35 μm rule. Thus, the SWATT cell combines a small cell size with a multi-level scheme to realize a very low bit cost. This paper describes the process technology and the device performance of the SWATT cell, which can be used to realize NAND EEPROM's of 512 Mbit and beyond