Thin film encapsulation for organic light emitting diodes using a multi-barrier composed of MgO prepared by atomic layer deposition and hybrid materials

We demonstrated an organic/inorganic multi-barrier and encapsulation for flexible OLED devices. The multi-barrier consisted of a silica nanoparticle-embedded hybrid nanocomposite, in short, S-H nanocomposite, and MgO, which were used as organic and inorganic materials, respectively. The S-H nanocomposite was spin-coated followed by UV curing. The thickness of the S-H nanocomposite was 200 nm, and 40 nm of MgO was deposited by atomic layer deposition (ALD) using Mg(CpEt)₂ and H₂O at 70 °C. The results of a Ca test showed that the 4.5 dyads of the MgO/S-H nanocomposite had a low water vapor transmission rate (WVTR) of 4.33 × 10^?6 g/m²/day and an optical transmittance of 84%. The normalized luminance degradation of the thin film encapsulated OLED was also identical to that of glass-lid encapsulation after 1000 h of the real operation time. We proposed low temperature ALD as a deposition method to create relatively thin film for OLED passivation without degradation, such as creation of dark spots. The results confirmed that it may be feasible for our multi-barrier to passivate flexible OLEDs devices.     

A flexible moisture barrier comprised of a SiO2-embedded organic–inorganic hybrid nanocomposite and Al2O3 for thin-film encapsulation of OLEDs

We demonstrated a high performance flexible multi-barrier containing a silica nanoparticle-embedded organic–inorganic hybrid (S–H) nanocomposite and Al₂O₃. The multi-barrier was prepared by low-temperature Al₂O₃ atomic layer deposition and with a spin-coated S–H nanocomposite. The moisture barrier properties were investigated with a water vapor transmission rate (WVTR), estimated by a Ca test at 30 °C, 90% R.H.. Moisture diffusion was effectively suppressed by the sub-700 nm thick multi-barrier incorporating well-dispersed silica nanoparticles in the organic layer. A low WVTR of 1.14 × 10^?5 g/m² day and average transmittance of 85.8% in the visible region were obtained for the multi-barrier. After bending under tensile stress mode, the moisture barrier property of the multi-barriers was retained. The multi-barrier was successfully applied to thin-film encapsulation of OLEDs. The thin-film encapsulated OLEDs showed practicable current–voltage–luminance (I–V–L) characteristics and stable real operation over 700 h under ambient conditions.     

Growth behavior and improved water–vapor-permeation-barrier properties of 10-nm-thick single Al2O3 layer grown via cyclic chemical vapor deposition on organic light-emitting diodes

We have investigated the growth behavior and water vapor permeation barrier properties of cyclic chemical vapor deposition (C-CVD)-grown 10-nm-thick single layer of Al₂O₃. Al₂O₃ layers grown by C-CVD showed a high density of 3.298 g/cm³ and were amorphous without grain boundaries. A deposition rate of 0.46 nm/cycle was obtained. The C-CVD system was self-limiting, as in the case of atomic layer deposition, which enables precise control of the thickness of the Al₂O₃ layer. A water vapor transmission rate of 1.51 × 10⁻⁵ (g/m²)/day was obtained from a Ca degradation test performed at 85 °C and 85% relative humidity. Moreover, the performance of organic light-emitting diodes, passivated by a C-CVD-grown 10-nm-thick Al₂O₃ single layer, was not affected after 24,000 h of turn-on time; this is strong evidence that C-CVD-grown Al₂O₃ layers effectively prevent water vapor from diffusing into the active organic layer.     

Effect of gate insulator thickness on device performance of InGaZnO thin-film transistors

Top-contact thin-film transistors (TFTs) are fabricated in this work using atomic layer deposition (ALD) Al₂O₃ as the gate insulator and radio frequency sputtering InGaZnO (IGZO) as the channel layer so as to investigate the effect of Al₂O₃ thickness on the performance of IGZO-TFTs. The results show that TFT with 100-nm-thick Al₂O₃ (100 nm-Al₂O₃-TFT) exhibits the best electrical performance; specifically, field-effect mobility of 5 cm²/Vs, threshold voltage of 0.95 V, I_on/I_off ratio of 1.1×10⁷ and sub-threshold swing of 0.3 V/dec. The 100 nm-Al₂O₃-TFT also shows a substantially smaller threshold voltage shift of 1.1 V after a 10 V gate voltage is applied for 1 h, while the values for TFTs with an Al₂O₃ thickness of 220 and 280 nm are 1.84 and 2 V, respectively. The best performance of 100 nm-Al₂O₃-TFT can be attributed to the larger capacitance and the smaller amount of total trap centers possessed by a thinner insulator compared to the thicker ones.     

High barrier properties of transparent thin-film encapsulations for top emission organic light-emitting diodes

This paper reported a low-temperature thin film encapsulation (TFE) process based on atomic layer deposition Al₂O₃ layer for top-emission organic light-emitting devices (TE-OLEDs). The barrier characteristics of both H₂O-based and O₃-based Al₂O₃ films were investigated. O₃-based Al₂O₃ TFE showed lower water vapor transmission rate (WVTR) of 8.7 × 10⁻⁶ g/m² day and longer continuous operation lifetime of 5 folds compared to the device with H₂O-based Al₂O₃ TFE under identical environmental and driving conditions. Furthermore, the extraction of emitting light of the devices with barrier layer was enhanced compared to the bared one. The theory simulation data were consistent with our experimental results and showed the potential for the design of TFE structures optimized for enhancing light transmission.     

Interface studies of ALD-grown metal oxide insulators on Ge and III–V semiconductors (Invited Paper)

Atomic layer deposited (ALD) HfO₂/GeO_xN_y/Ge(1 0 0) and Al₂O₃/In_0.53Ga_0.47As(1 0 0) ? 4 × 2 gate stacks were analyzed both by MOS capacitor electrical characterization and by advanced physical characterization to correlate the presence of electrically-active defects with chemical bonding across the insulator/channel interface. By controlled in situ plasma nitridation of Ge and post-ALD annealing, the capacitance-derived equivalent oxide thickness was reduced to 1.3 nm for 5 nm HfO₂ layers, and mid-gap density of interface states, D_it = 3 × 10¹¹ cm^?2 eV^?1, was obtained. In contrast to the Ge case, where an engineered interface layer greatly improves electrical characteristics, we show that ALD-Al₂O₃ deposited on the In_0.53Ga_0.47As (1 0 0) ? 4 × 2 surface after in situ thermal desorption in the ALD chamber of a protective As cap results in an atomically-abrupt and unpinned interface. By avoiding subcutaneous oxidation of the InGaAs channel during Al₂O₃ deposition, a relatively passive gate oxide/III–V interface is formed.     

Memory characteristics of Al2O3/La2O3/Al2O3 multi-layer films with various blocking and tunnel oxide thicknesses

In order to investigate charge trap characteristics with various thicknesses of blocking and tunnel oxide for application to non-volatile memory devices, we fabricated 5 and 15 nm Al₂O₃/5 nm La₂O₃/5 nm Al₂O₃ and 15 nm Al₂O₃/5 nm La₂O₃/5, 7.5, and 10 nm Al₂O₃ multi-stack films, respectively. The optimized structure was 15 nm Al₂O₃ blocking oxide/5 nm La₂O₃ trap layer/5 nm Al₂O₃ tunnel oxide film. The maximum memory window of this film of about 1.12 V was observed at 11 V for 10 ms in program mode and at ?13 V for 100 ms in erase mode. At these program/erase conditions, the threshold voltage of the 15 nm Al₂O₃/5 nm La₂O₃/5 nm Al₂O₃ film did not change for up to about 10⁴ cycles. Although the value of the memory window in this structure was not large, it is thought that a memory window of 1.12 V is acceptable in the flash memory devices due to a recently improved sense amplifier.     

Deposition of aluminum oxide-doped zinc oxide transparent nano-films on glass substrates for electrostatic discharge applications

Aluminum oxide-doped zinc oxide (ZnO:Al₂O₃) transparent thin films were deposited by DC magnetron sputtering on glass substrates; film thickness can be correlated with deposition time. The effect of ZnO:Al₂O₃ film thickness on electrical properties, ultraviolet (UV) transmission, surface morphology and structure, solvent resistance, and scratch hardness was investigated. The surface roughness and crystallite size of deposited films increased from 0.75 to 2.22 nm and from 14 to 57 nm, respectively, as the film thickness was increased from 18 to 112 nm. In contrast, the percent UV transmission (% T) of ZnO:Al₂O₃ deposited glass plates at a wavelength of 365 nm increased when the film thickness was decreased. The electrical properties of nano-film deposited glass plates such as electrical resistance, tribo-charge voltage, and decay time were in the range of electrostatic discharge (ESD) specifications. The ZnO:Al₂O₃ nano-film deposited glass substrate possessed good acetone and iso-propanol resistance as well as high scratch hardness. This work opens up the possibility of using the ZnO:Al₂O₃ transparent ultra-thin film on glass substrate in ESD applications based on their excellent properties in terms of the relatively thin and adjustable ZnO:Al₂O₃ film thickness needed.     

Effect of AlN buffer layer thickness on the properties of GaN films grown by pulsed laser deposition

The GaN films are grown by pulsed laser deposition (PLD) on sapphire, AlN(30 nm)/Al₂O₃ and AlN(150 nm)/Al₂O₃, respectively. The effect of AlN buffer layer thickness on the properties of GaN films grown by PLD is investigated systematically. The characterizations reveal that as AlN buffer layer thickness increases, the surface root-mean-square (RMS) roughness of GaN film decreases from 11.5 nm to 2.3 nm, while the FWHM value of GaN film rises up from 20.28 arcmin to 84.6 arcmin and then drops to 31.8 arcmin. These results are different from the GaN films deposited by metal organic chemical vapor deposition (MOCVD) with AlN buffer layers, which shows the improvement of crystalline qualities and surface morphologies with the thickening of AlN buffer layer. The mechanism of the effect of AlN buffer layer on the growth of GaN films by PLD is hence proposed.     

Enhanced OLED performance upon photolithographic patterning by using an atomic-layer-deposited buffer layer

This study addresses the problem of patterning-induced degradations to organic light-emitting diodes (OLEDs) by using a thin (10 Å) atomic-layer-deposited (ALD) Al₂O₃ film as both an electron-injection layer and a protecting layer for the electroluminescent material, poly[1-methoxy-4-(2′-ethyl-hexyloxy)-2,5-phenylene vinylene] (MEH-PPV). With the ALD Al₂O₃ film, the OLEDs not only withstood an aggressive photolithographic patterning process without any degradation but unprecedentedly showed increased luminous efficiency (by 100%) and lowered turn-on voltage (by 19%) afterward. Although the ALD precursor, trimethylaluminum (TMA), was found to damage the MEH-PPV layer through electrophilic addition to the vinylene groups of MEH-PPV during the deposition of the Al₂O₃ film, its damaging effect was eliminated by pre-treating the MEH-PPV surface with isopropyl alcohol (IPA), whose hydroxyl groups scavenged TMA throughout the ALD process. The performance of the photo-patterned OLEDs was further improved by using a high-conductivity hole-injection layer, which increased accumulation of holes at the EL–buffer interface to enhance electron injection. The method reported herein improves the applicability of photolithography to OLED fabrication, promising to resolve the issue of patterning that has in part impeded OLED’s commercialization.     

Analysis of nanometer-scale InGaAs/InAs/InGaAs composite channel MOSFETs using high-K dielectrics for high speed applications

The outstanding electron transport properties of InGaAs and InAs semiconductor materials, makes them attractive candidates for future nano-scale CMOS. In this paper, the ON state and OFF state performance of 30 nm gate length InGaAs/InAs/InGaAs buried composite channel MOSFETs using various high-K dielectric materials is analyzed using Synopsys TCAD tool. The device features a composite channel to enhance the mobility, an InP spacer layer to minimize the defect density and a heavily doped multilayer cap. The simulation results show that MOSFETs with Al₂O₃/ZrO₂ bilayer gate oxide exhibits higher gm/I_D ratio and lower sub threshold swing than with the other dielectric materials. The measured values of threshold voltage (V_T), on resistance (R_ON) and DIBL for Lg = 30 nm In_0.53Ga_0.47As/InAs/In_0.53Ga_0.47As composite channel MOSFET having Al₂O₃/ZrO₂ (EOT = 1.2 nm) bilayer dielectric as gate oxide are 0.17 V, 290 Ω-µm, and 65 mV/V respectively. The device displays a transconductance of 2 mS/µm.     

High-performance pentacene field-effect transistors using Al2O3 gate dielectrics prepared by atomic layer deposition (ALD)

High-performance pentacene field-effect transistors have been fabricated using Al₂O₃ as a gate dielectric material grown by atomic layer deposition (ALD). Hole mobility values of 1.5 ± 0.2 cm²/V s and 0.9 ± 0.1 cm²/V s were obtained when using heavily n-doped silicon (n⁺-Si) and ITO-coated glass as gate electrodes, respectively. These transistors were operated in enhancement mode with a zero turn-on voltage and exhibited a low threshold voltage (< −10 V) as well as a low sub-threshold slope (<1 V/decade) and an on/off current ratio larger than 10⁶. Atomic force microscopy (AFM) images of pentacene films on Al₂O₃ treated with octadecyltrichlorosilane (OTS) revealed well-ordered island formation, and X-ray diffraction patterns showed characteristics of a “thin film” phase. Low surface trap density and high capacitance density of Al₂O₃ gate insulators also contributed to the high performance of pentacene field-effect transistors.     

Use of Al2O3 as inter-poly dielectric in a production proven 130 nm embedded Flash technology

We have successfully integrated 2 Mb arrays with SiO₂/Al₂O₃ stacks as inter-poly dielectric (IPD) fabricated in a proven 130 nm embedded Flash technology. Gate stack write/erase high voltages (HV) can be reduced by 3 V. Write/erase distributions show evidence of bit pinning which can be explained by barrier lowering along Al₂O₃ grain boundaries. Reliability assessment of the 2 Mb array reveals promising data retention and cycle endurance, indicating the absence of charge trapping in the high-k IPD. Despite several integration issues, these results demonstrate the high potential of Al₂O₃ IPDs in embedded Flash technologies.     

Effect of interface traps for ultra-thin high-k gate dielectric based MIS devices on the capacitance-voltage characteristics

The impact of states at the Al₂O₃/Si interface on the capacitance-voltage C-V characteristics of a metal/insulator/semiconductor heterostructure (MIS) capacitor was studied by a numerical simulation, by solving Schrodinger-Poisson equations and taking the electron emission rate from the interface state into account. Efficient computation and accurate physics based capacitance model of MOS devices with advanced ultra-thin equivalent oxide thickness (EOT) (down to 2.5 nm clearly considered here) were introduced for the near future integrated circuit IC technology nodes. Due to the importance of the interface state density for a low dimension and very low oxide thickness, a high frequency C-V model has been developed to interpret the effect of interface state density traps which communicate with the Al₂O₃/Si and their influence on the C-V characteristics. We found that these states are manifested by jumping capacity in the inversion zone, for a density of interface, higher than 1 × 10¹¹ cm^− 2 eV^− 1 during a p-doping of 1 × 10¹⁸ cm^− 3. This behavior has been investigated with various doping, temperature, frequency and energy levels on the C-V curves, and compared with the MIS structure that contains a standard SiO₂ insulator.     

Effect of nano Al2O3 particles doping on electromigration and mechanical properties of Sn–58Bi solder joints

In the present study, the effect of Al₂O₃ nanoparticles on performances of Sn–58Bi solder were investigated in aspects of electro-migratio, shear strength and microhardness. The experimental results show that the Al₂O₃ nanoparticles significantly improved microstructure and mechanical performances of solder joints. With the addition of 0.5 wt% Al₂O₃, the intermetallic compounds (IMC) reduced from 2.5 μm to 1.27 μm after 288 aging hours at 85 °C. Furthermore, after electromigration test under a current density of 5 × 10³ A/cm² at 85 °C, Bi-rich layers formed at the anode side of both Al₂O₃ doped and plain solder. Moreover, the addition of Al₂O₃ nanoparticles reduced the mean thickness of Bi-rich layer. In addition, the growth rate of the IMC layer of Al₂O₃ doped solder decreased by 8% compared with the plain solder. Besides, the Al₂O₃ doped solder exhibited better performance than plain solder in microhardness after different aging times. While, the addition of Al₂O₃ significantly impeded the degradation of the shear strength of solder joint after aging for 48 and 288 h. Furthermore, it was worth noting that the fracture surface of doped solder showed a typical rough and ductile structure. However, plain solder exhibited a relatively smooth and fragile surface.     

Characterization of scaled MANOS nonvolatile semiconductor memory (NVSM) devices

We have modeled and characterized scaled Metal–Al₂O₃–Nitride–Oxide–Silicon (MANOS) nonvolatile semiconductor memory (NVSM) devices. The MANOS NVSM transistors are fabricated with a high-K (K_A = 9) blocking insulator of ALD deposited Al₂O₃ (8 nm), a LPCVD silicon nitride film (8 nm) for charge-storage, and a thermally grown tunneling oxide (2.2 nm). A low voltage program (+8 V, 30 μs) and erase (?8 V, 100 ms) provides an initial memory window of 2.7 V and a 1.4 V window at 10 years for an extracted nitride trap density of 6 × 10¹⁸ traps/cm³ eV. The devices show excellent endurance with no memory window degradation to 10⁶ write/erase cycles. We have developed a pulse response model of write/erase operations for SONOS-type NVSMs. In this model, we consider the major charge transport mechanisms are band-to-band tunneling and/or trap-assisted tunneling. Electron injection from the inversion layer is treated as the dominant carrier injection for the write operation, while hole injection from the substrate and electron injection from the gate electrode are employed in the erase operation. Meanwhile, electron back tunneling is needed to explain the erase slope of the MANOS devices at low erase voltage operation. Using a numerical method, the pulse response of the threshold voltages is simulated in good agreement with experimental data. In addition, we apply this model to advanced commercial TANOS devices.     

Active layer thickness effect on the recombination process of PCDTBT:PC71BM organic solar cells

We investigated the effect of active layer thickness on recombination kinetics of poly[N-9″-hepta-decanyl-2,7-carbazole-alt-5,5-(4′,7′-di-2-thienyl-2′,1′,3′-benzothiadiazole)] (PCDTBT) and [6,6]-phenyl C71-butyric acid methyl ester (PC₇₁BM) based solar cells. Analysis of the fitted Lambert W-function of illuminated current density–voltage (J–V) characteristics revealed increased recombination processes with increased active layer thicknesses. The ideality factor extracted from PCDTBT:PCBM solar cells continuously increased from 1.89 to 3.88 when photoactive layer thickness was increased from 70 to 150 nm. We found that such increase in ideality factor is closely related to the defect density which is increased with increased photoactive layer thickness beyond 110 nm. Therefore, the different density of defect states in PCDTBT:PCBM solar cells causes the different recombination paths where solar cells with a thicker active layer (?110 nm) are considered to undergo coupled trap-assisted recombination processes while single-defect trap-assisted recombination is dominant for thinner (70–90 nm) PCDTBT:PCBM solar cells. As a result, we found that the optimal efficiencies of PCDTBT:PC₇₁BM solar cells were limited to the active layers between 70 and 90 nm. Particularly, when PCDTBT:PC₇₁BM solar cells were optimized with an active layer thickness of 70 nm, energy conversion efficiency reached 6.5% while an increase in thickness led to the reduction of efficiency to 4.7% at 133 nm but then an increase to 5.02% at 150 nm.     

The nature of the aluminum–aluminum oxide interface: A nanoscale picture of the interfacial structure and energy-level alignment

We propose a new structural model for the Al(1 1 1)/Al₂O₃(0 0 0 1) interface based on density functional theory calculations. The ultrathin interface structure is shown to consist of two Al layers, one that is oxide-like and the other metal-like. Our model interface reproduces the barrier height to the oxide conduction band edge and predicts the oxide overlayer to lower the metal work function by 0.49 eV.     

Ultra-low-energy ion-beam-synthesis of Ge nanocrystals in thin ALD Al2O3 layers for memory applications

Structural and electrical properties of ALD-grown 5 and 7 nm-thick Al₂O₃ layers before and after implantation of Ge ions (1 keV, 0.5–1 × 10¹⁶ cm^?2) and thermal annealing at temperatures in the 700–1050 °C range are reported. Transmission Electron Microscopy reveals the development of a 1 nm-thick SiO₂-rich layer at the Al₂O₃/Si substrate interface as well as the formation of Ge nanocrystals with a mean diameter of ～5 nm inside the implanted Al₂O₃ layers after annealing at 800 °C for 20 min. Electrical measurements performed on metal–insulator–semiconductor capacitors using Ge-implanted and annealed Al₂O₃ layers reveal charge storage at low-electric fields mainly due to location of the Ge nanocrystals at a tunnelling distance from the substrate and their spatial dispersion inside the Al₂O₃ layers.     

Influence of processing and annealing steps on electrical properties of InAlN/GaN high electron mobility transistor with Al2O3 gate insulation and passivation

We report on preparation and electrical characterization of InAlN/AlN/GaN metal–oxide–semiconductor high electron mobility transistors (MOS HEMTs) with Al₂O₃ gate insulation and surface passivation. About 12 nm thin high-κ dielectric film was deposited by MOCVD. Before and after the dielectric deposition, the samples were treated by different processing steps. We monitored and analyzed the steps by sequential device testing. It was found that both intentional (ex situ) and unintentional (in situ before Al₂O₃ growth) InAlN surface oxidation increases the channel sheet resistance and causes a current collapse. Post deposition annealing decreases the sheet resistance of the MOS HEMT devices and effectively suppresses the current collapse. Transistors dimensions were source-to-drain distance 8 μm and gate width 2 μm. A maximum transconductance of 110 mS/mm, a drain current of ～0.6 A/mm (V_GS = 1 V) and a gate leakage current reduction from 4 to 6 orders of magnitude compared to Schottky barrier (SB) HEMTs was achieved for MOS HEMT with 1 h annealing at 700 °C in forming gas ambient. Moreover, InAlN/GaN MOS HEMTs with deposited Al₂O₃ dielectric film were found highly thermally stable by resisting 5 h 700 °C annealing.