NMOS低温热载流子晶体管的解析研究

利用低温（７７－２９５Ｋ）短沟ＮＭＯＳＦＥＴ准二维解析模型，研究了７７－２９５Ｋ温区ＮＭＯＳＦＥＴ衬底电流相关的物理机制。发现沟道电子平均自由程不随温度而改变，其值约为７．６ｎｍ；低温下虽然沟道电子在漏端获得较高的能量，但由于碰撞电离减弱，使ＮＭＯＳＦＥＴ的衬底电流不随温度降低而显著增长。实验结果证明，提出的衬底电流机制和模型适用于７７－２９５Ｋ宽温区范围。     

低温NMOS器件衬底电流的测试与分析

本文测量了低温(77K)下NMOSFET的衬底电流随偏置电压V_(GS)、V_(DS)和V_(BS)的变化曲线以及衬底电流与应力作用时间的关系。并与常温(300K)下进行了比较。测量结果表明:低温(77K)下NMOSFET的衬底电流比常温(300K)下增大了一个数量级。最后,分析了电场对衬底电流的影响,讨论了低温下衬底电流增大的物理机理。     

集成电路可制造性设计中器件参数的提取

分别采用流体力学模型和漂移扩散模型对不同沟道长度的NMOSFET进行衬底电流的提取,并以NMOSFET沟道长度和LDD注入峰值综合对器件特性的影响为研究内容,介绍了集成电路可制造性设计中器件参数的优化与提取。     

SOI基栅控横向PIN蓝紫光探测器温度特性研究

通过模型构建、数值计算和软件模拟,对绝缘衬底上的硅(SOI)基栅控横向P-I-N(通用结构)蓝紫光探测器在-25～75℃的电流-电压(I-V)特性进行研究。构建温度对栅极电压影响的解析模型,通过数值计算与软件模拟,验证模型的有效性。利用SILVACO软件中的ATLAS模块对不同温度下的沟道表面电子浓度、光电流、暗电流、信噪比(SNR)等特性进行模拟仿真。结果表明,沟道表面电子浓度和暗电流随温度的升高而增大,温度对光电流的影响不明显,信噪比随温度的升高而减小,在温度T=-25℃,栅极电压为1.44V时,SNR达到最大值6.11×10~5;在T=75℃,栅极电压为2V时,SNR达到最小值为1.064×10~3。     

Temperature dependent IDS-VGS characteristics of an N-channel Si tunneling field-effect transistor with a germanium source on Si(110) substrate

在Si(110)衬底上制备了Ge源n型Si沟道隧穿场效应晶体管（TFET）。本文研究了温度对Ge源Si TFET器件的电学性能的影响。温度相关性研究显示器件漏电流主要由漏区的Shockley - Read - Hall (SRH) 产生于复合电流决定。器件开态电流随温度升高而增加,这是因为温度升高材料禁带宽度减小,隧穿几率增大。界面缺陷引起的隧穿电流的亚阈值摆幅随温度升高而变差,但是带间隧穿电流的亚阈值摆幅不随温度变化而变化。     

变温C-V和传输线模型测量研究AlGaN/GaN HEMT温度特性

通过对异质结材料上制作的肖特基结构变温C-V测量和传输线模型变温测量,研究了蓝宝石衬底AlGaN/GaN异质结高电子迁移率晶体管的直流特性在25～200℃之间的变化,分析了载流子浓度分布、沟道方块电阻、欧姆比接触电阻和缓冲层泄漏电流随温度的变化规律.得出了器件饱和电流随温度升高而下降主要由输运特性退化造成,沟道泄漏电流随温度的变化主要由栅泄漏电流引起的结论.同时,证明了GaN缓冲层漏电不是导致器件退化的主要原因.     

变温C-V和传输线模型测量研究AlGaN/GaN HEMT温度特性

通过对异质结材料上制作的肖特基结构变温C-V测量和传输线模型变温测量,研究了蓝宝石衬底AlGaN/GaN异质结高电子迁移率晶体管的直流特性在25～200℃之间的变化,分析了载流子浓度分布、沟道方块电阻、欧姆比接触电阻和缓冲层泄漏电流随温度的变化规律.得出了器件饱和电流随温度升高而下降主要由输运特性退化造成,沟道泄漏电流随温度的变化主要由栅泄漏电流引起的结论.同时,证明了GaN缓冲层漏电不是导致器件退化的主要原因.     

PD SOI NMOSFET翘曲效应的温度模型

报道了一个部分耗尽 (PD) SOI NMOSFET翘曲效应的温度解析模型 .该模型从 PD SOI NMOSFET器件的物理结构 ,即由顶部的 NMOSFET和底部的寄生 BJT构成这一特点出发 ,以一定温度下 PD SOI NMOSFET体-射结电流与漏 -体结电流的动态平衡为核心 ,采用解析迭代方法求解 ,得出漏 -体结碰撞电离产生的空穴在体区中近源端积累达到饱和时的体 -射结电压 ,及漏 -体结和体 -射结电流的各主要分量 ,进而得到了 PD SOI NMOSFET翘曲效应漏电流的温度解析模型 ,并将一定条件下的模拟结果与实验结果进行了比较 ,二者吻合得很好     

PD SOI NMOSFET翘曲效应的温度模型

报道了一个部分耗尽(PD)SOI NMOSFET翘曲效应的温度解析模型.该模型从PD SOI NMOSFET器件的物理结构,即由顶部的NMOSFET和底部的寄生BJT构成这一特点出发,以一定温度下PD SOI NMOSFET体-射结电流与漏-体结电流的动态平衡为核心,采用解析迭代方法求解,得出漏-体结碰撞电离产生的空穴在体区中近源端积累达到饱和时的体-射结电压,及漏-体结和体-射结电流的各主要分量,进而得到了PD SOI NMOSFET翘曲效应漏电流的温度解析模型,并将一定条件下的模拟结果与实验结果进行了比较,二者吻合得很好.     

应变Si调制掺杂NMOSFET电子面密度模型

应变Si(Strain Si)调制掺杂NMOSFET量子阱沟道中电子面密度直接影响器件的开关特性.本文通过求解泊松方程,建立了应变Si调制掺杂NMOSFET量子阱沟道静态电子面密度模型,并据此建立了器件阈值电压模型,利用MATLAB软件对该模型进行了数值分析.讨论了器件结构中δ-掺杂层杂质浓度和间隔层厚度与电子面密度和阈值电压的关系,分析了器件几何结构参数和材料物理参数对器件量子阱沟道静态电子面密度和阈值电压的影响.随着δ-掺杂层杂质浓度的减小和间隔层厚度的增加,量子阱沟道中电子面密度减小,阈值电压绝对值减小.     

低温NMOSFET的解析模型

利用缓变沟道近似（ＧＣＡ）及准二维分析，提出了在７７～２９５Ｋ温区工作的ＮＭＯＳＦＥＴ的解析模型。建模中不仅考虑迁移率蜕变（电场引起）、载流子速度饱和及沟道调制效应，而且计入温度相关参数的温度特性。模拟结果显示了该模型的正确性及其在低温热载流子效应中的应用潜力。     

Hole trapping during low gate bias, high drain bias hot-carrierinjection in n-MOSFETs at 77 K

Injection and trapping of holes in the gate oxide of n-channel MOS transistors during operation at large drain and small gate biases are investigated at liquid-nitrogen temperature. Experimental evidence is given that about three times less trapping of holes occurs in the gate oxide at 77 K as compared to 295 K. The authors show that this is due to the small hole mobility in SiO₂ at low temperature     

Low-Temperature Transport Characteristics and Quantum-Confinement Effects in Gate-All-Around Si-Nanowire N-MOSFET

Gate-all-around n-MOSFETs with Si-nanowire (~7 nm) as the channel body are fabricated and characterized for their low-temperature behavior (~5 K to 295 K). I_DS-V_GS characteristics at low V_DS (~50 mV) exhibit a decrease in current with decreasing temperature in strong inversion up to about ~200 K. However, at high V_DS, drain current reverts to typical temperature behavior, i.e., I_DS increases with the reducing temperature due to the increase in phonon-limited mobility (mu_ph)- It is inferred that, at low V_DS the enhancement in mu_ph at a reduced temperature could be possibly masked by the intersubband scattering on account of subband splitting due to quantum-confinement effects as indicated by subband calculations for nanowire structures.     

Characteristics of a GaAs spontaneous infrared source with 40 percent efficiency

The external quantum efficiency of a forward-biased GaAs p-n junction device selected for high efficiency measures 40.5, 32, and 7.3 percent at 20, 77, and 295°K, respectively. The optical exit path is through bulk material doped to a 10¹⁷donors/cm²level. The infrared emission is measured directly with a silicon solar cell. The effective transmissivity of the GaAs bulk device material is measured to be 42 and 8.3 percent at 77 and 295°K, respectively. The corresponding values for the internal quantum efficiency are 76 and 88 percent. The primary optical rise time measured for high level current pulsing conditions is 0.6 and 1.6 ns at 77 and 295°K, respectively.     

A 150 ns, 150 mW, 64K dynamic MOS RAM

A 64K dynamic MOS RAM organized as 16K words/spl times/4 bits has been realized by short-channel and single-level polysilicon gate technologies. The RAM uses 2 /spl mu/m effective channel length (L/SUB eff/), and 400 /spl Aring/ gate oxide film thickness (t/SUB ox/) transistors as active elements. Also, the RAM with a newly designed sense amplifier has successfully been fabricated using only four photo resist masking processes. The access time and power dissipation are 150 ns and 150 mW, respectively, at the cycle time of 400 ns.     

Hot-carrier-induced interface state generation in submicrometerreoxidized nitrided oxide transistors stressed at 77 K

The hot carrier degradation at 77 K of silicon MOSFETs fabricated with reoxidized nitrided oxide (ONO) gate dielectrics has been investigated. Measurements have been performed at both room and LN₂ temperatures on n-channel FETs for both ONO and conventional SiO ₂ films. It is found that the hot-carrier immunity of ONO transistors is substantially larger than that of conventional SiO₂ devices, and that the degree of improvement is much larger at room temperature that an 77 K. While the interface state generation does increase dramatically as a result of 77-K stressing, the dominant degradation mechanism can be attributed to a large increase in the drain resistance of the device due to localized charge trapping at the drain side of the channel     

A study of on-resistance and switching characteristics of the power MOSFET under cryogenic conditions

The decrease in on-resistance of power MOSFETs operation under cryogenic temperature leads to a considerable reduction in heat generation inside the device. An experimental measurement of on-resistances at 77K, 173K, 243K and 295K was carried out by applying cryogenic cooling techniques. The decrease in on-resistance and capacitance associated with the temperature led to an enhancement of overall time response of the MOSFETs. Another advantage associated with operating MOSFETs under cryogenic temperature is the decrease of the internal thermal resistance. The present work demonstrated that by exposing the device to cryogenic conditions, it is possible to implement high frequency, high power applications with MOSFET devices.     

N-channel enhancement-mode MOSFET characteristics from 10 to 300 K

Operation of MOSFET circuits at the liquid nitrogen temperature (77 K) has been suggested as a means of improving circuit and system performance. Previously reported work emphasizes mobility and threshold voltage at 77 K. However, small MOSFET's require several (≳10) parameters for circuit design. Since a full set of MOSFET model parameters have not been previously reported, it has not been established whether conventional models can be applied for MOSFET circuit design at 77 K. We present here the temperature dependence of a full set of MOSFET circuit model parameters for channel lengths from 2.5 to 8.5 µm and for temperatures ranging from 10 to 300 K. Temperatures below 77 K are of interest in evaluating effects of impurity freezeout and temperatures above 77 K are important since actual device temperatures will be above the ambient. Overall, we find that the mobility and the threshold voltage are the dominant temperature dependent parameters and that conventional I-V characteristics persist down to 77 K. Below 77 K, some new features appear in the I-V characteristics. However, the conventional behavior down to 77 K suggests that standard (circuit models can be used for circuits operating at 77 K. Such circuits would be about four times faster than at room temperature and, with liquid nitrogen cooling, would provide an order of magnitude higher power density for VLSI.     

Selectively doped n+ InP/n? GaInAs heterostructure prepared using chloride transport vapour-phase epitaxy

A field-effect transistor with a 2 ?m Au gate was fabricated on a selectively doped InP/GaInAs heterostructure grown using chloride transport vapour-phase epitaxy. Complete pinch-off was observed, and transconductance of 90 and 160 mS/mm were measured at 295 and 77 K, respectively. From analysis of the drain I/V characteristic, two-dimensional electron gas at the interface was revealed to be the dominant factor for the channel current. This is the first report of a successful preparation of an n+ InP/n? GaInAs heterostructure for the selectively doped field-effect transistor.     

DIBL in short-channel NMOS devices at 77 K

Detailed experimental and two-dimensional numerical simulation results on drain-induced barrier lowering (DIBL) versus channel length at 300 and 77 K in short-channel NMOS devices are presented. It is found that by decreasing the temperature from 300 to 77 K. DIBL in NMOS devices with effective channel lengths (L) from 0.5 to 2.0 μm is improved for the range of L<0.6 μm and L>1.2 μm, but is worse for L between 0.6 and 1.2 μm. The new version of the two-dimensional device numerical simulation program MINIMOS 4.0, which includes device modeling at cryogenic temperatures, was used to investigate this unique characteristic. The measured DIBL characteristics can be explained physically as the transition from surface DIBL through the subsurface DIBL to the bulk DIBL or punchthrough effect at 300 K, but almost a surface DIBL for the whole range of channel length variation at 77 K. Design considerations for the channel doping profile for low-temperature operation based on keeping the same DIBL and V_TH as required for room-temperature operation are briefly discussed