一种带斩波的双采样Σ-Δ调制器

设计了一种适用于过高磁场抗扰度的电容式隔离型全差分Σ-Δ调制器。它采用单环2阶1位量化的前馈积分器结构,运用斩波技术降低低频噪声和直流失调。与传统的全差分结构相比,该调制器的每级积分器均采用4个采样电容,在一个时钟周期内能实现两次采样与积分,所需的外部时钟频率仅为传统积分器的一半,降低了运放的压摆率及单位增益带宽的设计要求,实现了低功耗。基于CSMC 0.35 μm CMOS工艺,在5 V电源电压、10 MHz采样频率和256过采样率的条件下进行电路仿真。后仿真结果表明,调制器的SNDR为100.7 dB,THD为－104.9 dB,ENOB可达16.78位,总功耗仅为0.4 mA。     

一个过采样增量－总和调制器的设计与实现

本文设计实现了一个高精度的双通道过采样Ａ／Ｄ电路，它采用由两个二阶调制器级联实现的四阶增量－总和调制器结构，并通过优化调制器内部各级增益，在改善过采样Ａ／Ｄ的大信号过载特性的同时提高其最大输出信嗓比．为降低数字开关噪声对过采样Ａ／Ｄ性能的影响，本文采用了一种低噪声电流控制逻辑设计数字电路．实验芯片的测试结果表明，在６４倍的过采样率下，电流控制逻辑通道和静态ＣＭＯＳ逻辑通道分别获得了９１ｄＢ和８４．５ｄＢ的输出动态范围．     

功耗及信噪比双重约束下∑△模数调制器积分器优化

针对前馈级联∑△模数调制器结构,详细分析了调制器信噪比及功耗与Class-A类运算放大器构成的各级积分器等效输入噪声功率及功耗间相互关系,并在此基础上提出对于给定调制器信噪比及功耗双重约束的前馈级联∑△模数调制器各级积分器参数参考值的优化选取,包括:采样电容、开关导通电阻、输入晶体管宽长比等,从而有利于低功耗高精度∑△模数调制器设计者确定满足给定功耗和信噪比双重约束的∑△模数调制器优化设计方案,指导晶体管级电路设计,缩短设计周期.     

基于音频应用的四阶带宽可重构的Delta Sigma调制器

本文提出一种应用于音频领域的单环四阶Delta Sigma调制器,采用可重构机制以适用于两种基于带宽的模式（8kHz/16kHz）。该芯片采用SMIC 0.13μm CMOS 混合信号工艺,功耗为153.6μW,占用面积0.98*0.46mm2。该调制器在16kHz模式下,性能达到89.3dB的信噪比（SNR）和90.2dB的动态范围（DR）;在8kHz模式下,性能达到90.2dB的信噪比（SNR）和86dB的动态范围（DR）。所设计的调制器的优值（FOM）同近几年来的低压调制器比较具有很大的竞争力。     

一个双采样双延迟型开关电容谐振子的研究设计􀀂

在研究了开关电容谐振子的基础上，提出了一个新颖的高性能的双采样的双延迟式谐振子，传输函数级的分析和模拟表明该谐振子具有高的陷波Q值和精确的陷波频率。与以前报告的双延迟式谐振子进行了比较。分析了电路中非理想特性对该谐振子性能的影响并给出了模拟结果，结果表明该谐振子对电路中非理想特性不敏感，并具有好的输出按比例缩放特性，适宜用于低功耗高性能的带通sigrna Delta调制器中。     

应用过采样与噪声整形技术的sigma-delta ADC 设计

针对sigma-delta ADC高精度和高分辨率要求,本文提出了一种采用过采样和噪声整形技术的sigma-delta ADC设计方法,更大限度上提高ADC信号转换的准确精度.     

用于单片集成热真空传感器的Σ-Δ调制器设计

设计了一款适用于集成热真空传感器的二阶1位Σ-Δ调制器.该调制器采用前馈通道抑制积分器的输出摆幅、降低谐波失真、提高动态范围.为了降低运算放大器的1/f噪声,积分器中引入相关双采样电路.利用Matlab/Simulink,分析运算放大器的非理想性对调制器性能的影响.调制器由全差分开关电容电路实现.仿真结果表明:在4 MHz采样频率和6.8 kHz信号输入频率、-3 dBFS幅值下,电路的最大信噪比为86.9 dB,分辨率可达14位.调制器的有效面积为0.67 mm2.3 V电源电压供电时,功耗为12 mW,各项性能指标均满足设计要求.     

用于单片集成热真空传感器的Σ-Δ调制器设计北大核心

设计了一款适用于集成热真空传感器的二阶1位Σ-Δ调制器。该调制器采用前馈通道抑制积分器的输出摆幅、降低谐波失真、提高动态范围。为了降低运算放大器的1/f噪声,积分器中引入相关双采样电路。利用Matlab/Simulink,分析运算放大器的非理想性对调制器性能的影响。调制器由全差分开关电容电路实现。仿真结果表明:在4 MHz采样频率和6.8 kHz信号输入频率-3、dBFS幅值下,电路的最大信噪比为86.9 dB,分辨率可达14位。调制器的有效面积为0.67 mm2。3 V电源电压供电时,功耗为12 mW,各项性能指标均满足设计要求。     

Sigma-delta modulator modeling analysis and design

This paper introduces a new method for SC sigma-delta modulator modeling.It studies the integrator's different equivalent circuits in the integrating and sampling phases.This model uses the OP-AMP input pair's tail current(I_0) and overdrive voltage(v_(on)) as variables.The modulator's static and dynamic errors are analyzed.A group of optimized I_0 and v_(on) for maximum SNR and power x area ratio can be obtained through this model.As examples, a MASH21 modulator for digital audio and a second order modu...     

Sigma-delta调制器的设计和降采样原理分析

根据实际的研发过程,详细讨论了音频ADC中Sigma-delta调制器的设计过程,即调制器系数的生成方法,并且深入的研究了降采样的作用和工作原理,并在此基础上给出了降采样滤波器的具体实现方法.     

用于电池管理系统的Sigma-Delta ADC模型优化设计及研究

针对用于电池管理系统中数模转换器的高精度要求以及Sigma-Delta ADC的适用特点,提出了一种加入零点优化的单环三阶前馈调制器结构以及适用于本系统的低功耗数字滤波器模型,通过噪声传输函数设计三准则和信号频谱分析给出具体设计及仿真参数,经验证该模型达到系统所需16位有效分辨率要求且易于电路实现。     

一种用于微机械惯性传感器中的16位ΣΔ调制器

A fourth-order low-distortion low-pass sigma-delta （∑△） modulator is presented for micro-machined inertial sensors. The proposed single-loop single-bit feedback modulator is optimized with a feed-forward path to decrease the nonlinearities and power consumption. The IC is implemented in a standard 0.6 μm CMOS technology and operates at a sampling frequency of 3.846 MHz. The chip area is 2.12 mm^2 with 23 pads. The experimental results indicate a signal-to-noise ratio （SNR） of 100 dB and dynamic range （DR） of 103 dB at an oversampling rate （OSR） of 128 with the input signal amplitude of-3.88 dBFS at 9.8 kHz; the power consumption is 15 raW at a 5 V supply.     

A Multistage Closed-loop Sigma-Delta modulator (MSCL)

A new family of high order Sigma Delta modulators called MSCL (Multi Stage Closed-loop) is presented in this paper. They use a global feedback to lower the sensitivity to circuit imperfections. This feedback from the output of the modulator is the sum of the output of each comparator so that no digital prefiltering is required before summing up these signals. However, easy calibration will be required to compensate for the feedback imperfections.MSCL modulators present the same insensitivity to circuit imperfections as classical multi-order one-bit converters, but reach the performance of high-order MASH (MultistAge noise SHaping) modulators. They help make high-order low-pass or band-pass modulators without limit cycles so that their quantizing noise characteristics are similar to those predicted by the linear simplified model.     

A 16-bit cascaded sigma-delta pipeline A/D converter

A low-noise cascaded multi-bit sigma-delta pipeline analog-to-digital converter (ADC) with a low oversampling rate is presented. The architecture is composed of a 2-order 5-bit sigma-delta modulator and a cascaded 4-stage 12-bit pipelined ADC, and operates at a low 8X oversampling rate, The static and dynamic performances of the whole ADC can be improved by using dynamic element matching technique. The ADC operates at a 4 MHz clock rate and dissipates 300 mW at a 5 V/3 V analog/digital power supply. It is developed in a 0.35 μm CMOS process and achieves an SNR of 82 dB.     

改进的适用于GSM的单环过采样调制器

传统的前馈结构由于在量化器前存在复杂的加法器因而会造成性能受限。本文给出了一个改进的四阶一位过采样调制器, 它采用了简单的加法器和延时输入前馈通路,从而降低了调制器的时序需求同时实现低失真。调制器由0.35微米工艺流片,完成了92.8dB的信号噪声失真比和101dB的动态范围,信号带宽100kHz,在3.3V电源电压下,消耗8.6mW。本调制器的性能满足GSM系统的需求。     

An improved single-loop sigma-delta modulator for GSM applications

Traditional feedforward structures suffer from performance constraints caused by the complex adder before quantizer.This paper presents an improved 4th-order 1 -bit sigma-delta modulator which has a simple adder and delayed input feedforward to relax timing constraints and implement low-distortion.The modulator was fabricated in a 0.35μm CMOS process,and it achieved 92.8 dB SNDR and 101 dB DR with a signal bandwidth of 100 kHz dissipating 8.6 mW power from a 3.3-V supply.The performance satisfies the requirements of a GSM system.     

A 16-bit cascaded sigma-delta pipeline A/D converter

A low-noise cascaded multi-bit sigma-delta pipeline analog-to-digital converter （ADC） with a low over-sampling rate is presented. The architecture is composed of a 2-order 5-bit sigma-delta modulator and a cascaded 4-stage 12-bit pipelined ADC, and operates at a low 8X oversampling rate. The static and dynamic performances of the whole ADC can be improved by using dynamic element matching technique. The ADC operates at a 4 MHz clock rate and dissipates 300 mW at a 5 V/3 V analog/digital power supply. It is developed in a 0.35μm CMOS process and achieves an SNR of 82 dB.     

Design of a high-order single-loop ∑△ ADC followed by a decimator in 0.18 μm CMOS technology

This work presents an oversampled high-order single-loop single-bit sigma-delta analog-to-digital con verter followed by a multi-stage decimation filter. Design details and measurement results for the whole chip are presented for a TSMC 0.18 μm CMOS implementation to achieve virtually ideal 16-b performance over a baseband of 640 kHz. The modulator in this work is a fully differential circuit that operates from a single 1.8 V power supply. With an oversampling ratio of 64 and a clock rate of 81.92 MHz, the modulator achieves a 94 dB dynamic range. The decimator achieves a pass-band ripple of less than 0.01 dB, a stop-band attenuation of 80 dB and a transition band from 640 to 740 kHz. The whole chip consumes only 56 mW for a 1.28 MHz output rate and occupies a die area of 1×2 mm~2.