Single event double node upset tolerance in MOS/spintronic sequential and combinational logic circuits

Spin-transfer torque random access memory (STT-RAM) is an emerging storage technology that is considered widely thanks to its attractive features such as low power consumption, nonvolatility, scalability and high density. STT-RAMs are comprised of a hybrid design of CMOS and spintronic units. Magnetic tunnel junction (MTJ) as the basic element of such hybrid technology is inherently robust against radiation induced faults. However, the peripheral CMOS component for sensing the resistance of the MTJs are prone to be affected by energetic particles. This paper proposes low power, nonvolatile and radiation hardened latch and lookup table circuits based on hybrid CMOS/MTJ technology for the next generation integrated circuit devices. Simulation results revealed that, the proposed circuits are fully robust against single event upsets (SEU) and also single event double node upsets (SEDU) that are of the main reliability challenging issues in current sub-nanometer CMOS technologies.     

Partial evaluation based triple modular redundancy for single event upset mitigation

We present a design technique, Partial evaluation-based Triple Modular Redundancy (PTMR), for hardening combinational circuits against Single Event Upsets (SEU). The basic ideas of partial redundancy and temporal TMR are used together to harden the circuit against SEUs. The concept of partial redundancy is used to eliminate the gates whose outputs can be determined in advance. We have designed a fault insertion simulator to evaluate partial redundancy technique on the designs from MCNC′91 benchmark. Experimental results demonstrate that we can reduce the area overhead by up to 39.18% and on average 17.23% of the hardened circuit when compared with the traditional TMR. For circuits with a large number of gates and less number of outputs, there is a significant savings in area. Smaller circuits or circuits with a large number of outputs also show improvement in area savings for increased rounding range.     

Single event upset and total dose radiation effects on rad-hard SRAMs

Radiation hardened 16K and 64K CMOS SRAMs were tested at the Brookhaven SEU Test Facility. No failures of 16K SRAMs were observed at room temperature with any value of the feedback resistors. SEU cross section measured at elevated temperatures was a function of reduced feedback resistance. A difference was observed in critical LET forBr andAu ions. SEU cross section decreased at very high angles of incidence. After initial SEU testing, the 64K SRAM was degraded by proton total dose irradiation. An increase in the SEU cross section as well as imprinting of the memory pattern was observed. Test chips fabricated by the same technology were also submitted to proton radiation. Threshold voltage shift was measured for NMOS transistors with and without inversion bias. An increase in the density of interface states for both NMOS and PMOS transistors was measured by the charge-pumping technique. This research has been supported by the NASA grants NAG-5-929 and NAG-9-333.     

Single event soft error in advanced integrated circuit

As technology feature sizes decrease, single event upset (SEU), and single event transient (SET) dominate the radiation response of microcircuits. Multiple bit upset (MBU) (or multi cell upset) effects, digital single event transient (DSET) and analogue single event transient (ASET) caused serious problems for advanced integrated circuits (ICs) applied in a radiation environment and have become a pressing issue. To face this challenge, a lot of work has been put into the single event soft error mechanism and mitigation schemes. This paper presents a review of SEU and SET, including: a brief historical overview, which summarizes the historical development of the SEU and SET study since their first observation in the 1970's; effects prominent in advanced technology, which reviews the effects such as MBU, MSET as well as SET broadening and quenching with the influence of temperature, device structure etc.; the present understanding of single event soft error mechanisms, which review the basic mechanism of single event generation including various component of charge collection; and a discussion of various SEU and SET mitigation schemes divided as circuit hardening and layout hardening that could help the designer meet his goals.     

原始状态在时序逻辑电路设计中的应用研究

原始状态的确定对于时序逻辑电路的设计而言十分重要,本文通过对设计实例设计过程中原始状态的分析和确定,完善了时序逻辑电路的设计步骤,使时序逻辑电路的设计思路更加清晰。     

静电放电模拟器电路建模分析

从实际的静电放电模拟器结构出发,根据接触放电时静电放电电流的主要特征,考虑到静电模拟器本身、连接线及回路电缆与地平面间产生的分布参数的影响,建立了一个新的静电放电模拟器等效电路模型,并用PSPICE软件对等效电路进行模拟分析,得到了与实测波形基本一致的电流波形.利用该模型讨论了各分布参数对放电电流的影响.结果表明:模拟器体电阻与地间的电感对电流波形影响不大,因此可以忽略,但其与地之间的分布电容对电流波形的低频段有重要影响;连接线分布参数对电流波形的第一峰值及波形光滑度都有影响;回路电缆分布参数主要影响了电流波形中第二个波峰峰值及其位置.     

Improvement of a resonant-transfer circuit by means of a compensating reactance

The effective loss Ae of a resonant-transfer circuit containing two lowpass filters and a resonant-transfer switch can be reduced in the passband by inserting a compensating reactance. For a particular circuit, the compensating reactance has been designed and the reduction of Ae has been measured.     

温度对SRAM器件单粒子翻转重离子测试的影响

本文基于单粒子效应地面重离子模拟实验,选取体硅SRAM与SOI SRAM两种待测器件,在兰州重离子加速器上（HIRLF）研究了温度对单粒子翻转测试的影响。用12C粒子对体硅SRAM器件的温度实验显示,单粒子翻转截面易受温度的影响。对于SOI SRAM器件,12C粒子测得的单粒子翻转截面随温度升高有显著的增大,但209Bi 粒子测得的单粒子翻转截面却随温度保持恒定。用Monte Carlo的方法分析了温度对单粒子翻转测试的影响规律,发现在单粒子翻转阈值LET附近温度对单粒子翻转截面有大的影响,但是随着单粒子翻转的发生接近于饱和,单粒子翻转截面渐渐的表现出低的温度依赖性。基于该模拟结果,我们对实验数据进行了分析,同时提出了一种准确评估在轨翻转率的合理方法。     

基于量子线路逻辑运算的单光子量子态测量方案

在量子探测领域,关键任务之一就是要对未知量子态进行测量以获取量子态信息。通过将量子计算中的量子门所组成的量子线路应用于量子探测领域,提出实现单光子未知量子态的测量方案。利用量子计算的叠加性、纠缠性、可纠错性以及量子线路的可集成性,可以使得探测更具高效性并简化探测的实验系统。利用本文提出的探测新方案,通过仿真计算对该方案进行了模拟。在该方案的理论计算与仿真模拟结果的基础上,得到了以下的结论:通过在不同信噪比等参数的条件下选择适当的测量次数,基于量子线路的方案可以得到较为精确的测量结果。     

一种单粒子效应加固输入接口电路的设计

提出一种新颖的单粒子效应加固输入接口电路,采用组合逻辑延迟后运算处理的方案。该电路基于华润上华600 V BCD 0.8 μm工艺进行电路设计和流片,并在中科院国家空间科学中心完成单粒子辐照测试。仿真测试结果表明,提出的输入接口电路可以有效免疫线性能量传递值(LET)在80 MeV·cm2/mg以下单粒子翻转(SEU)事件,特别是对多个节点同时发生单粒子翻转事件的情况,提出的电路抗单粒子翻转可靠性较高。     

Single event transient effects in a voltage reference

The Single Event Transient response of the LM236 band gap voltage reference from Texas Instruments is analyzed through heavy ion experiments and simulation. The LM236 circuit calibration was performed using generic transistor parameters that were subsequently optimized using device and circuit simulations. This technique avoids the requirement for performing detailed device-level parameter extraction and simplifies the SET methodology for circuit calibration.     

卫星光通信系统中单粒子翻转计算方法研究

高能带电粒子造成的单粒子翻转是影响卫星光通信系统性能的重要因素,给出了单粒子翻转的物理机制及主要研究方法。利用OMERE 3.4软件对星载CMOS 2164器件进行了单粒子翻转率计算,结果表明,通过对轨道倾角和轨道高度的优化设计可以有效减小卫星光通信系统中电子器件的单粒子翻转率。为了有效克服单粒子辐射效应,除了简单的增加屏蔽层厚度等防护方法外,还应考虑通过电子器件的选择来提高抗辐射性能。     

Synthesis of synchronous sequential machines by means of given memory elements

A systematic method for the synthesis of sequential machines by means of given memory elements is described. This method, presented here using J?K master-slave flip-flops, allows a straightforward synthesis from the transition table or the transition diagram. Examination of the table or diagram leads directly to the Boolean equations of J and K inputs without using any intermediate step.     

Interference mitigation in WSN by means of directional antennas and duty cycle control

Network spanning algorithms, such as ZigBee‐native and Stojmenovič, constitute a crucial element in the wireless sensor network design, by determining its potential for reliability and fault‐tolerance. The interconnections between nodes have a great impact on the radio interference level present in such a network and may create a serious electromagnetic compatibility issue in some cases. It can be proved that the total interference incurred by a statistical node can be diminished in two ways: either by using directional antennas or by setting an upper limit on the duty cycle of each network node. Copyright © 2010 John Wiley & Sons, Ltd.     

An optimization of a non-volatile latch using memristors for sequential circuit applications

Analog Integrated Circuits and Signal Processing - The next generation of non-volatile memory elements have been attracting significant attention for future emerging memory applications in recent...     

浅谈线路调试中的现代手段

信息时代的到来推动了我国电子产业的发展,电子产品的发展必将离不开线路调试工作,电路的调试在实际的运行中占据着十分重要的地位。一般情况下电子电路的调试需要达到预定的指标,而每一部分都需要拥有详细而有序的电路调试方式。本文笔者将会针对线路调试的准备工作进行简单的分析,并对电源调试和调试方法及步骤等内容进行具体的阐述。     

时变源作用下介观ＬＣ电路系统量子态的演化

采用Wei-Norman方法,求出含时变电压源的介观LC电路随时间演化的精确解,应用wigner函数研究了时变电源作用下介观LC电路相干态的量子特性,结果表明wigner函数是一个二维运动的Gauss波包。研究了时变电源在不同频率的正弦信号对系统量子态的影响,结果表明,当所加正弦信号的频率远离共振频率信号时,对介观LC电路没有影响;当所加信号的频率为共振频率时,系统由低能态向高能跃迁,使处于高能态的几率增大;研究了输入电压源为单矩形脉冲的特例。     

时变源作用下介观LC电路系统量子态的演化

采用代数动力学规范变换方法,求出含时变电压源的介观LC电路量子态随时间演化算符的精确解,研究含时变电压源的介观LC电路量子态的相干特性.结果表明,电路中电容器储电量q的几率是一个运动的Gauss波包,导出波包中心电量与外电源的一般关系.研究了输入电压源为单矩形脉冲电压的特例.     

倒装SRAM型FPGA单粒子效应防护设计验证

在倒装芯片的单粒子效应防护设计验证中,重离子在到达器件敏感区前要经过几百微米的衬底材料,需要计算器件敏感区中离子的线性能量传输(LET)值。采用兰州重离子加速器加速的55 MeV/μ58Ni离子对基于倒装的Xilinx公司550万门现场可编程门阵列(FPGA)实现的典型系统的单粒子效应防护设计进行了试验验证,采用SRIM、FLUKA和GEANT等不同方法对试验中的LET值进行了分析,同时将SRIM分析的典型结果与基于磁偏转飞行时间法的试验数据进行了比较,发现与现有的重离子分析结果有一定差异。因此在防护验证中采用离子LET作为主要参数的情况下,应对重离子(尤其是高能段)的LET的计算方法进行约定,以规范试验过程,增强数据的可比性。