Total ionizing dose effect in 0.2 μm PDSOI NMOSFETs with shallow trench isolation

This paper presents the total ionizing dose radiation performance of 0.2 μm PDSOI NMOS devices under different bias conditions. The hump effect is observed in the transfer characteristic of the back gate device instead of the front gate device after radiation. A STI bottom corner parasitic transistor model is proposed to explain this phenomenon. It also provides a simple way to extract the effective sheet charge density along the STI sidewall. Three-dimensional simulation was applied to explain the radiation effect. It shows that charge trapped in the shallow trench isolation, particularly at the bottom region of the trench oxide where the STI and the BOX are connected, is the dominant contributor to the off-state drain-to-source leakage current. The dimension of the transistor plays an important role on influencing the device’s performance after radiation. Larger off-state leakage current and radiation induced threshold voltage shift are reported in the narrow channel device than in the wide channel one. Different TID responses due to the STI process variation are also discussed.     

Influences of silicon-rich shallow trench isolation on total ionizing dose hardening and gate oxide integrity in a 130 nm partially depleted SOI CMOS technology

The influences of silicon-rich shallow trench isolation (STI) on total ionizing dose (TID) hardening and gate oxide integrity (GOI) in a 130 nm partially depleted silicon-on-insulator (SOI) complementary metal-oxide semiconductor (CMOS) technology are investigated. Radiation-induced charges buildup in STI oxide can invert the parasitic sidewall channel of the n-channel transistor, which will increase the off-state leakage current and decrease the threshold voltage for the main transistor. Compared with the general STI process, the silicon-rich STI process can significantly suppress the increase in leakage current and negative shifts in subthreshold region induced by the total dose radiation, implying TID hardening for STI trench oxide. However, the silicon-rich STI process has a deleterious impact on GOI. It leads to the thin gate oxide thickness at trench corner and lowers the gate oxide breakdown voltage. Issues of gate oxide integrity induced by silicon-rich STI are investigated in this paper, and an optimized process to solve this problem is proposed and examined. Finally, the TID response of the optimized silicon-rich STI process is presented in comparison to the general and silicon-rich STI processes.     

Gate length dependence of the shallow trench isolation leakage current in an irradiated deep submicron NMOSFET

The effects of gamma irradiation on the shallow trench isolation(STI)leakage currents in a 0.18μm technology are investigated.NMOSFETs with different gate lengths are irradiated at several dose levels.The threshold voltage shift is negligible in all of the devices due to the very thin oxide thickness.However,an increase in the off-state leakage current is observed for all of the devices.We believe that the leakage is induced by the drain-to-source leakage path along the STI sidewall,which is formed by the positive trapped charge in the STI oxide.Also, we found that the leakage is dependent on the device’s gate length.The three-transistor model(one main transistor with two parasitic transistors)can provide us with a brief understanding of the dependence on gate length.     

超深亚微米SOI总剂量效应泄漏电流模型

总剂量辐射效应会导致绝缘体上硅金属氧化物半导体场效应晶体管(SOI MOSFET)器件的阈值电压漂移、泄漏电流增大等退化特性。浅沟槽隔离(STI)漏电是器件退化的主要因素,会形成漏极到源极的寄生晶体管。针对130 nm部分耗尽(PD) SOI NMOSFET器件的总剂量辐射退化特性,建立了一个包含总剂量辐射效应的通用模拟电路仿真器(SPICE)模型。在BSIM SOI标准工艺集约模型的基础上,增加了STI寄生晶体管泄漏电流模型,并考虑了辐射陷阱电荷引起寄生晶体管的等效栅宽和栅氧厚度的变化。通过与不同漏压下、不同宽长比的器件退化特性的实验结果对比,该模型能够准确反映器件辐射前后的漏电流特性变化,为器件的抗辐射设计提供参考依据。     

Novel cell transistor using retractedSi3N4-liner STI for the improvement of dataretention time in gigabit density DRAM and beyond

In this paper, we propose a novel cell transistor using retracted Si₃N₄-liner STI (shallow trench isolation) for the enhanced and reliable operation of 256-Mb dynamic random access memory (DRAM) in 0.15-μm technology. As the technology of DRAM has been developed into the sub-quarter-micron regime, the control of junction leakage current at the storage node is much more important due to the increased channel doping concentration. With the decreased parasitic electric field at the STI corner using the retracted Si₃N₄-liner, the inverse narrow width effect (INWE) was significantly reduced. The channel doping concentration, hence, was lowered without degrading the subthreshold leakage characteristics and the channel doping profile was optimized from the viewpoint of the electric field at local areas in the depletion region. In addition to the optimized channel doping profile resulted in a dramatic increase in data retention time and device yield for 256-Mb DRAM. The proposed cell transistor can be extended to future high-density DRAMs in 0.13-μm technology and beyond     

1.2kV SiC MOSFET器件URS应力退化机理研究

本文首次研究了1.2kV碳化硅(Silicon Carbide,SiC)MOSFET在非钳位重复应力(Unclamped Repetitive Stress,URS)应力下的退化现象,并通过软件仿真和电荷泵测试技术对该现象进行了深入的分析.研究结果表明:URS应力会使得器件积累区由于碰撞电离产生大量的电子空穴对,其中的热空穴将在电场的作用下注入到氧化层中,使氧化层中出现许多空间正电荷,这些空间正电荷的存在使得器件的导通电阻与阈值电压出现下降,关态漏电流出现上升.     

Total ionizing dose effects in shallow trench isolation oxides

The peaked evolution of leakage current with total ionizing dose observed in transistors in 130 nm generation technologies is studied with field oxide field effect transistors (FOXFETs) that use the shallow trench isolation as gate oxide. The overall radiation response of these structures is determined by the balance between positive charge trapped in the bulk of the oxide and negative charge in defect centers at its interface with the silicon substrate. That these are mostly interface traps and not border traps is demonstrated through dynamic transconductance and variable-frequency charge-pumping measurements. These interface traps, whose formation is only marginally sensitive to the bias polarity across the oxide, have been observed to anneal at temperatures as low as 80 °C. At moderate or low dose rate, the buildup of interface traps more than offsets the increase in field oxide leakage due to oxide-trap charge. Consequences of these observations for circuit reliability are discussed.     

Enhanced I ON/I OFF in ultra deep submicron CMOS devices using grooved nMOSFETs in comparison to planar nMOSFET

To manage the increasing static leakage in low power applications and reducing ON‐OFF current ratio due to scaling limitations, solutions for leakage reduction as well as improving the current drive of the device are sought at the device design and process technology levels. At the device design level, the important low power variables are the threshold voltage, the gate leakage current, the subthreshold leakage current and the device size. Grooved‐gate MOS devices are considered as the most promising candidates for use in submicron and deep submicron regions as they can overcome the short‐channel effects effectively. By varying the corner angle and adjusting other structural parameters such as junction depth, channel doping concentration, negative junction depth and oxide thickness, leakage current in nMOS devices can be minimised. In this article, 90, 80, 70, 60 and 50?nm devices are simulated using Devedit and Deckbuild module of Silvaco device simulator. The simulated results show that by changing the structural parameters, ON‐OFF current ratio is improved and maintained constant even in the deep submicron region. This study can be helpful for low power applications as the static leakage is drastically reduced, as well as applicable to high speed devices as the ON current is maintained at a constant value. The results are compared with those of corresponding conventional planar devices to bring out the achievements of this study.     

总剂量辐照对65 nm NMOSFET热载流子敏感参数的影响

为了研究总剂量辐射对纳米MOS晶体管热载流子效应的影响,对65 nm 体硅工艺的NMOS器件进行了总剂量辐射和热载流子试验,对比了辐射前后不同宽长比器件的跨导、栅极泄漏电流、线性饱和电流等电参数。结果表明,MOS器件的沟道宽度越窄,热载流子效应受辐射的影响越显著,总剂量辐射后热载流子效应对器件的损伤增强。分析认为,辐射在STI中引入的陷阱电荷是导致以上现象的主要原因。该研究结果为辐射环境下器件的可靠性评估提供了依据。     

Drain voltage limitations of MOS transistors

A comprehensive investigation has been carried out into the factors which influence the maximum drain voltage of an M.O.S. transistor for normal pentode-like operation. The drain voltage is limited by two principal mechanisms, namely punch-through of the drain depletion region to the source, and breakdown, due to impact ionization in the high field region at the drain edge. A two-dimensional analysis technique for determining the drain voltage at the onset of either punch-through or avalanche breakdown, from a solution of Poisson's equation within the substrate depletion region, is described. The solutions are obtained using finite difference numerical methods which take into account the gate-induced potential profiles at the edge of the source and drain junctions. Boundary conditions of zero effective gate bias and channel current are imposed which simplify the solution of Poisson's equation to an electrostatic one. The punch-through voltage V_PT is defined as the drain-to-source voltage at which the longitudinal field at any point along the edge of the source region inverts in sign to permit the drift of minority carriers from source to drain. Breakdown voltage, V_BD, however, is determined by the drain voltage at which the maximum field in the device reaches the critical value for avalanche multiplication. Good agreement is achieved between theoretical and practical results for both mechanisms on a wide variety of devices. It is shown that V_PT decreases as the channel length and substrate doping concentration decrease and as the oxide thickness and diffusion depth increase. V_BD, however, decreases as the channel length, oxide thickness and diffusion depth decrease.Punch-through and breakdown are discussed for gate bias conditions above and below threshold. The sharp fall in breakdown voltage as the gate bias rises above threshold is explained on the basis of injected charge from the channel into the drain depletion region.     

Elimination of surface state induced edge transistors in high voltage NMOSFETs for flash memory devices

The abnormal leakage failure in high voltage NMOSFETs is investigated by measuring the subthreshold hump characteristics. Gated diode, width and substrate bias dependence of the I_D-V_GS characteristics, and two-terminal I-V measurements between the source and the drain reveal that the hump characteristic is caused by the surface states, not by the gate field crowding at STI edges. The numerical calculation shows that the high voltage NMOSFETs are very delicate to leakage failure by a small amount of surface state (10¹¹ /cm²), due to the thick gate oxide and very low doping concentration for high voltage operation (>25 V). A thermal oxidation with the thickness of 1.0 nm successfully eliminates the parasitic corner transistors without changing electrical characteristics of the targeted transistors in current state of the art flash memory devices.     

Avalanche punch-through erase (APTE) mode in dual-dielectric charge-storage (DDC) cells

The erase of multilayer charge-storage memory cells by a reverse-bias pulsing of source and drain with the gate and substrate grounded has been previously suggested. Here the physical mechanisms behind this erase mode are explored. It is shown that both punch-through and avalanche are necessary for its operation. This avalanche punch-through erase (APTE) succeeds by pumping majority carriers into a potential pocket at the interface, thereby raising the interface surface potential to a level high enough to allow the stored charge to tunnel out. It is found experimentally that APTE is strongly affected by the lateral leakage of carriers from the pocket. Theoretical curves are presented which show how the pocket itself is affected by the cell geometry, doping level, and pulse amplitude. It appears that APTE is particularly suitable for reprogrammable read-often memories (REPROM's) using dual-dielectric memory cells (DDC/s) with interfacial dopant. These cells allow the use of a gate inhibit voltage pulse which is shown to increase the effectiveness of the APTE, making it a practical approach for random-access REPROM integrated circuits.     

Electrical testing for process evaluations

MOS LSI process evaluation techniques based on electrical measurements are presented. Important processing parameters, such as gate length, gate oxide thickness, junction depth and channel doping which determine major device characteristics, e.g. threshold voltage and gain factor, are evaluated by electrical measurements, and compared with those measured by optical or in-process monitoring methods. Good agreement between these results indicates the effectiveness of this electrical evaluation technique. According to the analysis, threshold voltage variations across the wafer are primarily due to variations in gate oxide thickness, while anomalous threshold voltage reduction in the short channel region is attributed to MOSFET punch-through.     

Hot-carrier-stress effects on gate-induced drain leakage current inn-channel MOSFETs

The effects of hot-carrier stress on gate-induced drain leakage (GIDL) current in n-channel MOSFETs with thin gate oxides are studied. It is found that the effects of generated interface traps (ΔD _it) and oxide trapped charge on the GIDL current enhancement are very different. Specifically, it is shown that the oxide trapped charge only shifts the flat-band voltage, unlike ΔD _it. Besides band-to-band (B-B) tunneling, ΔD _it introduces an additional trap-assisted leakage current component. Evidence for this extra component is provided by hole injection. While trapped-charge induced leakage current can be eliminated by a hole injection subsequent to stress, such injection does not suppress interface-trap-induced leakage current     

GaN HBT: toward an RF device

This paper reviews efforts to develop growth and fabrication technology for the GaN HBT. Conventional devices are grown by plasma assisted MBE on MOCVD GaN templates on sapphire. HBTs were fabricated on LEO material identifying threading dislocations as the primary source of collector-emitter leakage which was reduced by four orders of magnitude for devices on nondislocated material. Base doping studies show that the mechanism of this leakage is localized punch-through caused by compensation near the dislocation. High contact and lateral resistance in the base cause large parasitic common emitter offset voltages (from 1 to 5 V) in GaN HBTs. The effect of this voltage drop on common emitter characteristics is discussed. The combination of this voltage drop and the emitter collector leakage make Gummel and common base characteristics unreliable without verification with common emitter characteristics. The selectively regrown emitter bipolar transistor is presented with a DC current gain of 6 and early voltage greater than 400 V. The transistor operated to voltages over 70 V. This device design reduces base contact resistance, and circumvented difficulties associated with the emitter mesa etch process. The Mg memory effect in MOCVD grown GaN HBTs is discussed, and MBE grown device layers are shown to produce sharp doping profiles. The low current gain of these devices is discussed, and an HBT with a compositionally graded base is presented, as well as simulations predicting further current gain improvements with base grading     

Positive oxide charge-enhanced read disturb in a localized trapping storage flash memory cell

Read disturb-induced erase-state threshold voltage instability in a localized trapping storage Flash memory cell with a poly-silicon-oxide-nitride-oxide-silicon (SONOS) structure is investigated and reported. Our results show that positive trapped charge in bottom oxide generated during program/erase (P/E) cycles play a major role. Both gate voltage and drain voltage will accelerate the threshold voltage (V/sub t/) drift. Hot-carrier caused disturb effect is more severe in a shorter gate length device at low temperature. A model of positive charge-assisted electron tunneling into a trapping nitride is proposed. Influence of channel doping on the V/sub t/ drift is studied. As the cell is in an "unbiased" storage mode, tunnel detrapping of positive oxide charges is responsible for the threshold voltage shift, which is insensitive to temperature.     

NPB/Alq3双层有机电致发光器件薄膜厚度与器件性能的优化

研究了以NPB为空穴传输层、Alq₃为发光层的双层异质结有机电致发光器件的薄膜厚度对器件性能的影响.制备了一系列具有不同NPB和Alq₃厚度的器件并测试了其电致发光特性.结果表明,器件电流随Alq₃与NPB厚度变化的关系并不相同.不同有机层厚度双层器件的电流机制符合陷阱电荷限制(TCL)理论,随外加电压的增大,器件电流经历了欧姆电导区、TCL电流区、陷阱电荷限制-空间电荷限制(TCL-SCL)过渡区三个区域的变化.当有机层厚度匹配为NPB(20nm)/Alq₃(50nm)时可以获得性能优良的器件.器件的流明效率-电压关系曲线的变化规律是在低电压区较快达到最大值,然后随电压的增加逐渐降低.     

Analysis of the DCIV peaks in electrically stressed pMOSFETs

This paper presents the effects of Fowler-Nordheim (FN) and hot-carrier (HC) stress in the direct-current current voltage (DCIV) measurements. The effect of interface trapped charge on DCIV curves is reported. Stress-induced oxide charge shifts the DCIV peaks, while stress-induced interface trapped charge causes a spread in the DCIV peaks. It is found that under HC stress, when the absolute value of stress gate voltage changes from low to high, the interface trap spatial location moves from the drain region to the channel region. It is inferred that the generation of oxide charge in the drain region is a two-step process. For short stress times, electrons mainly fill the process-induced neutral oxide traps, while for long stress times, electrons fill the stress created electron traps     

Radiation induced transconductance overshoot in the 130 nm partially-depleted SOI MOSFETs

This paper presents the total ionizing dose (TID) radiation performances of core and input/output (I/O) MOSFETs from 130 nm partially-depleted silicon-on-insulator (PDSOI). Both the core NMOS and PMOS are totally hardened to 1.5 Mrad(Si), while the I/O devices are still sensitive to TID effect. The worst performance degradation is observed in I/O PMOS which is manifested as significant front gate threshold voltage shift and transconductance decrease. Contrary to PMOS, front gate transconductance overshoot is observed in short channel I/O NMOS after irradiation. A radiation induced localized damage model is proposed to explain this anomalous phenomenon. According to this model, the increments of transconductance depend on the extension distance and trapped charge density of the localized damage region in gate oxide. More trapped charge lead to more transconductance increase. These conclusions are also verified by the TCAD simulations. Furthermore, the model presents a way to extract the trapped charge density in the localized damage region.     

Bias dependence of TID induced single transistor latch for 0.13 μm partially depleted SOI input/output NMOSFETs

In this work, single transistor latch effects induced by total dose irradiation for 0.13 μm partially depleted silicon-on-insulator (PDSOI) n-type metal-oxide-semiconductor field effect transistors (NMOSFETs) were investigated. The front gate transfer characteristics under different bias configurations with forward and reverse gate voltage sweep are characterized to evaluate the latch phenomenon. The results indicate that transmission–gate (TG) bias is the worst case bias for total dose induced latch, and the onset drain voltage required for latchup degrades as the irradiation level increased. Experiments and 2D simulations are performed to analyze the positive trapped charge in the buried oxide (BOX) and its impact on the latch effect. It is demonstrated that the irradiation can enhance the impact ionization and thereby make the device more sensitive to latchup, especially at negative gate voltage. Moreover, the radiation induced coupling effect between the front gate and back gate can make the PDSOI devices in our experiments behave like the fully depleted (FD) ones.