Analytical modeling of flicker and thermal noise in n-channel DG FinFETs

A compact physics-based thermal and flicker noise model has been developed for n-channel Double Gate FinFETs with varying structural parameters. The effects of mobility degradation due to velocity saturation, carrier heating and channel length modulation have been incorporated for an accurate modeling of noise. The mobility fluctuations dependent on the inversion carrier density have been considered and a characteristic of the flicker noise different from that of Bulk MOSFETs was observed. This has been validated by the experimental results. Based on the proposed thermal and flicker noise model, a compact expression of the corner frequency has been derived and the effects of the structural parameters such as the length and the thickness of the channel have been analyzed. Finally, the model has been applied for p-channel devices and noise behavior in accordance with experimental data has been obtained.     

Comparison of characteristics of n-channel and p-channel MOSFET's for VLSI's

A comparison of device characteristics of n-channel and p-channel MOSFET's is made from the overall viewpoint of VLSI construction. Hot-carrier-related device degradation of device reliability, as well as effective mobility, is elaborately measured for devices having effective channel lengths of 0.5-5 µm. From these experiments, it is found that hot-electron injection due to impact ionization at the drain, rather than "lucky hot holes," imposes a new constraint on submicrometer p-channel device design, though p-channel devices have been reported to have much less trouble with hot-carrier effects than n-channel devices do. Additionally, p-channel devices are found to surpass n-channel devices in device reliability in that they have a highest applicable voltage BVDCthat is more than two times as high as for n-channel devices. It is also experimentally confirmed that the effective hole mobility approaches the effective electron mobility when effective channel lengthL_{eff} < 0.5µm. These significant characteristics of p-channel devices imply that p-channel devices have important advantages over n-channel devices for realization of sophisitcated VLSI's with submicrometer dimensions. It is also shown that hot holes, which may create surface states or trap centers, play an important role in such hot-carrier-induced device degradation as transconductance degradation.     

Determination of interface-state density and mobility ratio in silicon surface inversion layers

A method has been proposed to deduce the energy distribution of interface states and the mobility ratio of carriers simultaneously from Hall effect measurements at two different temperatures. Using this method, the interface-state density Nssand the mobility ratiorof carriers were determined on both n-channel and p-channel silicon MOS transistors. The result indicates that Nssdetermined in this method is very small near the center of the energy gap and increases as the energy of the states approaches the band edges. The interface-state density inside the conduction and the valence band was found as high as 10¹³cm^-2eV^-1. The value of mobility ratio was found to depend both on temperature and surface-carrier density. Increase of mobility ratio with decreasing carrier density was observed in all samples, it is interpreted as due to diffuse scattering and to Coulomb scattering by localized interface charges.     

Drain current thermal noise modeling for deep submicron n- and p-channel MOSFETs

The drain current thermal noise has been measured and modeled for the short-channel devices fabricated with a standard 0.18 μm CMOS technology. We have derived a physics-based drain current thermal noise model for short-channel MOSFETs, which takes into account the velocity saturation effect and the carrier heating effect in gradual channel region. As a result, it is found that the well-known Q_inv/L²––formula, previously derived for long-channel, remains valid for even short-channel. The model excellently explained the carefully measured drain thermal noise for the entire V_GS and V_DS bias regions, not only in the n-channel, but also in the p-channel MOSFETs. Large excess noise, which was reported earlier in some other groups, was not observed in both the n-channel and the p-channel devices.     

Low 1/f noise design of Hi-CMOS devices

Low-frequency noise characteristics of High-Performance CMOS(Hi-CMOS) devices were measured. It was found that the equivalent input noise power SVg,eqfor n-channel MOSFET's has a 1/fα spectrum (0.8 < α < 0.95) above 10 µA, even for sealed-down devices with channel lengths LGof 2 µm. The SVg,eqis clearly proportional to 1/Leffdown to 0.8 µm. The noise characteristics of p-channel and n-channel MOSFET's were compared. It was found that in Hi-CMOS devices, noise reduction in normally-off-type p-channel devices was obtained by light boron-ion implantations at doses below 10¹²cm^-2. The 1/f noise level of p-channel devices was reduced to 1/10- 1/20 that of n-channel devices. In n-channel devices, the low-frequency noise power is a slow increasing function of the drain current. In p-channel devices, on the other hand, a threshold current was observed at which the noise begins to increase rapidly. The results are discussed in this paper in relation to the theoretical model of 1/f noise. The device design for reducing 1/f noise in CMOS differential amplifiers is also examined.     

SiGe沟道SOI CMOS的设计及模拟

在 SOI(Silicon on Insulator)结构硅膜上面生长一层 Si Ge合金 ,采用类似 SOICMOS工艺制作成具有Si Ge沟道的 SOICMOS集成电路。该电路不仅具有 SOICMOS电路的优点 ,而且因为 Si Ge中的载流子迁移率明显高于 Si中载流子的迁移率 ,所以提高了电路的速度和驱动能力。另外由于两种极性的 SOI MOSFET都采用 Si Ge沟道 ,就避免了只有 SOIPMOSFET采用 Si Ge沟道带来的选择性生长 Si Ge层的麻烦。采用二维工艺模拟得到了器件的结构 ,并以此结构参数进行了器件模拟。模拟结果表明 ,N沟和 P沟两种 MOSFET的驱动电流都有所增加 ,PMOSFET增加得更多一些     

Flicker noise in CMOS transistors from subthreshold to stronginversion at various temperatures

Flicker noise is the dominant noise source in silicon MOSFET's. Even though considerable amount of work has been done in investigating the noise mechanism, controversy still exists as to the noise origin. In this paper, a systematic study of flicker noise in CMOS transistors from twelve different fabricators is reported under various bias conditions corresponding to the gate voltage changing from subthreshold to strong inversion, and the drain voltage changing from linear to saturation regions of operation. The measurement temperature was varied from room temperature down to 5 K. Experimental results consistently suggest that 1/f noise in n-channel devices is dominated by carrier-density fluctuation while in p-channel devices the noise is mainly due to mobility fluctuation     

IGFET circuit performance-n-channel versus p-channel

The n-channel insulated-gate field-effect transistor offers a factor of 2 to 3.4 mobility advantage (depending on crystal orientation and substrate doping level) over p-channel devices. In addition, several advantages result from the fact that the work function difference between an aluminum gate and the silicon substrate is about -0.8 volt for a p substrate compared with about zero for an n substrate. In particular, this results in a low threshold voltage that allows the use of a substrate bias to adjust the threshold voltage over a useful design range resulting in an added flexibility in choice of thresholds and substrate doping, a reduction in the effect of source-substrate bias on device threshold, decreased junction capacitance, and larger parasitic thick-oxide thresholds for a given insulator thickness. The speed, power, and density advantages of the n-channel device are illustrated for logic and memory circuits using representative n- and p-channel device designs.     

Strained-Si Channel Super-Self-Aligned Back-Gate/Double-Gate Planar Transistors

We present a reproducible approach to the fabrication of super-self-aligned back-gate/double-gate n-channel and p-channel transistors with thin silicon channels and thick source/drain polysilicon regions. The device structure provides capability for scalable control of channel electrostatics, threshold variability without sacrificing source/drain series resistance, and capability of introducing strain to improve carrier transport. The separate device, circuit, and functional level back-gate access that is available through bottom interconnection also provides capability for adaptive power control and novel circuit design. Both n-channel and p-channel devices are demonstrated with the threshold tuning capability     

1/f noise and radiation effects in MOS devices

An extensive comparison of the 1/f noise and radiation response of MOS devices is presented. Variations in the room-temperature 1/f noise of unirradiated transistors in the linear regime of device operation correlate strongly with variations in postirradiation threshold-voltage shifts due to oxide trap charge. A simple number fluctuation model has been developed to semi-quantitatively account for this correlation. The 1/f noise of irradiated n-channel MOS transistors increases during irradiation with increasing oxide-trap charge and decreases during postirradiation positive-bias annealing with decreasing oxide-trap charge. No such correlation is found between low-frequency 1/f noise and interface-trap charge. The noise of irradiated p-channel MOS transistors also increases during irradiation, but in contrast to the n-channel response, the p-channel transistor noise magnitude increases during positive-bias annealing with decreasing oxide-trap charge. A qualitative model involving the electrostatic charging and discharging of border traps, as well as accompanying changes in trap energy, is developed to account for this difference in n- and p-channel postirradiation annealing response. The correlation between the low-frequency 1/f noise of unirradiated devices and their postirradiation oxide-trap charge suggests noise measurements can be used as a nondestructive screen of oxide trap charge related failures in discrete MOS devices and for small scale circuits in which critical transistors can be isolated. It also suggests that process techniques developed to reduce radiation-induced-hole trapping in MOS devices can be applied to reduce the low-frequency 1/f noise of MOS circuits and devices. In particular, reducing the number of oxygen vacancies and vacancy complexes in the SiO ₂ can significantly reduce the 1/f noise of MOS devices both in and outside a radiation environment     

Low-frequency noise characteristics in p-channel FinFETs

We report on the characterization of low-frequency noise in fully depleted (FD) double-gate p-channel FinFETs. While the average noise follows a 1/f dependence, considerable device-to-device variations in noise level are observed due to the statistical fluctuation of the number of oxide traps involved. We found that the low-frequency noise in poly-Si-gated p-FinFETs is mainly governed by the carrier number fluctuation with correlated mobility fluctuation. The low-frequency noise characteristics indicate that the FinFET device can be a promising candidate for analog and RF applications.     

SiO2/native double-gate InSb MOSFETs

An InSb MOS double-gate structure formed by a novel thermal oxidation method has been investigated. C/V characteristics showed a sharp change and no hysteresis. Both n-channel and p-channel MOSFETs have been successfully operated. The effective mobility at 77 K was approximately 7800 cm2/Vs for the n-channel and 300 cm2/Vs for the p-channel.     

Effects of mechanical strain on laser crystallized polysilicon thin film transistors and ring oscillators fabricated on stainless steel foil

In this paper the influence of mechanical tensile strain on the performance of thin film transistors (TFTs), with various channel geometries, and of ring oscillators, with 3, 7, 11, 21, and 51 number of stages and device channel lengths of 1, 4, and 8 μm, fabricated on stainless steel foil substrate is investigated. TFT parameters such as field effect mobility, threshold voltage, subthreshold slope, leakage and gate current for both n-channel, and p-channel TFTs are studied at various longitudinal tensile strain levels. For strain levels from 0.0% to 0.5%, the field effect mobility of n-channel TFTs increases while that of p-channel ones decreases as the longitudinal tensile strain increases. The field effect mobility, of both n-channel and p-channel TFTs, becomes independent of longitudinal tensile strain at strain levels greater than 0.5%. Threshold voltage and subthreshold slope of p-channel TFTs increases while that of n-channel ones does not follow a specific trend. The leakage current of both type devices tends to decrease by increasing the longitudinal tensile strain. The propagation delay, per inverter stage of a ring oscillator, is investigated at different supply voltages and tensile strain levels. The propagation delay of inverters with longer device channel length (?4 μm) tends to decrease while that of shorter length tends to increase as the longitudinal tensile strain increases.     

Change in transfer and low-frequency noise characteristics of n-channel polysilicon TFTs due to hot-carrier degradation

Results on the impact of hot-carrier effects on the transfer and low-frequency noise characteristics of n-channel poly-crystalline silicon thin-film transistors (polysilicon TFTs) are presented. After stressing at the condition of maximum substrate current, the experimental data show that TFTs suffer from substantial on-current reduction. Through numerical simulation, it is shown that the stress-induced degradation increases the density of the band tail traps in a region extending 200 nm from the drain and the series resistance on the drain side. It is found that the origin of the noise is reverted from carrier number fluctuation for the unstressed to the mobility fluctuation for the stressed device.     

Noise performance of Si/Si/sub 1-x/Ge/sub x/ FETs

Noise characteristics are evaluated for SiGe/Si based n-channel MODFETs and p-channel MOSFETs. The analysis is based on a self-consistent solution of Schrodinger and Poisson's equations. The model predicts a superior minimum noise figure for an n-channel MODFET at 77 K. P-channel MOSFETs behave similar to n-channel devices operating at 300 K. Minimum noise figure decreases with increasing quantum well (QW) width for both n- and p-channel devices. However, the p-channel devices are less sensitive to QW width variation. Minimum noise temperature behaves similarly. As observed, a range of doped epilayer thickness exists where minimum noise figure is a minimum for both n- and p-channel FETs.<>     

Novel polycrystalline silicon thin film transistors prepared by deposition from Si2H6 and subsequent annealing by NH3 plasma

This work investigated the channel layer of polycrystalline silicon (poly-Si) thin film transistors (TFTs) prepared by amorphous silicon (a-Si) films deposited using Si₂H₆ gas. The recrystallization of channel layers, source/drain, gate electrodes and post implant anneal were performed at the same time. Due to the larger grain size, the device has higher field effect mobility than SiH₄ deposited devices. These devices were also subsequently passivated by NH₃ plasma. The NH₃ plasma significantly improves the n-channel devices; however, the improvement of p-channel devices is limited. Especially, the threshold voltage of n-channel devices is significantly shifted toward the negative gate voltage than the shift magnitude of p-channel devices. To investigate the band gap width and Fermi level by determining the leakage activation energy, it is found that the channel film is changed slightly from p-type to n-type. These results may be attributed to the donor effect by NH₃ plasma passivation.     

Analytical model and characterization of small geometry MOSFET's

Electrical characteristics of small geometry p-channel and n-channel MOSFET's are characterized based on an analytical model that includes short-channel, narrow-channel, and carrier-velocity-saturation effects. Theoretical results on threshold voltage, threshold-voltage shift by a substrate bias voltage, and drain current are in good agreement with the experimental results over wide ranges of channel lengths from 1 to 9 µm and channel widths from 2 to 14 µm. A comparison of the electrical characteristics of MOSFET's with and without field implantation leads to the conclusion that the field implantation is the main cause of the narrow-channel-width effect on threshold-voltage increase and drain-current degradation. The carrier-velocity-saturation effect starts to appear at the 3-µm channel length for the n-channel device and at 1 µm for the p-channel device under 5-V operation. According to the theoretical analysis of a 1-µm-channel inverter circuit, a CMOS inverter has superior noise immunity with 1.4 to 2.0 times larger driving-current capability in a load MOS device and requires 9 percent less area than a 1-µm n-channel enhancement/depletion inverter.     

Characteristics of p-channel polysilicon conductivity modulatedthin-film transistors

A p-channel polysilicon conductivity modulated thin-film transistor (CMTFT) is demonstrated and experimentally characterized. The transistor uses the concept of conductivity modulation in the offset region to obtain a significant reduction in on-state resistance. The conductivity modulation is achieved by injecting minority carriers (electrons) into the offset region through a diode added to the drain. Experimental results show that the conductivity modulation in the p-channel device is as effective as that in the n-channel device. This structure can provide 1.5 to 2 orders of magnitude higher on-state current than that of the conventional offset drain thin-film transistor (TFT) at drain voltage ranging from -15 V to -5 V while still maintaining low leakage current and simplicity in device operation. The p-channel CMTFT can be combined with the n-channel CMTFT to form CMOS high-voltage drivers, which is very suitable for use in fully integrated large-area electronic applications     

Integration of n- and p-channel InGaP=InGaAs doped-channel pseudomorphic HFETs

n- and p-channel InGaP/InGaAs doped-channel pseudomorphic HFETs on the identical chip by selectively etching process are first demonstrated. Particularly, the saturation voltage of the n-channel device is relatively small because 2DEG is formed and modulated in the InGaAs strain channel. Experimentally, an extrinsic transconductance of 292 (72) mS/mm and a saturation current density of 335 (-270) mA/mm are obtained for the n-channel (p-channel) device. Furthermore, the integrated devices exhibit broad gate voltage swings for linear and signal amplifier applications.     

p-channel modulation-doped field-effect transistors based on AlSb0.9As0.1/GaSb

Operation of the first AlSbAs/GaSb p-channel modulation-doped field-effect transistor (MODFET) is reported. Devices with 1-μm gate length exhibit transconductance of 30 and 110 mS/mm at room temperature and 80 K, with respective maximum drain current densities of 25 and 80 mA/mm. The low field Hall mobility and sheet carrier density of this modulation doped structure were 260 cm²/V-s and 1.8×10 ¹² cm^-2 at room temperature and 1700 cm²/V-s and 1.4×10¹² cm^-2 at 77 K. Calculations based on these results indicate that room-temperature transconductances of 200 mS/mm or greater could be achieved. This device can be integrated with an InAs n-channel HFET for complementary circuit applications