MISO current mode bi-quadratic filter employing high performance inverting second generation current conveyor circuit

This paper presents static and dynamic studies of a new CMOS realization for the inverting second generation current conveyor circuit (ICCII). The proposed design offers enhanced functionalities compared to ICCII circuits previously presented in the literature. It is characterized by a rail to rail dynamic range with high accuracy, a low parasitic resistor at terminal X (1.6 Ω) and low power consumption (0.31 mW) with wide current mode (3.32 GHz) and voltage mode (3.9 GHz) bandwidths.Furthermore, a new MISO current mode bi-quadratic filter based on using ICCII circuits as active elements is proposed. This filter can realize all standard filter responses without changing the circuit topology. It is characterized by active and passive sensitivities less than unity and an adjustment independently between pole frequency and quality factor. The operating frequency limit of this filter is about 0.8 GHz with 0.674 mW power consumption.The proposed current conveyor circuits and bi-quadratic filter are tested by TSPICE using CMOS 0.18 µm TSMC technology with ±0.8 V supply voltage to verify the theoretical results.     

A new ultra low-power,universal OTA-C filter in subthreshold region using bulk-drive technique

In this paper, a new ultra low-power universal OTA-C filter which can properly operate in all modes of operation (voltage, current, trans-resistance and trans-conductance) is presented. However, in order to reduce the power consumption effectively, the proposed circuit uses subthreshold transistors which are biased at I_a = 50 nA, I_b = 150 nA. Furthermore, using the bulk-drive technique leads to a reduced power consumption as well as the supply voltage of ±0.3 V. Moreover, the grounded capacitors are used to effectively reduce the parasitic effects. However, the result of sensitivity analysis shows that the proposed circuit has a very low sensitivity to the values of active and passive circuit elements such as: trans-conductance (g_m) and capacitance (C) values. Furthermore, the proposed circuit uses the minimum number of active elements to effectively reduce the power consumption as well as the chip area. Finally, the proposed filter is designed and simulated in HSPICE using 0.18µm CMOS technology parameters, while HSPICE simulation results have very close agreement with theoretical results obtained from MATLAB, which justifies the design accuracy and low-power performance of the proposed universal filter.     

Realization of current-mode biquadratic filter employing multiple output OTAs and MO-CCII

This paper presents a low voltage low power operational transconductance amplifier circuit. By using a source degeneration technique, the proposed realization powered at ±0.9 V shows a high DC gain of 63 dB with a unity gain frequency at 3.5 MHz, a wide dynamic range and a total harmonic distortion of −60 dB at 1 MHz for an input of 1 Vpp. According to the connection of negative current terminal to positive voltage terminal of double output OTA circuit, a second generation current conveyor (CCII-) has been realized. This circuit offers a good linearity over the dynamic range, an excellent accuracy and wide current mode of 56 MHz and voltage mode of 16.78 MHz cut-off frequency f-3 dB.Thereafter, new SIMO current-mode biquadratic filter composed by OTA and CCII as active elements and two grounded capacitors is implemented. This filter is characterized by (i) independent adjusting of pole frequency and quality factor, (ii) it can realize all simulations results without changing the circuit topology, (iii) it shows low power consumption about 0.24 mW. All simulations are performed by Cadence (Cadence Design Systems) technology Tower Jazz 0.18 μm TS18SL.     

Electronically tunable MOSFET-only current-mode biquad filter

A novel current mode MOSFET-only structure with multi-input single-output (MISO) is proposed. The proposed circuit is free from passive circuit elements like resistors and capacitors and able to realize low-pass (LP), band-pass (BP), high-pass (HP), band-stop (BS) and all-pass (AP) filter functions with using the same circuit configuration. It is also important to note that the proposed filter has electronic tunability property. The proposed circuit is laid-out in the Cadence environment using 0.18 µm TSMC CMOS technology parameters. The layout area is only 408 μm² and the power consumption is about 0.6 mW. Furthermore, to investigate the performance of the BP filter output of the proposed MISO filter, Monte Carlo and corner analyses are also presented. It is shown that the mismatches and the process variations cause only small deviations for the BP filter configuration. Furthermore, the noise performance of the proposed filter is also investigated.     

Single-input four-output voltage-mode universal filter using single DDCCTA

An electronically tunable universal voltage-mode biquadratic filter with single input and four outputs using one differential difference current conveyor transconductance amplifier (DDCCTA), two resistors and two grounded capacitors is proposed. All the five standard biquadratic filter functions; lowpass (LP), bandpass (BP), highpass (HP), bandstop (BS) and allpass (AP), can be obtained from the circuit configuration. The LP, BP and HP are simultaneously available without component matching condition. By imposing component choice, the BS and AP responses can also be realized from the same circuit configuration. In addition, the proposed circuit provides an electronic control of its natural angular frequency (ω₀) and quality factor (Q) by adjusting the bias current of the DDCCTA. The simulation results together with the ideal values are also given to demonstrate the performance of the proposed circuit.     

Low-voltage low-power FGMOS based VDIBA and its application as universal filter

This paper presents Floating gate MOS (FGMOS) based low-voltage low-power variant of recently proposed active element namely Voltage Differencing Inverting Buffered Amplifier (VDIBA). The proposed configuration operates at lower supply voltage ±0.75 V with the total quiescent power consumption of 1.5 mW at the biasing current of 100 µA. Further the operating frequency of the proposed VDIBA is improved by using the resistive compensation method of bandwidth extension in Operational Transconductance Amplifier (OTA) stage of the block. By using resistive compensation method of bandwidth extension, the bandwidth of OTA stage increases from 92.47 MHz to 220.67 MHz. As an application, proposed FGMOS based VDIBA has been used to realize a novel resistorless voltage mode (VM) universal filter. The proposed universal filter configuration is capable of realizing all the standard filter functions in both inverting and non-inverting forms simultaneously without any matching constraint. Other important features include independently tunable filter parameters, cascadibility and low sensitivity figure. The proposed filter is tunable over the frequency range of 4.1 MHz to 12.9 MHz and is capable of compensating for process, voltage and temperature (PVT) variation. The simulations are performed using SPICE and TSMC 0.18 µm CMOS technology parameters with±0.75 V supply voltage to validate the effectiveness of the proposed circuit.     

A low power current controllable single-input three-output current-mode filter using MOS transistors only

A novel circuit configuration for the realization of low power single-input three-output (SITO) current mode (CM) filters employing only MOS transistors are presented. The proposed circuit can realize low-pass (LP), band-pass (BP) and high-pass (HP) filter functions simultaneously at three high impedance outputs without changing configuration. Despite the other previously reported works, the proposed circuit is free from resistors and passive capacitors. Instead of passive capacitors; the gate-source capacitor of MOS transistor is used making the proposed circuit ideally suitable for integration. Compared to other works, the proposed filter has also the lowest number of transistors and lowest power consumption. The proposed circuit exhibits low-input and high-output impedances, which is highly desirable for cascading in CM signal processing. Moreover, it is center frequency can be electronically adjusted using a control current without a significant effect on quality factor (Q) granting it the highly desirable capability of electronic tunability. Transfer functions of the LP, BP and HP outputs are derived and the performance of the proposed circuit is proved through pre layout and post layout simulations at supply voltage of 1.8 V and using 0.18 μm CMOS process parameters. The power consumption and the required chip area are only 0.5 mW and 77.4 μm × 70.2 μm, respectively.     

Current mode single-input multi-output MOSFET-only filter

In this paper, a very simple topology of a current mode MOSFET-only filter with single-input and multi-output is proposed. It is very important to emphasize that it is possible to obtain five of the filter functions, namely low-pass (LP), band-pass (BP), high-pass (HP), band-stop (BS) and all-pass (AP) using the proposed topology without using external passive elements. The core circuit of the proposed filter employs only four MOS transistors; therefore, it occupies very small chip area. It is also possible to adjust the filter gain with the biasing voltage. In addition, the circuit exhibits a very low input impedance and also high output impedances which make it possible for cascading. The MOSFET capacitances which determine the transfer functions are all grounded, so physical capacitances can be used instead of MOSFET parasitic capacitances to operate the filter at very low frequencies. Moreover, proposed filter structure has low supply voltage as 1 V in order to be applicable to low voltage operations. Detailed simulation results, including noise and Monte Carlo analysis, are provided using 0.18 µm TSMC technology parameters to verify the feasibility of the filter circuit.     

Current mode filters with reduced complexity using a single EX-CCCII

In this paper an active element Extra-X current controlled conveyor (EX-CCCII) is used to reduce the complexity of some existing circuits. Two second-order current-mode biquadratic filter circuits are proposed, each using a single active element and two grounded capacitors. The first circuit is three input single output (TISO) and the second one is single input three outputs (SITO) biquadratic filter. The First circuit can realize all the standard filter transfer functions, while the second circuit can realize LP, BP and HP responses. The study of non-idealities and parasitics of the active element and their effects on transfer functions is carried out. The new circuits are found to be simpler than the earlier ones in terms of number of transistors. The functionality of the proposed biquadratic filters is verified through detailed PSPICE simulations using 0.25 µm TSMC CMOS technology parameters.     

A compact planar ultra-wideband bandpass filter with multiple resonant and defected ground structure

A compact bandpass filter with dumbbell shape Defected Ground Structure (DGS) operating on ultra wide pass band (UWB – 3.1 to 10.6 GHz) is proposed. It is based on hybrid microstrip coplanar waveguide (dual sided metal) structure. A Multiple Resonant Structure (MRS) is constructed using coplanar waveguide (CPW) planar transmission line. The MRS makes the resonance using quarter wavelength and half wavelength open-ended CPW. The equispaced three resonances at lower (3.1 GHz), center (6.85 GHz) and higher edge (10.6 GHz) of the whole Ultra Wide Band is achieved using CPW MRS. To make the band as flat as possible, two more resonances are introduced using quarter wavelength microstrip patches on top of the commonly shared substrate, so the proposed filter becomes a five pole bandpass filter. A dumbbell shaped defected ground structure on either side of CPW MRS improves the return loss almost less than 20 dB over the whole UWB passband. The simulated results of proposed filter show good transmission response within passband and good rejection in out of the band. The simulated and measured results are very close to each other which proves the efficacy of proposed design.     

Current mode high-frequency KHN filter employing differential class AB log domain integrator

In this study, a current mode log domain differential Class AB biquad filter based on Kerwin–Huelsman–Newcomb (KHN) structure has been synthesized by using the state-space method and by adopting translinear circuits. The proposed circuit can produce second-order low pass, band pass, high pass, all pass, and notch filter characteristics. The circuit is synthesized for high-frequency applications, i.e. around 100 MHz. The natural frequency and Q quality factor of the filter can be tuned electronically by varying the currents of current sources. Moreover, by varying currents of selected current sources, one can change the characteristics of the notch filter to generate general, low pass, and high pass notch filters. The designed circuit is simulated in both time domain and frequency domain in PSpice by using both idealized and NE 600 series type real transistors that are suitable for high-frequency operations. The frequency as well as time domain responses are found to be as expected. In addition to these simulations, THD and noise analysis are carried out. The details of obtained results are given.     

A sub-sampling 4.25 GS/s 3-bit flash ADC with asymmetric spatial filter response

A sub-sampling 3-bit 4.25 GS/s flash ADC with a novel averaging termination technique—asymmetric spatial filter response—in 0.13 um CMOS for impulse radio ultra-wideband (IR-UWB) receiver is presented. In this design, a track and hold (T/H) circuit with self-biased buffer is used to compensate the degradation in amplitude when frequency increases to giga Hz. Averaging termination technique using asymmetric spatial filter response is proposed to relieve the termination offset of the flash ADC. A revised encoder scheme is adopted to solve the problem of different propagation delay. The measurement results reveal that the SFDR and SNDR of the ADC are 26.3 dB and 18.4 dB, respectively, even the input signal frequency is 4.2 GHz. INL and DNL are measured improved to 0.11LSB and 0.18LSB, respectively, when asymmetric spatial filter is used. The power of ADC is 63 mW and the active area is 0.49×0.72 mm². The ADC achieves a figure of merit (FoM) of 2.2 pJ/conversion-step.     

A low-jitter wide-range duty cycle corrector for high-speed high-precision ADC

This paper presents a duty cycle corrector (DCC) circuit for high-speed and high-precision pipelined A/D converter. Combined charge pump is used to ensure the stability of the current source and the current sink, and the charge sharing effect can be suppressed to improve the accuracy of the duty cycle of the output clock. The added second-order low-pass filter with Miller capacitance to the differential output of combined charge pump not only saves the area, but also improve the loop stability, which making wider range of input duty cycle (10–90%). The circuit can also effectively suppress the clock jitter. The post-simulation results are based on SMIC 65 nm CMOS process. The duty cycle accuracy of output clock signal in the proposed DCC is 50±0.2%. In 200 MHz input frequency, 27 °C TT process corner, RMS jitter is about 186.6 fs, Peak-to-Peak jitter is about 1.447 ps. With 2.5 V supply voltage, the power consumption is 1.88 mW and the active chip area is 0.02 mm². This work has been successfully applied in 13-bit 200MSPS A/D converter.     

Electronically tunable DXCCII-based grounded capacitance multiplier

In this paper a new grounded capacitance multiplier based on DXCCII suitable for operation at low and moderate frequencies is presented. The proposed circuit employs only a single dual-X second-generation current conveyor (DXCCII) active device, used as a voltage amplifier with two NMOS transistors operating in triode region, cooperating with a floating capacitor. The realized equivalent capacitance obtained from Miller multiplication of the reference capacitor and its multiplication factor is electronically tunable. Simulation results using AMS 0.35 μm CMOS process technology parameters are included. Functionality of the proposed circuit is verified through its application in a G_m-C second-order low-pass filter.     

Design of microstrip wide stopband quad-band bandpass filters for multi-service communication systems

This paper presents two planar high performance quad-channel bandpass filters, which are designed based on a novel circular multi-mode resonator. In this paper and for the first time, the proposed resonator is utilized to achieve quad passbands. It consists of diverged feeding lines that are coupled to etched circular cells. The first filter has quite close channels at 2.62, 2.88, 4.34 and 4.67 GHz, which make it appropriate for frequency division duplex (FDD) scheme. Meanwhile, the second filter is designed for WCDMA and WiMAX applications. Both filters are able to attenuate the harmonics up to 19 GHz with a maximum harmonic level of −20 dB. The insertion losses and return losses of both filters at all channels are better than 1.2 dB and 17.5 dB, respectively. The harmonic attenuation method is presented employing a LC equivalent circuit of the proposed resonator. In order to verify the designing methodology, the proposed filters are fabricated and measured where there are good agreements between the simulation and measurement results.     

A low voltage and low power parallel electronically tunable resistor with linear and nonlinear characteristics

In this paper a bilateral resistive circuit is designed and presented with is work as a positive and negative electronically tunable resistor and has zero DC offset. The proposed topology is designed by paralleling two electronically tunable resistors to obtain lower resistive values and decreasing nonlinearity percent. The proposed topology is low voltage and low power and with proper transcurrent circuit, its current–voltage characteristics can be linear, expansive (square) and compressive (square root). Its supply voltages are ±1 V and its dynamic range is ±1 V too. The designed circuit is simulated in an industrial 65 nm CMOS process. The linear version is tunable over the wide resistance range of 7 kΩ–37 GΩ.     

CMOS linear high performance push amplifier for WiMAX power amplifier

In this work a novel and efficient approach is proposed to optimize the linearity and efficiency of power amplifiers used in mobile WiMAX applications. A linear and high performance push amplifier is designed and implemented in 0.18 μm CMOS technology to enhance the linearity of a class-E switched-mode power amplifier. The proposed push amplifier consists of two sections; analog and switching sections. The analog section provides required linearity and the switching section guarantees satisfying total efficiency level. Each block is designed and optimized to meet required specifications. The core power amplifier which is a class-E switched-mode power amplifier is also designed to have maximum possible efficiency. The implemented circuit is simulated using HSPICERF and TSMC models for active and passive elements. The proposed power amplifier provides a maximum output power of 25 dBm and a power added efficiency (PAE) as high as 48% at 2.5 GHz operation frequency and supply voltage of 1.8 V. At 1 dB compression point this PA exhibits 23 dBm of output power with 42% PAE and 4.5% EVM which was appropriate for 64QAM OFDM signals.     

0.8 V PLL-based automatic frequency tuning system for current-mode filters

A wide-range automatic frequency tuning system for current-mode filters is proposed in this paper. The cutoff frequency of the tunable filter is controlled by an external reference signal and is locked in the desired frequency through a current-mode based phase locked loop (PLL) circuit. Although the PLL operates in a relatively narrow band, the total tuning range of the topology is extended by interpolating an automatic frequency detector after the reference input and before the PLL. The use of current controlled oscillator, based on same blocks with those in the filter, offers accuracy and feasible design in the control path. The topology has been simulated using MOS transistor models for a 130 nm CMOS technology in 0.8 V supply voltage. The achieved overall automatic tuning range was from 2.3 MHz to 660 MHz.     

Analytical modeling of CMOS circuit delay distribution due to concurrent variations in multiple processes

A technique for modeling the effect of variations in multiple process parameters on circuit delay performance is proposed. The variation in saturation current I_on at the device level, and the variation in rising/falling edge stage delay for the NAND gate at the circuit level, are taken as performance metrics. The delay of a two-input NAND gate with 65 nm gate length transistors is extensively characterized by mixed-mode simulations, which is then used as a library element. Appropriate templates for the NAND gate library are incorporated in a general purpose circuit simulator SEQUEL. A 4-bit × 4-bit Wallace tree multiplier circuit, consisting of two-input NAND gates is used to demonstrate the proposed methodology. The variation in the multiplier delay is characterized, by generating delay distributions, using an extensive Monte Carlo analysis. The use of linear interpolation and linear superposition is evaluated to study simultaneous variations in two and more process parameters. An analytical model for gate delays, in terms of device drive current I_on, is proposed, which can be used to extend this methodology for a generic technology library with a variety of library elements. The model is validated against Monte Carlo simulations and is shown to have a typical error of less than 0.1% for simultaneous variations in multiple process parameters. The proposed methodology can be used for statistical timing analysis and circuit simulation at the gate level.     

Current mode first order universal filter and multiphase sinusoidal oscillator

In this article a new current mode first order universal filter with single input and multiple outputs is proposed. The realization uses single dual-X multiple output second generation current conveyor (DX-MOCCII) and two passive grounded components. The presented circuit provides high-pass, low-pass and non-inverting and inverting all-pass responses simultaneously, all at different high impedance outputs. The realized circuit does not require any component matching constraint and all the sensitivities are found low. As an application the non-inverting all-pass filter is cascaded in a close loop with the current mode non-inverting integrator to design a current mode multiphase sinusoidal oscillator (MSO) having six phases. Voltage mode six phase sinusoidal oscillator is also achieved by resistively loading the current mode outputs. The analysis such as phase noise, non-ideality, stability and Monte Carlo are presented and discussed. The presented theory and its results are validated using 0.25 µm process parameters of TSMC in PSPICE simulator.