On the use of high-impedance power supplies to reduce the substrate switching noise in system-on-chips

This paper analyzes the generation and the propagation in system-on-chips of the switching noise due to embedded core logic blocks. Such disturbances contribute to degrade the performance of the other on-chip circuits and cause unwanted electromagnetic emission. These parasitic effects can be largely ascribed to the steep currents that flow into the power supply interconnects of the core logic blocks and to the parasitic coupling of the system-on-chip building blocks through the silicon substrate they share.In this work it is shown that the substrate voltage bounce due to the switching noise can be significantly attenuated if conventional low-impedance DC power supplies are replaced by high-impedance one. The effectiveness of the proposed approach is validated through computer simulations and experimental tests carried out on the digital core block of a test chip.     

Single event upset mitigation by means of a sequential circuit state freeze

This paper describes a novel design technique for hardening sequential circuits against Single Event Transients (SETs) and Single Event Upsets (SEUs) in non-volatile FPGAs. Double Modular Redundancy (DMR) is used to detect the presence of a SET in a sequential circuit. However, DMR solutions are only able to detect SET’s and not mask or correct them. Therefore, extra functionality is required to mask and correct the error after it has been detected. The central idea of the method proposed is to “freeze” the sequential circuit at a particular state when a SET is detected. As soon as the SET dissipates, the circuit is “unfrozen” so that it can continue with normal operation. Due to the short SET lifetime versus much longer circuit clock periods, the “frozen” state will normally not last more than one clock period. The proposed scheme is suitable for delay-insensitive applications requiring minimal hardware overhead.The proposed DMR method is thoroughly tested on ITC99 benchmarks. With a small delay of one clock period whenever a SET is detected, the proposed method offers immunity against the errors caused by SETs in non-volatile FPGA systems.     

Coupling induced soft error mechanisms in nanoscale CMOS technologies

Due to scaling induced effects, CMOS circuits become increasingly more sensitive to transient pulses caused by single event (SE) particles. Researchers mostly considered SE transients as the main cause for combinational logic (CL) related radiation-induced soft errors. However, for high-reliability applications such as avionics, military and medical applications, additional sources such as SE induced soft delays, clock jitters, false clock pulses and crosstalk effects need to be included in soft-error reliability analysis. As technologies advance, coupling effects among interconnects increasingly cause SE transients to contaminate electronically unrelated circuit paths, which can in turn increase the “SE susceptibility” of CMOS circuits. This work focuses on such coupling induced soft error mechanisms in CL, namely the SE crosstalk noise and delay effects. An attempt has been made to compare SE crosstalk noise and SE transient effects, and crosstalk contribution to soft error rate has been examined. In addition, the SE induced coupling delay effect has been studied and compared to radiation induced soft delay effect for various technologies. Results show that, in newer technologies, the SE coupling delay becomes quite comparable to soft delay effect, although caused indirectly by cross-coupling effects. In comparisons, the distributed nature of interconnects has been taken into account and results are demonstrated using HSPICE simulations with interconnect and device parameters derived in 130, 90 and 65 nm technologies.     

基于四值脉冲参数模型的单粒子瞬态传播机理与软错误率分析方法

随着工艺尺寸的不断缩小,由单粒子瞬态(Single Event Transient, SET)效应引起的软错误已经成为影响宇航用深亚微米VLSI电路可靠性的主要威胁,而SET脉冲的产生和传播也成为电路软错误研究的热点问题。通过研究SET脉冲在逻辑链路中的传播发现：脉冲上升时间和下降时间的差异能够引起输出脉冲宽度的展宽或衰减;脉冲的宽度和幅度可决定其是否会被门的电气效应所屏蔽。该文提出一种四值脉冲参数模型可准确模拟SET脉冲形状,并采用结合查找表和经验公式的方法来模拟SET脉冲在电路中的传播过程。该文提出的四值脉冲参数模型可模拟SET脉冲在传播过程中的展宽和衰减效应,与单参数脉冲模型相比计算精度提高了2.4%。该文应用基于图的故障传播概率算法模拟SET脉冲传播过程中的逻辑屏蔽,可快速计算电路的软错误率。对ISCAS89及ISCAS85电路进行分析的实验结果表明：该方法与HSPICE仿真方法的平均偏差为4.12%,计算速度提升10000倍。该文方法可对大规模集成电路的软错误率进行快速分析。     

Parallel pseudorandom number generation in GaAs cellular automata for high speed circuit testing

To facilitate test vector generation for high-speed circuits, we present the design and circuit simulation of parallel pseudorandom number generators in GaAs technology. These PRNGs are based on hybrid cellular automata (CA) in which mixtures of local rules are employed in one dimensional arrays, with minimal delay due to having only local wiring between neighboring cells. HSPICE simulations of these circuits demonstrate that they operate at a clock frequency above 1 GHz. Delay simulations indicate that GaAs PRNGs based upon linear feedback shift registers, in contrast with hybrid CAs, exhibit a degradation in clock frequency due to the effects of global interconnects, and that this degradation increases with the register length.This work was supported by Micronet, by the Canadian Microelectronics Corporation, and by the Natural Sciences and Engineering Research Council of Canada.     

Picosecond nodal testing of centimeter-size superconducting Nb microstrip interconnects

We have implemented a low-temperature electro-optic sampling system for non-invasive, nodal testing of superconducting Nb integrated circuits. With submillivolt sensitivity and a subpicosecond temporal response, this system has been used to perform nodal analysis on rapid-single-flux quantum (RSFQ) devices and superconducting microstrip interconnects. Here we demonstrate that by measuring the propagation of 6-ps-wide pulses at various test nodes, we are able to fully characterize a superconducting microstrip waveguide the size of an entire chip. The transmission line was selected not only to perform the first complete characterization of a superconducting microstrip, but also to demonstrate full nodal testing of a foundry-fabricated RSFQ integrated circuit. Finally, our results provided much-needed feedback for improving computer simulations of superconducting digital circuits.     

Analysis and experimental verification of digital substrate noisegeneration for epi-type substrates

Substrate coupling in mixed-signal IC's can cause important performance degradation of the analog circuits. Accurate simulation is therefore needed to investigate the generation, propagation, and impact of substrate noise. Recent studies were limited to the time-domain behavior of generated substrate noise and to noise injection from a single noise source. This paper focuses on substrate noise generation by digital circuits and on the spectral content of this noise. To simulate the noise generation, a SPICE substrate model for heavily doped epi-type substrates has been used. The accuracy of this model has been verified with measurements of substrate noise, using a wide-band, continuous-time substrate noise sensor, which allows accurate measurement of the spectral content of substrate noise. The substrate noise generation of digital circuits is analyzed, both in the time and frequency domain, and the influence of the different substrate noise coupling mechanisms is demonstrated. It is shown that substrate noise voltages up to 20 mV are generated and that, in the frequency band up to 1 GHz, noise peaks are generated at multiples of the clock and repetition frequency. These noise signals will strongly deteriorate the behavior of small signal analog amplifiers, as used in integrated front-ends     

Transient drain current and propagation delay in SOI CMOS

The transient overshoot in drain current that occurs in thin-film SOI (Si-on-SiO2) MOSFET's because of the floating body in analyzed, and the benefit it can provide to propagation delay (speed) in SOI CMOS digital circuits is assessed. The analysis accounts for the charge coupling between the front and back gates, and hence describes the dependence of the transient drain (saturation) current and propagation delay on the back-gate bias as well as on the switching frequency. Measurements of the transient current in recrystallized SOI MOSFET's and of propagation delay in SOI CMOS inverters and ring oscillators are described and shown to support the theoretical analysis. The current overshoot is especially beneficial in low-voltage circuits, although at high frequencies other floating-body effects can degrade the speed.     

Full-wave simulation of electromagnetic coupling effects in RF and mixed-signal ICs using a time-domain finite-element method

This paper describes the computer simulation and modeling of distributed electromagnetic coupling effects in analog and mixed-signal integrated circuits. Distributed electromagnetic coupling effects include magnetic coupling of adjacent interconnects and/or planar spiral inductors, substrate coupling due to stray electric currents in a conductive substrate, and full-wave electromagnetic radiation. These coupling mechanisms are inclusively simulated by solving the full-wave Maxwell's equations using a three-dimensional (3-D) time-domain finite-element method. This simulation approach is quite general and can be used for circuit layouts that include isolation wells, guard rings, and 3-D metallic structures. A state-variable behavioral modeling procedure is used to construct simple linear models that mimic the distributed electromagnetic effects. These state-variable models can easily be incorporated into a VHDL-AMS simulation providing a means to include distributed electromagnetic effects into a circuit simulation.     

Single event soft error in advanced integrated circuit

As technology feature sizes decrease, single event upset (SEU), and single event transient (SET) dominate the radiation response of microcircuits. Multiple bit upset (MBU) (or multi cell upset) effects, digital single event transient (DSET) and analogue single event transient (ASET) caused serious problems for advanced integrated circuits (ICs) applied in a radiation environment and have become a pressing issue. To face this challenge, a lot of work has been put into the single event soft error mechanism and mitigation schemes. This paper presents a review of SEU and SET, including: a brief historical overview, which summarizes the historical development of the SEU and SET study since their first observation in the 1970's; effects prominent in advanced technology, which reviews the effects such as MBU, MSET as well as SET broadening and quenching with the influence of temperature, device structure etc.; the present understanding of single event soft error mechanisms, which review the basic mechanism of single event generation including various component of charge collection; and a discussion of various SEU and SET mitigation schemes divided as circuit hardening and layout hardening that could help the designer meet his goals.     

Modeling single event crosstalk speedup in nanometer technologies

With advances in CMOS technology, circuits become increasingly more sensitive to transient pulses caused by single event (SE) particles. In addition, coupling effects among interconnects can cause SE transients to spread electronically unrelated circuit paths which may increase the SE Susceptibility of CMOS circuits. The coupling effects among interconnects need to be considered in single event modeling and analysis of CMOS logic gates due to technology scaling effects that increase both SE vulnerability and crosstalk effects. This work reports on the signal speedup effects caused by SE crosstalk and then proposes a best-case delay estimation methodology for use in design automation tools for the first time to our knowledge. The SE coupling speedup expressions derived show very good results in comparison to HSPICE results. Results show an average error of about 8.42% for best-case delay while allowing for very fast analysis in comparison to HSPICE.     

SET logic driving capability and its enhancement in 3-D integrated SET–CMOS circuit

The driving capability of a single-electron transistor (SET) circuit is sensitive to the load and interconnects. We discuss about improving the performance of a SET logic in hybrid SET–CMOS circuit by parameter variation and circuit architecture along with its simulation results. With an intention of studying the SET logic drivability in a SET-only circuit, we examined a circuit composed of 2¹³ SET inverters with its interconnect effect in a 3-D CMOS IC. The schematic of the simulation is based on fabrication model of this large circuit along with interlayer and coupling capacitances of its metallization. The simulation results for delay, bandwidth and power validate the efficiency of a SET circuit.     

Formal Methods Based Synthesis of Single Event Transient Tolerant Combinational Circuits

Recent radiation ground testing campaigns of digital designs have demonstrated that the probability for Single Event Transient (SET) propagation is increasing in advanced technologies. This paper presents a hierarchical reliability-aware synthesis framework to design combinational circuits at gate level with minimal area overhead. This framework starts by estimating the vulnerability of the circuit to SETs. This is done by modeling the SET propagation as a Satisfiability problem by utilizing Satisfiability Modulo Theories (SMTs). An all-solution SMT solver is adapted to estimate the soft error rate due to SETs. Different strategies to mitigate SETs are integrated in the proposed framework to selectively harden vulnerable nodes in the design. Both logical and temporal masking factors of the target circuit are improved to harden sensitive paths or sub-circuits, whose SET propagation probability is relatively high. This process is repeated until the desired soft error rate is achieved or a given area overhead constraint is met. The proposed framework was implemented on different combinational designs. The reliability of a circuit can be improved by 64% with less than 20% area overhead.     

Coupling and crosstalk between high speed interconnects inultralarge scale integrated circuits

The advent of sophisticated lithographic techniques has made it possible to fabricate densely packed ultra-large-scale-integrated (ULSI) circuits. In these chips, interconnect lines are so narrow and spaced in such close proximity that signal from one line could easily get coupled to another, causing interference and crosstalk. A general theory to model coupling between optical interconnects (waveguides) and quantum-mechanical coupling between narrow and very closely spaced silicide interconnects embedded in dielectrics (SiO₂) is presented     

脉冲激光试验评估模拟电路单粒子效应

利用脉冲激光对典型模拟电路的单粒子效应进行了试验评估及加固技术试验验证,研究2种不同工艺的运算放大器的单粒子瞬态脉冲(SET)效应,在特定工作条件下两者SET脉冲特征规律及响应阈值分别为79.4 pJ和115.4 pJ,分析了SET脉冲产生和传播特征及对后续数字电路和电源模块系统电路的影响。针对SET效应对系统电路的危害性,设置了合理的滤波电路来完成系统电路级加固,并通过了相关故障注入试验验证,取得了较好的加固效果。     

Modeling of Substrate Noise Generation, Isolation, and Impact for an LC-VCO and a Digital Modem on a Lightly-Doped Substrate

Substrate noise generated by the digital circuits on a mixed-signal IC can severely disturb the analog and RF circuits sharing the same substrate. Simulations at the circuit level of the substrate noise coupling in large systems-on-chip (SoCs) do not provide the necessary understanding in the problem. Analysis at a higher level of abstraction gives much more insight in the coupling mechanisms. This paper presents a physical model to estimate and understand the substrate noise generation by a digital modem, the propagation of this noise and the resulting performance degradation of LC tank VCOs. The proposed linearized model is fast to derive and to evaluate, while remaining accurate. It is validated with measurements on two test structures: a reference design and a design with a$hboxp^+ $/n-well (digital) guard ring. Both structures contain a functional 40k gate digital modem and a 0.18$muhbox m$3.5 GHz CMOS LC-VCO on a lightly-doped substrate. In both cases, the model accurately predicts the level of the spurious components appearing at the VCO output due to the digital switching activity. The error remains smaller than 3 dB. Finally, we demonstrate how the proposed model enables a systematic and controlled isolation strategy to suppress substrate noise coupling problems. As an example, the model is used to determine suitable dimensions for a digital guard ring.     

电荷共享对于CMOS逻辑门单粒子瞬态响应的影响

随着CMOS工艺继续缩小,单粒子瞬态脉冲已经成为航天用数字电路的重要故障来源。同时,相邻晶体管之间的电荷共享也随之增加并导致组合电路中单粒子瞬态脉宽缩短,即脉宽抑制效应。之前的文献提出了PMOS到PMOS的脉宽抑制,而本文提出了三种新的脉宽抑制机理(NMOS到PMOS,PMOS到NMOS和NMOS到NMOS),并且通过90纳米三维工艺混合仿真进行了验证。本文的贡献主要有以下三点：1）除了PMOS到PMOS的情况,90纳米工艺下脉宽抑制在PMOS到NMOS和NMOS到NMOS中同样比较明显;2）脉宽抑制效应总体上与粒子入射能量关系较弱,而与粒子入射角度和版图结构(晶体管间距和N阱接触)关系较强。3）紧凑的版图和级联反向单元可以用来促进组合电路中的单粒子瞬态脉宽抑制效应。     

SET and noise fault tolerant circuit design techniques: Application to 7 nm FinFET

In the near future of high component density and low-power technologies, soft errors occurring not only in memory systems and latches but also in the combinational parts of logic circuits will seriously affect the reliable operation of integrated circuits. This paper presents a novel design style which reduces the impact of radiation-induced single event transients (SET) on logic circuits, and enhances the robustness in noisy environments. The independent design style of this method achieves SET mitigation and noise immunity by strengthening the sensitive nodes using a technique similar to feedback. A realization for this methodology is presented in 7 nm FinFET and in order to check the accuracy of our proposal, we compare it with others techniques for hardening radiation at the transistor level against a single event transient. Simulation results show that the proposed method has a good soft error tolerance capability as well as better noise immunity.     

On-chip antennas in silicon ICs and their application

The feasibility of integrating antennas and required circuits to form wireless interconnects in foundry digital CMOS technologies has been demonstrated. The key challenges including the effects of metal structures associated with integrated circuits, heat removal, packaging, and interaction between transmitted and received signals, and nearby circuits appear to be manageable. This technology can potentially be applied for implementation of a true single-chip radio for general purpose communication, on-chip and inter-chip data communication systems, RFID tags, RF sensors/radars, and others.     

Single event crosstalk prediction in nanometer technologies

As CMOS technology continues to scale down, circuits become increasingly more sensitive to transient pulses caused by single event (SE) particles. On the other hand, coupling effects among interconnects can cause single event transients to contaminate electronically unrelated circuit paths which may increase the SE susceptibility of CMOS circuits. The coupling effects among interconnects need to be considered in single event hardening, modeling and analysis of CMOS logic gates due to technology scaling effects that increase both SE vulnerability and crosstalk effects. This work, for the first time, proposes an SE crosstalk noise estimation method for use in design automation tools. The proposed method uses an accurate 4-π model for interconnect and correctly models the effect of non-switching aggressors as well as aggressor tree branches noting the resistive shielding effect. The SE crosstalk noise expressions derived show very good results in comparison to HSPICE results. Results show that average error for noise peak is about 5.2% while allowing for very fast analysis in comparison to HSPICE.