New algorithm for testing random access memories

A linear time complexity algorithm to test RAMs is presented. The algorithm requires only 7 n read/write operations and provides an extensive fault coverage. The main advantage of the proposed scheme is that a small test time can be achieved.<>     

On-chip testing of random access memories

This article gives an overview of the Built-In Self-Test techniques for stand alone Random-Access Memory chips. It identifies the limitations of the existing fault models and the test algorithms used to test large RAMs. Methods to reduce test time for testing large RAMs are categorized. The article argues that even linear time test algorithms must use architecture and design for testability induced parallelisms to keep the total test time to an acceptable limit. Following that two algorithms are presented that can be used to test large RAMs for neighborhood pattern sensitive faults. Test lengths and test time for application of these algorithms are computed and it is suggested that a microprogrammed controller based scheme be used to implement self-test in stand alone RAMs.Part of this work was completed when the author was a Visting Professor at the University of Roorkee, India.     

Power reduction methods for NMOS dynamic random access memories

Power reduction methods for NMOS dynamic random access memories are proposed which reduce power dissipation. As the bit density increases in NMOS dynamic random access memories the power dissipation increases. A major consideration in the design of megabit dynamic random access memories is the power supply voltage. The power supply voltage mainly depends upon the following factors: power dissipation; reliability, such as high field effects due to small device size; memory cell operating margin. Power dissipation in decoders and 1 megabit NMOS dynamic random access memory chips are discussed. The basic properties of the proposed methods and a prototype VLSI implementation are discussed. In order to meet user power supply requirements, the proposed power reduction methods are useful for future megabit NMOS dynamic random access memories.     

Testable design of large random access memories

In this paper we propose a method for testable design of large Random Access Memories. The design technique relies on modification of address decoders to achieve multi-writes and multi-reads during test mode. Almost no modification is required in the design of memory array.A number of different designs for decoders are proposed. In all the designs the objective has been to keep the extra hardware for enhancing testability to as small as possible while causing a minimal or no degradation at all in the speed performance of RAM. Use of extra control and observation points is allowed as long as such points cause only a very small increase in the number of extra pins.We also propose the design of decorders in which only a limited number of cells of RAM are written to or read from during test mode.     

Maximal diagnosis of interconnects of random access memories

This paper presents an approach for the maximal diagnosis of all faults (stuck-at, open and short) in the interconnect of a random access memory (RAM); and the interconnect includes data and address lines. This approach accomplishes maximal diagnosis under a complex model in which the lines in the interconnect of the RAM can be affected by multiple faults. Maximal diagnosis consists of detection and location of all diagnosable faults as well as type identification of multiple faults affecting each line. The proposed algorithm (referred to as the Improved Maximal Diagnosis Algorithm, or IMDA) requires max{n,m-1}+n+3 WRITE and max{n,m}+2n READ, where n is the number of address lines and m is the number of data lines. IMDA executes in three different steps: the first step diagnoses the data lines (and in particular the stuck-at faults); the second step accomplishes maximal diagnosis of the shorts (involving either the data lines only, or the data and address lines); and the third step completes the diagnosis of the address lines.     

铅基卤素钙钛矿阻变式存储器研究进展

随着数字通信在大数据以及物联网等领域的应用,推动了下一代存储设备的发展.阻变式存储器因其功耗低、尺寸可调、操作速度快等优点被认为是最有前景的信息存储器件之一.近年来,兼具成本低、带隙可调、载流子扩散长度长、离子迁移速率快、载流子迁移率高等优点的铅基卤素钙钛矿,在阻变式存储器领域引起了广泛关注.主要对铅基卤素钙钛矿阻变式...     

Improving retention properties by thermal imidization for polyimide-based nonvolatile resistive random access memories

In this study, a polyimide (PI) thin film was synthesized as a resistive layer for creating resistive random access memory (ReRAM). The switch between high- and low-resistance states is caused by the formation and dissociation of dipole direction and Schottky barrier. The impact of imidization on memory properties was evaluated in detail by clarifying the transmission mechanism, and reliability properties including retention and endurance were improved using thermal imidization. In addition, the proposed PI-based ReRAM demonstrated superior performance levels compared with those of electrochemical-metallization-based and valence-change-based ReRAMs, including higher R_ON/R_OFF ratio (> 10⁷) and lower operation energy (< 0.16 MV/cm).     

Advances in ALOHA random multiple access techniques

Since the 1970s random multiple access techniques have made big progress and found a wide application in modern communication systems. In this paper we review the evolution of ALOHA random multiple access techniques: from pure ALOHA to Spread ALOHA. We introduce the principle of Spread ALOHA, investigate the relationship between spread‐spectrum CDMA and Spread ALOHA, and discuss the prospective applications of Spread ALOHA. Copyright © 2000 John Wiley & Sons, Ltd.     

Testing of static random access memories by monitoring dynamic power supply current

This article presents a correlation between dynamic power supply current and pattern sensitive faults in SRAMs. It is shown that the dynamic power supply current provides a window for observing the internal switching behavior of the memory cells. Switching of the logic state of a memory cell results in a transient current pulse in the power supply rails. A new current-testable SRAM structure is presented which can be used to isolate normal current transients from those resulting from pattern sensitivity. The new structure differs from traditional SRAM structures only in the way that power is distributed to the cells. The new structure allows for very high coverages of disturb-type pattern sensitivity using a simple algorithm of length 5n where n is the number of cells.     

Performance analysis and enhancement of random access process in cellular-IoT

Narrowband Internet of things (NB-IoT) and enhanced machine-type communications (eMTC) are two new IoT-oriented solutions introduced by the 3rd generation partnership project (3GPP) in Rel-13. In order to meet the new requirements (such as long battery life, low device cost, low deployment cost, extended coverage and support for a massive number of devices) of machine-to-machine (M2M) communication, these two technologies had some improvements on the random access (RA) mechanism compared to traditional long term evolution (LTE). For example, repetition of preamble transmission and coverage enhancement (CE) levels have been proposed to offer communication services in a wider area. In addition, NB-IoT has adopted a new spectrum allocation method and proposed a new type of preamble structure to meet the requirement of big amount of connections. We summarize details and differences of the RA process in LTE, eMTC and NB-IoT. Afterwards, as an improvement, we propose an enhanced access protocol for NB-IoT. Finally, performance analysis and comparison are presented in terms of access success probability, average access delay, access spectrum efficiency and average number of RA attempts.     

Yield enhancement and manufacturing throughput of redundant memories by repairability/unrepairability detection

In this article, yield enhancement and manufacturing throughput of large repairable memories are analyzed. These objectives are met by repairability/unrepairability detection. Initially two new techniques for detection of memory chips with redundancy are presented. Initially, a heuristic, yet efficient approach is proposed. This first approach is based on finding a very good approximation to the minimum covering set. An algorithm, which executes in quadratic time with respect to the largest dimension of the memory, is presented. This algorithm is executed off-line, that is, when the memory has been fully diagnosed. New conditions for detection are presented and fully analyzed. These are based on a more accurate estimation of the regions of repairability and unrepairability. Hence, this results in a reduction of the uncertainty region, where the status of a memory cannot be established without executing a fully exhaustive search algorithm. The second approach to repairability/unrepairability detection is based on a more complex covering relationship, namely the generalized leading element. A model for manufacturing throughput of large repairable memories is presented.A new repair algorithm which utilizes a ternary tree approach, is also presented. This repair algorithm is perfect in the sense that it finds the optimal repair-solution (whenever one exists) after the memory has not been diagnosed unrepairable.Illustrative examples and simulation results show that considerable improvements for average and the worst-case analysis over existing techniques can be achieved.This research was supported in part by grants from AT&T and NATO.     

Priority-based random access scheme for S-PCN

A novel random multiple access technique, priority-based fast access (PBFA), is proposed by the authors to reduce the access delay of delay-sensitive random access (RA) packets in S-PCNs. The approach, based on the concept of good channel transmission (GCT), can significantly improve the delay performance, in particular, for those delay-sensitive packets, of a slotted ALOHA (S-ALOHA) random access channel (RACH) in a satellite fading environment. In addition, the time capture effect is exploited to further improve the RACH performance     

On-chip error correcting techniques for new-generation flash memories

In new-generation flash memories, issues such as disturbs and data retention become more and more critical as a consequence of reduced cell size and decreased oxide thickness. Furthermore, the progressive increase in the cell count within a single die tends to decrease device reliability. In particular, reliability issues turn out to be more critical in multilevel (ML) flash memories, due to the reduced spacing between adjacent programmed levels. It is therefore deemed that the use of on-chip error correction codes (ECCs) will gain widespread acceptance in large-capacity flash memories. ECCs for flash memories must have very fast and compact encoding/decoding circuitry so as to have a minimum impact on memory access time. The area penalty due to check cells must also be minimized. Moreover, specific codes must be developed for ML storage. This paper presents error control coding techniques and schemes for new-generation flash memories, focusing on ML devices. The basic concepts of error control coding are reviewed, and the on-chip ECC design procedure is analyzed. Dedicated codes such as polyvalent ECCs, able to correct data stored in ML memories working at a variable number of bits per cell, and bit-layer organized ECCs are described.     

Layout-synthesis techniques for yield enhancement

Several yield-enhancement techniques are proposed for the last two stages of VLSI design, i.e., topological/symbolic and physical layout synthesis. Our approach is based on modifications of the symbolic/physical layout to reduce the sensitivity of the design to random point defects without increasing the area, rather than fault tolerance techniques. A layout compaction algorithm is presented and the yield improvement results of some industrial layout examples are shown. This algorithm has been implemented in a commercial CAD framework. Some routing techniques for wire length and via minimization are presented, and the results of wire length reduction in benchmark routing examples are shown. We demonstrate through topological optimization for PLA-based designs that yield enhancement can be applied even at a higher level of design abstraction. Experimental results show that it is possible to achieve significant yield improvements without increasing the layout area by applying the proposed techniques during layout synthesis     

Yield enhancement of bit level systolic array chips using fault tolerant techniques

Methods by which bit level systolic array chips can be made fault tolerant are discussed briefly. Using a simple analysis based on both Poisson and Bose-Einstein statistics we demonstrate that such techniques can be used to obtain significant yield enhancement. Alternatively, the dimensions of an array can be increased considerably for the same initial (nonfault tolerant) chip yield.     

Static random access memories based on resonant interband tunnelingdiodes in the InAs/GaSb/AlSb material system

We have fabricated SRAM's based on resonant interband tunneling diodes in the InAs/AlSb/GaSb material system. The bistability and the switching principles are demonstrated. Numerical simulations of the memory characteristics of the SRAM cell are performed and used for comparing with experiments. Several key issues involving the applications of the device are also discussed     

Asymmetric electric field enhancement in nanocrystal memories

The electrostatic model for nanocrystal memories is used to illustrate the fundamental difference of the metal nanocrystal memory in low-voltage program/erase (P/E) operations in comparison with semiconductor nanocrystal and trap-based memories. Due to repulsion of potential contours inside conductors, the metal nanocrystals will significantly enhance the electric field between the nanocrystal and the sensing channel set up by the control gate bias and, hence, can achieve much higher efficiency in low-voltage P/E. On the other hand, the electric field originated from the stored charge will only be slightly different for metal and semiconductor nanocrystal cases. We presented the electrostatic models by both approximate analytical formulation and three-dimensional numerical simulation in a nanocrystal array. Operations of P/E and read disturbance were analyzed for the cases of homogeneous charge distribution, silicon, and metal nanocrystals. In the P/E condition of +5/-5 V, the metal nanocrystal memory offers around 1.6 times higher peak fields than Si counterparts and almost three times higher than that from the one-dimensional model for homogeneous charge distribution. The field enhancement factor suggests the design criteria of oxide thickness, nanocrystal size, and spacing. The advantage of asymmetric field enhancement of metal nanocrystals will be even more prominent when high-K gate dielectrics are employed.     

Network-assisted diversity for random access wireless networks

A novel viewpoint to the collision resolution problem is introduced for wireless slotted random access networks. This viewpoint is based on signal separation principles borrowed from signal processing problems. The received collided packets are not discarded in this approach but are exploited to extract each individual user packet information. In particular, if k users collide in a given time slot, they repeat their transmission for a total of k times so that k copies of the collided packets are received. Then, the receiver has to resolve a k×k source mixing problem and separate each individual user. The proposed method does not introduce throughput penalties since it requires only k slots to transmit k colliding packets. Performance issues that are related to the implementation of the collision detection algorithm are studied. The protocol's parameters are optimized to maximize the system throughput