Flexible Chip-on-Flex (COF) and embedded Chip-in-Flex (CIF) packages by applying wafer level package (WLP) technology using anisotropic conductive films (ACFs)

Due to increasing demand for higher performance, greater flexibility, smaller size, and lighter weight in electronic devices, extensive studies on flexible electronic packages have been carried out. However, there has been little research on flexible packages by wafer level package (WLP) technology using anisotropic conductive films (ACFs) and flex substrates, an innovative packaging technology that requires fewer process steps and lower process temperature, and also provides flexible packages. This study demonstrated and evaluated the reliability of flexible packages that consisted of a flexible Chip-on-Flex (COF) assembly and embedded Chip-in-Flex (CIF) packages by applying a WLP process.The WLP process was successfully performed for the cases of void-free ACF lamination on a 50 μm thin wafer, wafer dicing without ACF delamination, and a flip-chip assembly which showed stable bump contact resistances. The fabricated COF assembly was more flexible than the conventional COF whose chip thickness is about 700 μm. To evaluate the flexibility of the COF assembly, a static bending test was performed under different bending radiuses: 35 mm, 30 mm, 25 mm, and 20 mm. Adopting optimized bonding processes of COF assembly and Flex-on-Flex (FOF) assembly, CIF packages were then successfully fabricated. The reliability of the CIF packages was evaluated via a high temperature/humidity test (85 °C/85% RH) and high temperature storage test (HTST). From the reliability test results, the CIF packages showed excellent 85 °C/85% RH reliability. Furthermore, guideline of ACF material property was suggested by Finite Element Analysis (FEA) for better HTST reliability.     

A study on thermal cycling (T/C) reliability of anisotropic conductive film (ACF) flip chip assembly for thin chip-on-board (COB) packages

In this work, thermal cycling (T/C) reliability of anisotropic conductive film (ACF) flip chip assemblies having various chip and substrate thicknesses for thin chip-on-board (COB) packages were investigated. In order to analyze T/C reliability, shear strains of six flip chip assemblies were calculated using Suhir’s model. In addition, correlation of shear strain with die warpage was attempted.The thicknesses of the chips used were 180 μm and 480 μm. The thicknesses of the substrates were 120, 550, and 980 μm. Thus, six combinations of flip chip assemblies were prepared for the T/C reliability test. During the T/C reliability test, the 180 μm thick chip assemblies showed more stable contact resistance changes than the 480 μm thick chip assemblies did for all three substrates. The 550 μm thick substrate assemblies, which had the lowest CTE among three substrates, showed the best T/C reliability performance for a given chip thickness.In order to investigate what the T/C reliability performance results from, die warpages of six assemblies were measured using Twyman–Green interferometry. In addition, shear strains of the flip chip assemblies were calculated using measured material properties of ACF and substrates through Suhir’s 2-D model. T/C reliability of the flip chip assemblies was independent of die warpages; it was, however, in proportion to calculated shear strain. The result was closely related with material properties of the substrates. The T/C reliability of the ACF flip chip assemblies was concluded to be dominatingly dependent on the induced shear strains of ACF layers.     

Development of chip-on-flex bonding using Sn-based bumps and non-conductive adhesive

We developed a reliable and low cost chip-on-flex (COF) bonding technique using Sn-based bumps and a non-conductive adhesive (NCA). Two types of bump materials were used for the bonding process: Sn bumps and Sn–Ag bumps. The bonding process was performed at 180 °C for 10 s using a thermo-compression bonder after dispensing the NCA. Sn-based bumps were easily deformed to contact Cu pads during the bonding process. A thin layer of Cu₆Sn₅ intermetallic compound was observed at the interface between Sn-based bumps and Cu pads. After bonding, electrical measurements showed that all COF joints had very low contact resistance, and there were no failed joints. To evaluate the reliability of COF joints, high temperature storage tests (150 °C, 1000 h), thermal cycling tests (−25 °C/+125 °C, 1000 cycles) and temperature and humidity tests (85 °C/85% RH, 1000 h) were performed. Although contact resistance was slightly increased after the reliability test, all COF joints passed failure criteria. Therefore, the metallurgical bond resulted in good contact and improved the reliability of the joints.     

Evaluation of hybrid bonding technology of single-micron pitch with planar structure for 3D interconnection

In this paper, we describe hybrid bonding technology of single-micron pitch with planar structure for three-dimensional (3D) interconnection. Conventionally, underfill method utilizing capillary force was used after the bonding of microbump. However, the filling becomes insufficient in a gap less than 10 μm between chips or bumps. One promising technology is the hybrid bonding technology that microbumps and an adhesive can be simultaneously bonded. To realize a single-micron pitch hybrid bonding, we fabricated a planar structure that consists of 8 μm-pitch Cu/Sn microbumps and a non-conductive film (NCF) by a chemical mechanical polishing (CMP) of resin. After planarization, the Cu/Sn bumps and the NCF were simultaneously bonded at 250 °C for 60 s. Cross-sectional scanning electron microscope (SEM) images and energy dispersive X-ray spectroscopy (EDX) images show that the adhesive resin on the bump surface was successfully removed by the CMP. In addition, SEM images of the bonded sample show that the adhesive filled the 2.5-μm gap between the chip and substrate. The Cu/Sn bumps were properly bonded in a corner on the chip. The proposed bonding method is expected to enable single-micron pitch interconnection for ultra-high density 3D LSI of next generation.     

A novel bumping process for fine pitch Sn–Cu lead-free plating-based flip chip solder bumps

Electroplating is the best process for the manufacture of fine pitch flip chip solder bumps. However, certain unstable electroplating parameters usually cause poorer coplanarity, which affects packaging reliability and yield. This paper attempts to utilize a CMP-like polisher to reduce the nonuniform height deviation after electroplating. The optimization of three major polishing parameters—pad hardness, loading pressure, and polishing speed—enables the polisher to have a higher material removal rate (MRR) and an easier manipulation as compared with chemical mechanical polishing (CMP). After polishing at a pitch size of 100 μm, the overall coplanarity could be decreased sharply from 33±2.5 μm (coplanarity=7.5%) to 28±1 μm (coplanarity=3%) and it even reached 26±0.5 μm (coplanarity=1%) after reflow.     

Highly reliable flip-chip-on-flex package using multilayered anisotropic conductive film

Anisotropic conductive film (ACF) has been used as interconnect material for flat-panel display module packages, such as liquid crystal displays (LCDs) in the technologies of tape automated bonding (TAB), chip-on-glass (COG), chip-on-film (COF), and chip-on-board (COB). Among them, COF is a relatively new technology after TAB and COG bonding, and its requirement for ACF becomes more stringent because of the need of high adhesion and fine-pitch interconnection. To meet these demands, strong interfacial adhesion between the ACF, substrate, and chip is a major issue. We have developed a multilayered ACF that has functional layers on both sides of a conventional ACF layer to improve the wetting properties of the resin on two-layer flex for better interface adhesion and to control the flow of conductive particles during thermocompression bonding and the resulting reliability of the interconnection using ACF. To investigate the enhancement of electrical properties and reliability of multilayered ACF in COF assemblies, we evaluated the performance in contact resistance and adhesion strength of a multilayered ACF and single-layered ACF under various environmental tests, such as a thermal cycling test (−55°C/+160°C, 1,000 cycles), a high-temperature humidity test (85°C/85% RH, 1,000 h), and a high-temperature storage test (150°C, 1,000 h). The contact resistance of the multilayered ACF joint was in an acceptable range of around a 10% increase of the initial value during the 85°C/85% RH test compared with the single-layered ACF because of the stronger moisture resistance of the multilayered ACF and flex substrate. The multilayered ACF has better adhesion properties compared with the conventional single-layered ACF during the 85°C/85% RH test because of the enhancement of the wetting to the surface of the polymide (PI) flex substrate with an adhesion-promoting nonconductive film (NCF) layer of multilayered ACF. The new ACF of the multilayered structure was successfully demonstrated in a fine-pitch COF module with a two-layer flex substrate.     

Surface and interface characterization of oxygen plasma activated anodic bonding of glass–ceramics to stainless steel

The anodic bonding of RAS glass–ceramics to stainless steel were carried out at 350–400 °C and 800–1000 V under atmosphere, the micro-topography and compositions of the bonding interfaces also were investigated. With the assistant of oxygen plasma activated, anodic bonding was achieved at 350 °C and 800 V for 23 min under atmosphere, and the anodic bonding strength was up to 1.23 MPa. Experiments results pointed out oxygen plasma could help forming the bonding with glass–ceramics to stainless steel, and the width of cation depletion layer about 50 μm, lithium iron oxide (LiFe₅O₈ and Li₅FeO₄) were observed on the surface of glass–ceramics after anodic bonding.     

Void-free and high-speed filling of through ceramic holes by copper electroplating

In order to achieve void-free and high-speed filling for through ceramic holes (TCHs) to prepare direct plated copper (DPC) ceramic substrates, copper electroplating technology combined with nano-carbon coating process was used in this work. The nano-carbon coating process was adopted to form a nano-carbon film as a conductive layer on the hole wall. For the TCH electroplating, an ameliorative plating additive mixture was proposed, which consists of accelerator thiazolyl dithio-propane sodium sulfonate (SH110), leveler nitrotetrazolium blue chloride (NTBC) and inhibitor polyethylene glycol (PEG, MW = 8000). Experimental results indicate that the optimized formula of the additives is 6 ppm SH110, 5 ppm NTBC, and 200 ppm PEG. By this optimized formula, the filling speed was further improved by duly increasing current densities. Consequently, TCHs with high aspect ratios (ARs) of 6.25 (500 μm depth and 80 μm diameter) were completely and void-free filled at the high current density of 1.5 ASD for 2 h, which promotes the development of vertical interconnection for DPC ceramic substrates and enhances their reliability for high power packages.     

Effect of active layer thickness on environmental stability of printed thin-film transistor

We have studied the effect of active layer thickness on the performance and environmental stability of the 6,13-bis(triisopropylsilylethynyl) pentacene (TIPS pentacene) thin-film transistor. The organic thin-film transistors (OTFTs) were fabricated by inkjet printing using a solution based TIPS pentacene. To get thick organic semiconductor, the surface of gate insulator was treated with n-octyltrichlorosilane (OTS-C₈) before jetting. The on-currents of the OTFT with ～1 μm active layer decreases a little in air, but the OTFT with 0.05 μm TIPS pentacene shows a significant degradation in drain currents.     

Non-conductive film with Zn-nanoparticles (Zn-NCF) for 40 μm pitch Cu-pillar/Sn–Ag bump interconnection

Non-conductive film with Zn nano-particles (Zn-NCF) is an effective solution for fine-pitch Cu-pillar/Sn–Ag bump interconnection in terms of manufacturing process and interfacial reliability. In this study, NCFs with Zn nano-particles of different acidity, viscosity, and curing speed were formulated and diffused Zn contents in the Cu pillar/Sn–Ag bumps were measured after 3D TSV chip-stack bonding. Amount of Zn diffusion into the Cu pillar/Sn–Ag bumps increased as the acidity of resin increased, as the viscosity of resin decreased, as the curing speed of resin decreased, and as the bonding temperature increased. Diffusion of Zn nano-particles into the Cu pillar/Sn–Ag bumps are maximized when the resin viscosity became lowered and the solder oxide layer was removed. To analyze the effects of Zn-NCF on IMC reduction, IMC height depending on aging time was measured and corresponding activation energies for IMC growth were calculated. For the evaluation of joint reliabilities, test vehicles were bonded using NCFs with 0 wt%, 1 wt%, 5 wt%, and 10 wt% of Zn nano-particles and aged at 150 °C up to 500 h. NCF with 10 wt% Zn nano-particle showed remarkable suppression in Cu₆Sn₅ and (Cu,Ni)₆Sn₅ IMC compared to NCFs with 0 wt%, 1 wt%, and 5 wt% of Zn nano-particles. However, in terms of Cu₃Sn IMC suppression, which is the most critical goal of this experiment NCFs with 1 wt%, 5 wt%, and 10 wt% showed an equal amount of IMC suppression. As a result, it was successfully demonstrated that the suppression of Cu–Sn IMCs was achieved by the addition of Zn nano-particles in the NCFs resulting an enhanced reliability performance in the Cu/Sn–Ag bumps bonding in 3D TSV interconnection.     

Vertical InGaN light-emitting diodes with Ag paste as bonding layer

Vertical InGaN-based light-emitting diodes (LEDs) were fabricated with a Si substrate using Ag paste as bonding layer. Vertical LEDs with Ag paste bonding layer were bonded with Si substrate at a low temperature of 140 °C. In addition to the low-temperature bonding process, the soft property of Ag paste could better alleviate thermal stress compared with conventional eutectic metal bonding layer such as Au–Sn. Under the same test conditions, these two LEDs showed similar optical and electrical properties and reliability. However, LEDs with Ag-paste bonding layer were fabricated through a low-temperature bonding process. The characteristic of soft solder enables a relatively wider process window, such as bonding pressure and temperature, and a higher yield as compared with the vertical LEDs with Au–Sn eutectic bonding layer.     

Effect of trace platinum additions on the interfacial morphology of Sn–3.8Ag–0.7Cu alloy aged for long hours

While the Sn–Ag–Cu (SAC) family of solders are considered good candidate as lead-free solder replacement materials, their relatively short processing history and application result in a host of materials as well as reliability problems. For good metallurgical bonding and electrical connection, a thin, even layer of intermetallic compound (IMC) is required but excessive growth of the IMC layer will cause various reliability problems. This is especially critical for miniaturized solder pitches in very large scale integration circuits. This work adopts the composite approach of adding 0.15 and 0.30 wt.% of Pt into Sn–3.8Ag–0.7Cu alloy to study the effect of these additions to the IMC layer thickness between the solder and substrate. Alloys were isothermally aged at 150 °C for up to 1000 h to observe contribution of Pt in suppressing excessive IMC growth. It was found that when more Pt was added to the alloy, the IMC layer became more even and continuous. Voids and IMC layer thickness were reduced. This is attributed to the role of Pt in replacing Cu in the solder and thus impeding excessive diffusion.     

Reliability challenges for barrier/liner system in high aspect ratio through silicon vias

The reliability results for barrier/liner systems in different high aspect ratio (5 × 50 μm) through silicon vias (TSV) are presented. Quite a few factors can influence the TSV barrier/liner reliability performance, including the TSV trench etch process, the oxide liner material/thickness, etc. The challenges for more advanced TSV technology nodes (e.g. 3 × 40 μm) are also discussed and possible solutions are proposed.     

Corrosion testing of anisotropic conductive adhesive interconnections on FR4, liquid crystal polymer and polyimide substrates

Anisotropic conductive adhesive films (ACF) have been widely studied for numerous applications. However, their resistance to corrosion in highly corrosive environments has been studied only very little. This study investigated the reliability and behaviour of ACFs in corrosive salt spray environment. ACF was used to attach flip chip (FC) components on FR4, liquid crystal polymer (LCP) and polyimide (PI) substrates and the FC packages were subjected to a salt spray test lasting 3000 h. The FC packages had daisy chain structures which were measured continuously in real time during testing. After testing cross sections of the tested packages were examined using an optical microscope and a scanning electron microscope (SEM). Most components failed during the test and the results showed significant differences between the various substrate materials. The LCP substrate performed considerably better than the other substrates and the PI substrate proved to have the poorest reliability. Corrosion of the pads on the substrates as well as open joints was seen in all substrate materials. The corrosion behaviour as well as the differences between the substrates showed that the substrate structure and material are critical factors in corrosive environments and should be carefully considered. The reliability of the ACF FC package with the LCP substrate was found to be good, as the test was very severe and no failures occurred during the first 625 h of testing and only 20% failed during the first 1000 h.     

RF measurements to pinpoint defects in inkjet-printed,thermally and mechanically stressed coplanar waveguides

In this work 10-GHz-band RF measurement and microscopy characterizations were performed on thermally and mechanically long-term-stressed coplanar waveguides (CPW) to observe electrical and mechanical degradation in 1-mm-thick PPO/PPE polymer substrates with inkjet-printed Ag conductors. The structure contained two different CPW geometries in a total of 18 samples with 250/270 μm line widths/gaps and 670/180 μm line widths/gaps. A reliability test was carried out with three sets. In set #1 three 250 μm and three 670 μm lines were stored in room temperature conditions and used as a reference. In set #2 six samples were thermally cycled (TC) for 10,000 cycles, and in set #3 six samples were thermally cycled and bent with 6 mm and 8 mm bending diameters.Thermal stressing was done by cycling the samples in a thermal cycling test chamber operating at 0/100 °C with 15-minutes rise, fall, and dwell times, resulting in a one-hour cycle. The samples were analyzed during cycling breaks using a vector network analyzer (VNA). In addition to optical microscopy, field emission scanning electron microscopy (FESEM) and atomic force microscopy (AFM) imaging were used to mechanically characterize the structures.The results showed that the line width of 670 μm had better signal performance and better long-term reliability than the line width of 250 μm. In this study, the average limit for proper RF operation was 2500 thermal cycles with both line geometries. The wide CPW lines provided more stable characteristics than the narrow CPW lines for the whole 10,000-cycle duration of the test, combined with repeated bending with a maximum bending radius of 6 mm. A phenomenon of nanoparticle silver protruding from cracks in the print of the bent samples was observed, as well as fracturing of the silver print in the CPW lines.     

Enhanced organic ferroelectric field effect transistor characteristics with strained poly(vinylidene fluoride-trifluoroethylene) dielectric

Poly(vinylidene fluoride-trifluoroethylene) (70–30 mol%) was used as the functional dielectric layer in organic ferroelectric field effect transistors (FeFET) for non-volatile memory applications. Thin P(VDF-TrFE) film samples spin-coated on metallized plastic substrates were stretch-annealed to attain a topographically flat-grain structure and greatly reduce the surface roughness and current leakage of semi-crystalline copolymer film, while enhancing the preferred β-phase of the ferroelectric films. Resultant ferroelectric properties (P_R = |10| μC/cm², E_C = |50| MV/m) for samples simultaneously stretched (50–70% strain) and heated below the Curie transition (70 ^oC) were comparable to those resulting from high temperature annealing (>140 ^oC). The observed enhancements by heating and stretching were studied by vibration spectroscopy and showed mutual complementary effects of both processes. Organic FeFET fabricated by thermal evaporating pentacene on the smooth P(VDF-TrFE) films showed substantial improvement of semiconductor grain growth and enhanced electrical characteristics with promising non-volatile memory functionality.     

Reliability of Diode-Integrated SiC Power MOSFET(DioMOS)

Status of the reliability study on silicon carbide (SiC) power MOS transistors is presented. The SiC transistors studied are diode-integrated MOSFETs (DioMOS) in which a highly doped n-type epitaxial channel layer formed underneath the gate oxide acts as a reverse diode and thus an external Schottky barrier diode can be eliminated. The novel MOS device can reduce the total area of SiC leading to potentially lower cost as well as the size of the packaging. After summarizing the issues on reliability of conventional SiC MOS transistors, the improvements by the newly proposed DioMOS with blocking voltage of 1200 V are presented. The I–V characteristic of the integrated reverse diode is free from the degradation which is typically observed in conventional pn-junction-based body diode in SiC MOS transistors. The improved quality of the MOS gate in the DioMOS results in very stable threshold voltage within its variation less than 0.1 V even after 2000 h of serious gate voltage stresses of + 25 V and − 10 V at 150 °C. High temperature reverse bias test (HTRB) shows very stable off-state and gate leakage current up to 2000 h under the drain voltage of 1200 V at 150 °C. These results indicate that the presented DioMOS can be applied to practical switching systems free from the reliability issues.     

Theoretical Prediction and Experimental Measurement of the Degree of Cure of Anisotropic Conductive Films (ACFs) for Chip-On-Flex (COF) Applications

The degree of cure of anisotropic conductive films (ACFs) was theoretically predicted and experimentally measured to investigate the effect of the degree of cure of ACFs on the electrical and mechanical stability of ACF joints and the␣reliability of chip-on-flex (COF) assemblies. The cure reaction of ACFs, observed by an isothermal differential scanning calorimetry (DSC) analysis, followed an autocatalytic cure mechanism, and the degree of cure of ACFs as a function of time and temperature was mathematically derived from an autocatalytic cure kinetics model. To simulate the ACF temperature field accurately during the COF bonding process, the thermal properties of the ACF such as the thermal diffusivity (α), specific heat capacity (C _p), and thermal conductivity (λ) were characterized experimentally. The degrees of cure of ACFs as functions of the bonding time during the COF bonding process were theoretically predicted by the incorporation of autocatalytic kinetics modeling and ACF temperature simulation. The predicted degrees of cure of ACFs were well matched with the experimental data measured by attenuated total reflectance/Fourier-transform infrared (ATR/FT-IR) analysis. The contact resistances of the ACF joints and the peel adhesion strengths of the COF assemblies were evaluated for electrical and mechanical interconnection stability. According to these results, the ACF contact resistances decreased and the ACF peel adhesion strengths increased as the degree of cure of ACFs increased. In addition, to investigate the effect of the degree of cure of ACFs on the reliability of COF assemblies, an 85°C/85% relative humidity (85°C/85% RH) test was performed. These results showed that the reliability of COF assemblies also strongly depends on the degree of cure of the ACFs.     

Numerical analysis on the LDMOS with a double epi-layer and trench electrodes

We proposed a new lateral double-diffused MOS (LDMOS) structure employing a double p/n epitaxial layer, which is formed on p⁻ substrates. Trenched gate and drain are also employed to obtain uniform and high drift current density. The breakdown voltage and the specific on-resistance of the proposed LDMOS are numerically calculated by using a two-dimensional (2D) device simulator, Medici. The n⁻ drift region and upper p⁻ region of the proposed LDMOS are fully depleted in off-states employing the RESURF technique. The simulation results show that the breakdown voltage is 142 V and specific on-resistance is 183 mΩ mm² when the cell pitch of the LDMOS is 7.5 μm. The proposed LDMOS shows better trade-off characteristics than the previous results.     

Thermo-mechanical reliability of a multi-walled carbon nanotube-incorporated solderable isotropic conductive adhesive

Carbon nanotubes (CNTs) are considered as ideal candidates for the reinforcement of polymer composites due to their superior physical properties. In this paper, in order to investigate the influence of multi-walled carbon nanotubes (MWCNTs) on the reliability properties of solderable isotropic conductive adhesives (SICAs) with a low-melting-point alloy (LMPA), two types of SICAs (with 0.03 wt.% MWCNTs and without MWCNT) were formulated. Thermal shock (− 55 to 125 °C, 1000 cycles) and high-temperature and high-humidity (85 °C, 85% RH, 1000 h) tests were conducted on these samples. The SICA assemblies with and without MWCNTs showed stable electrical reliability properties during reliability testing; this stability was due to the formation of excellent metallurgical interconnection between corresponding metallization by the molten LMPA fillers. Although the mechanical pull strength of SICA assemblies decreased after thermal aging, due to the excessive layer growth and planarization of the IMCs, the SICA with MWCNTs showed enhanced mechanical reliability properties compared with the SICA samples without MWCNTs. This improvement in performance was caused by the enhancement effect of the MWCNTs. These results demonstrate that MWCNTs within SICAs can enhance the reliability properties of SICA joints due to their outstanding physical properties.