A new technique in LDMOS transistors to improve the breakdown voltage and the lattice temperature

A new technique for high breakdown voltage of the LDMOS device is proposed in this paper. The main idea in the proposed technique is to insert the P⁺ silicon windows in the buried oxide at the interface of the n-drift to improve the breakdown voltage, electric field and maximum lattice temperature. The proposed structure is called as P⁺ window LDMOS (PW-LDMOS). It is shown by extending the depletion region between the P⁺ windows and the n-drift region, the breakdown voltage of PW-LDMOS increases to 405 V from 84 V of the conventional LDMOS on 1 µm silicon layer and 2 µm buried oxide layer. Also, effective values of doping, length, and depth of P⁺ window are investigated in the breakdown voltage. Moreover, a self-heating-effect is alleviated by the silicon windows in comparison with the conventional LDMOS. All the achieved results have been extracted by two-dimensional and two-carriers simulator ATLAS.     

Growth enhancement and field emission characteristics of one-dimensional 3,4,9,10-perylenetetracarboxylic dianhydride nanostructures on pillared titanium substrate

We have utilized the π–π interactions between 3,4,9,10-perylenetetracarboxylic dianhydride (PTCDA) molecules and temperature-induced morphology changes to synthesize one-dimensional (1D) nanostructures of PTCDA on a heated (ca. 100 °C) titanium substrate through vacuum sublimation. Because of the pillared Ti structures and the presence of reactive Ti–Cl sites, the titanium substrate played a crucial role in assisting the PTCDA molecules to form 1D nanostructures. The average diameter of the nanofibers deposited on the Ti-CVD substrate, a Ti substrate formed by chemical vapor deposition (CVD), at 100 °C was ca. 84 nm, with lengths ranging from 100 nm to 3 μm. When the PTCDA nanofibers were biased under vacuum, the emission current remained stable. The turn-on electric field for producing a current density of 10 μA/cm² was 8 V/μm. The maximum emission current density was 1.3 mA/cm², measured at 1100 V (E = 11 V/μm). From the slope of the straight line obtained after plotting ln(J/E²) versus 1/E, we calculated the field enhancement factor β to be ca. 989. These results demonstrate the PTCDA nanofibers have great potential for applicability in organic electron-emitting devices.     

A low voltage SANOS nonvolatile semiconductor memory (NVSM) device

In this paper, we present a new Polysilicon–Aluminum Oxide–Nitride–Oxide–Silicon (SANOS) device structure suitable for future nonvolatile semiconductor memories. Replacing SiO₂ with a high-K material, Al₂O₃ (K_f = 9) as the top blocking layer of the conventional SONOS device increases the electric field across the tunnel oxide, while reducing the electric field across the blocking layer with its dielectric constant during write and erase operations. Therefore, this new device can achieve lower programming voltages and faster programming speed than the conventional SONOS device. We have fabricated SANOS capacitors with 2 nm tunnel oxide, 5 nm silicon nitride and 8 nm aluminum oxide and studied the programming speed and charge retention characteristics of the new devices. These new SANOS devices achieve a 2 V reduction in the programming voltages with 2.1 V initial memory window.     

Operational frequency degradation induced trapping in scaled GaN HEMTs

Cut-off frequency increase from 12.1 GHz to 26.4 GHz, 52.1 GHz and 91.4 GHz is observed when the 1 μm gate length GaN HEMT is laterally scaled down to L_G = 0.5 μm, L_G = 0.25 μm and L_G = 0.125 μm, respectively. The study is based on accurately calibrated transfer characteristics (I_D-V_GS) of the 1 μm gate length device using Silvaco TCAD. If the scaling is also performed horizontally, proportionally to the lateral (full scaling), the maximum drain current is reduced by 38.2% when the gate-to-channel separation scales from 33 nm to 8.25 nm. Degradation of the RF performance of a GaN HEMT due to the electric field induced acceptor traps experienced under a high electrical stress is found to be about 8% for 1 μm gate length device. The degradation of scaled HEMTs reduces to 3.5% and 7.3% for the 0.25 μm and 0.125 gate length devices, respectively. The traps at energy level of E_T = E_V + 0.9 eV (carbon) with concentrations of N_IT = 5 × 10¹⁶cm^− 3, N_IT = 5 × 10¹⁷cm^− 3 and N_IT = 5 × 10¹⁸cm^− 3 are located in the drain access region where highest electrical field is expected. The effect of traps on the cut-off frequency is reduced for devices with shorter gate lengths down to 0.125 μm.     

Characterization of scaled MANOS nonvolatile semiconductor memory (NVSM) devices

We have modeled and characterized scaled Metal–Al₂O₃–Nitride–Oxide–Silicon (MANOS) nonvolatile semiconductor memory (NVSM) devices. The MANOS NVSM transistors are fabricated with a high-K (K_A = 9) blocking insulator of ALD deposited Al₂O₃ (8 nm), a LPCVD silicon nitride film (8 nm) for charge-storage, and a thermally grown tunneling oxide (2.2 nm). A low voltage program (+8 V, 30 μs) and erase (?8 V, 100 ms) provides an initial memory window of 2.7 V and a 1.4 V window at 10 years for an extracted nitride trap density of 6 × 10¹⁸ traps/cm³ eV. The devices show excellent endurance with no memory window degradation to 10⁶ write/erase cycles. We have developed a pulse response model of write/erase operations for SONOS-type NVSMs. In this model, we consider the major charge transport mechanisms are band-to-band tunneling and/or trap-assisted tunneling. Electron injection from the inversion layer is treated as the dominant carrier injection for the write operation, while hole injection from the substrate and electron injection from the gate electrode are employed in the erase operation. Meanwhile, electron back tunneling is needed to explain the erase slope of the MANOS devices at low erase voltage operation. Using a numerical method, the pulse response of the threshold voltages is simulated in good agreement with experimental data. In addition, we apply this model to advanced commercial TANOS devices.     

Silicon-on-insulator power integrated circuits

A power integrated circuit process has been developed, based on silicon-on-insulator, which allows intelligent CMOS control circuitry to be placed alongside integrated high-voltage power devices. A breakdown voltage of 335 V has been obtained by using a silicon layer of 4 μm thickness together with a buried oxide layer of 3 μm thickness. The respective LDMOS specific on-resistance and LIGBT on-state voltage for this breakdown voltage were 148 mΩ cm² and 3.9 V, respectively.     

Reduced contact resistance and highly stable operation in polymer thin-film transistor with aqueous MoOx solution contact treatment

We report on a newly developed solution process using MoO₃ for reducing source and drain (S/D) electrodes in organic thin-film transistor (TFT). By taking advantage of the difference in surface wettability between the gate dielectric layer and the S/D electrodes, the electrode treatment using the MoO_x solution was applied to polymer TFT with short channel lengths less than 10 μm. The contact resistance was noticeably reduced at the interface of the S/D electrodes in a polymer TFT using a pBTTT-C16. Furthermore, the field effect mobility for this TFT was enhanced from 0.03 to 0.1 cm²/V s. Most notably, the threshold voltage (V_th) shift under gated bias stress was less than 0.2 V after 10⁵ s, which is comparable to that of conventional poly crystalline Si TFT.     

Source/drain metallization effects on the specific contact resistance of indium tin zinc oxide thin film transistors

We report on the specific contact resistance of interfaces between thin amorphous semiconductor Indium Tin Zinc Oxide (ITZO) channel layers and different source/drain (S/D) electrodes (Al, ITO, and Ni) in amorphous oxide thin film transistors (TFTs) at different channel lengths using a transmission line model. All the contacts showed linear current–voltage characteristics. The effects of different channel lengths (200–800 μm, step 200 μm) and the contact resistance on the performance of TFT devices are discussed in this work. The Al/ITZO TFT samples with the channel length of 200 μm showed metallic behavior with a linear drain current-gate voltage (I_D–V_G) curve due to the formation of a conducting channel layer. The specific contact resistance (ρ_C) at the source or drain contact decreases as the gate voltage is increased from 0 to 10 V. The devices fabricated with Ni S/D electrodes show the best TFT characteristics such as highest field effect mobility (16.09 cm²/V·s), ON/OFF current ratio (3.27×10⁶), lowest sub-threshold slope (0.10 V/dec) and specific contact resistance (8.62 Ω·cm² at V_G=0 V). This is found that the interfacial reaction between Al and a-ITZO semiconducting layer lead to the negative shift of threshold voltage. There is a trend that the specific contact resistance decreases with increasing the work function of S/D electrode. This result can be partially ascribed to better band alignment in the Ni/ITZO interface due to the work function of Ni (5.04–5.35 eV) and ITZO (5.00–6.10 eV) being somewhat similar.     

105 nm Gate length pMOSFETs with high-K and metal gate fabricated in a Si process line on 200 mm GeOI wafers

We report on the fabrication and electrical characterization of deep sub-micron (gate length down to 105 nm) GeOI pMOSFETs. The Ge layer obtained by hetero-epitaxy on Si wafers has been transferred using the Smart Cut^TM process to fabricate 200 mm GeOI wafers with Ge thickness down to 60–80 nm. A full Si MOS compatible pMOSFET process was implemented with HfO₂/TiN gate stack. The electrical characterization of the fabricated devices and the systematic analysis of the measured performances (I_ON, I_OFF, transconductance, low field mobility, S, DIBL) demonstrate the potential of pMOSFET on GeOI for advanced technological nodes. The dependence of these parameters have been analyzed with respect to the gate length, showing very good transport properties (μ_h ～ 250 cm²/V/s, I_ON = 436 μA/μm for L_G = 105 nm), and OFF current densities comparable or better than those reported in the literature.     

Planar copper-tin inter-metallic film formation on strained substrates

This paper presents the results of four-point bending tests investigating the effects of substrate strain on the growth ɛ of interfacial Cu–Sn inter-metallic compounds (IMCs). Test specimens were cut into strips, 27.5 mm in length and 5 mm in width, from 4 in. double polished silicon wafers. A very thin adhesion layer (Ta) was deposited on the silicon substrate by sputtering followed by a 10 μm thick layer of copper using electroplating. Finally, a 30 μm tin layer was deposited over the copper film also by electroplating. Samples were then placed in a furnace at 200 °C to undergo bending in order to introduce in-plane strain under tension or compression. Control samples also underwent the same treatment without applied strain. Our aim was to investigate the influence of substrate strain and aging time on the formation of IMCs (1.54 × 10⁻⁴, 2.3 × 10⁻⁴ and 3.46 × 10⁻⁴). The thickness and separation of each phase (Cu₃Sn) and η (Cu₆Sn₅) are clearly visible in scanning electron microscope images. Compressive strain and tensile strain both increased the thickness of the IMC layer during the aging process; however, the effects of compressive strain were more pronounced than those of tensile strain. We hypothesize that the increase in IMC thickness is related to the strain enhanced out-diffusion of Cu towards the solder as well as strain in the underlying lattice at the diffusion interface.     

A novel method to improve cell endurance window in source-side injection split gate flash memory

To enhance cell endurance window of a split gate flash memory, we used a ramp pulse with long rising time to replace the conventional square pulse for programming. The change is based on the study of the electric field at electron injection point (E_G) related to programming time. Statistic measurements on various samples including different technologies, cell locations (even or odd) and rise times were done. The results confirm that the read currents shift under erase state (ΔI_r1) could be improved significantly with an acceptable programming speed by the proposed method.For example, as increasing the rising time from 0.1 μs to 20 μs for the conventional square pulse and the ramp pulse respectively, after 1 M cycling the ΔI_r1 is reduced from 64.8% to 36.2% with an acceptable minimum programming time of 12.5 μs.     

Organic light-emitting diodes based on an ambipolar single crystal

Slice-like organic single crystals of 1,4-bis(2-cyano-2-phenylethenyl)benzene (BCPEB) are grown by the physical vapor transport (PVT) method, and exhibit a very high photoluminescence quantum efficiency (Φ_PL) of 75%. The ambipolar behavior of BCPEB single crystals are confirmed using the time of flight technique. The high efficiency and balanced (μ_h = 0.059 cm²/Vs and μ_e = 0.070 cm²/Vs) carriers’ mobility imply that the BCPEB single crystal is a promising light-emitting layer in the diodes structure. Intense green electroluminescence (EL) from a diode has been successfully demonstrated at an applied electric field of 2 × 10⁵ V/cm.     

Enhanced field emission and hysteresis characteristics of aligned carbon nanotubes with Ti decoration

The field emission behavior of aligned carbon nanotubes (CNTs) is remarkably improved by decorating their surfaces with Ti nanoparticles through a sputtering process. The CNT/Ti(4 nm) sample shows a low turn-on field of 0.63 V/μm at 10 μA/cm², low threshold field of 1.06 V/μm at 1 mA/cm², and maximum field emission current density of 23 mA/cm² at 1.80 V/μm. The enhanced field emission properties of the CNT/Ti samples are attributed to the added defect sites and Ti nanoparticles, which increase the field enhancement factor and density of emission sites. Stability measurements indicate that the Ti coating, which acts as a protective layer, also strengthens the field emission stability of the CNT arrays. Moreover, the extent of hysteresis in the current–voltage sweep highly depends on the voltage-sweep speed.     

The effect of gate overlap lightly doped drains on low temperature poly-Si thin film transistors

Low temperature polycrystalline silicon (LTPS) thin-film transistors (TFTs) have a high carrier mobility that enables the design of small devices that offer large currents and fast switching speeds. However, the electrical characteristics of the conventional self-aligned polycrystalline silicon (poly-Si) TFTs are known to present several undesired effects, such as large leakage currents, the kink effect, and the hot-carrier effect. For this paper, LTPS TFTs were fabricated, and the SiN_x/SiO₂ gate dielectrics and the effect of the gate-overlap lightly doped drain (GOLDD) were analyzed in order to minimize these undesired effects. GOLDD lengths of 1, 1.5 and 2 μm were used, while the thickness of the gate dielectrics (SiN_x/SiO₂) was fixed at 65 nm (40 nm/25 nm). The electrical characteristics show that the kink effect is reduced in the LTPS TFTs using a more than 1.5 μm of GOLDD length. The TFTs with the GOLDD structure have more stable characteristics than the TFTs without the GOLDD structure under bias stress. The degradation from the hot-carrier effect was also decreased by increasing the GOLDD length. After applying the hot-carrier stress test, the threshold voltage variation (ΔV_TH) was decreased from 0.2 V to 0.06 V by the increase of the GOLDD length. The results indicate that the TFTs with the GOLDD structure were protected from the degradation of the device due to the decreased drain field. From these results it can be seen that the TFTs with the GOLDD structure can be applied to achieve high stability and high performance in driving circuit applications for flat-panel displays.     

Influence of deposition pressure on p-type a-Si:H window layer doped by trimethylboron for a-Si:H superstrate solar cell in plasma enhanced chemical vapor deposition

Wide bandgap (E_g) p-type window layer is very important for silicon based thin film solar cell to obtain high performance, especially high open-circuit voltage (V_OC). In this work, the influence of the deposition pressure on the properties of p-type a-Si:H window layer doped by trimethylboron (TMB) in plasma enhanced chemical vapor deposition (PECVD) was investigated systematically by transmission, Raman, and Fourier transform infrared (FTIR) spectroscopies. As a result, high performance hydrogenated amorphous silicon (a-Si:H) p–i–n superstrate solar cell with V_OC up to 927 mV was successfully achieved on Asahi Type-U SnO₂:F coated glass. In this case, excellent wide bandgap p-type a-Si:H window layer was fabricated under a mild deposition condition, including a low hydrogen dilution ratio (H₂/SiH₄) of 20, a relatively high deposition temperature of 220 °C, which was also adopted for the i-layer and n-layer deposition, and a moderate deposition pressure of about 160 Pa. We think it is the compromise between wide E_g and good microstructure quality of the p-layer that brings about the good solar cell performance. Such p-type window layer will be very helpful for the fabrication of a-Si:H solar cell, especially of the cell finished in a single PECVD chamber, due to its mild deposition condition.     

一种新的基于E-SIMOX衬底的PSOI高压器件

首次提出了一种新的采用E-SIMOX技术的界面电荷岛结构的PSOI高压器件(NI PSOI)。该结构在SOI器件介质层上界面注入形成一系列等距的高浓度N+区。器件外加高压时,纵向电场所形成的反型电荷将被未耗尽N+区内高浓度的电离施主束缚在介质层上界面,同时在下界面积累感应电子。详细研究NI PSOI工作机理及相关结构参数对BV的影响,在0.375μm介质层、2μm顶层硅上仿真获得188 V高耐压,较常规结构提高54.1%,其中附加场EI和ES分别达到190 V/μm和13.7 V/μm。     

Enhanced organic ferroelectric field effect transistor characteristics with strained poly(vinylidene fluoride-trifluoroethylene) dielectric

Poly(vinylidene fluoride-trifluoroethylene) (70–30 mol%) was used as the functional dielectric layer in organic ferroelectric field effect transistors (FeFET) for non-volatile memory applications. Thin P(VDF-TrFE) film samples spin-coated on metallized plastic substrates were stretch-annealed to attain a topographically flat-grain structure and greatly reduce the surface roughness and current leakage of semi-crystalline copolymer film, while enhancing the preferred β-phase of the ferroelectric films. Resultant ferroelectric properties (P_R = |10| μC/cm², E_C = |50| MV/m) for samples simultaneously stretched (50–70% strain) and heated below the Curie transition (70 ^oC) were comparable to those resulting from high temperature annealing (>140 ^oC). The observed enhancements by heating and stretching were studied by vibration spectroscopy and showed mutual complementary effects of both processes. Organic FeFET fabricated by thermal evaporating pentacene on the smooth P(VDF-TrFE) films showed substantial improvement of semiconductor grain growth and enhanced electrical characteristics with promising non-volatile memory functionality.     

Study on mobility enhancement in MOVPE-grown AlGaN/AlN/GaN HEMT structures using a thin AlN interfacial layer

Al_0.26Ga_0.74N/AlN/GaN high-electron-mobility transistor (HEMT) structures with AlN interfacial layers of various thicknesses were grown on 100-mm-diameter sapphire substrates by metalorganic vapor phase epitaxy, and their structural and electrical properties were characterized. A sample with an optimum AlN layer thickness of 1.0 nm showed a highly enhanced Hall mobility (μ_Hall) of 1770 cm²/Vs with a low sheet resistance (ρ_s) of 365 Ω/sq. (2DEG density n_s = 1.0 × 10¹³/cm²) at room temperature compared with those of a sample without the AlN interfacial layer (μ_Hall = 1287 cm²/Vs, ρ_s = 539 Ω/sq., and n_s = 0.9 × 10¹³/cm²). Electron transport properties in AlGaN/AlN/GaN structures were theoretically studied, and the calculated results indicated that the insertion of an AlN layer into the AlGaN/GaN heterointerface can significantly enhance the 2DEG mobility due to the reduction of alloy disorder scattering. HEMTs were successfully fabricated and characterized. It was confirmed that AlGaN/AlN/GaN HEMTs with the optimum AlN layer thickness show superior DC properties compared with conventional AlGaN/GaN HEMTs.     

Drivability improvement in Schottky barrier source/drain MOSFETs with strained-Si channel by Schottky barrier height reduction

Due to an extra barrier between source and channel, the drivability of Schottky barrier source/drain MOSFETs (SBMOSFETs) is smaller than that of conventional transistors. To reach the drivability comparable to the conventional MOSFET, the Schottky barrier height (SBH) should be lower than a critical value. It is expected that SBH can be effectively reduced by a bi-axially strain on Si. In this letter, p-channel MOSFETs with PtSi Schottky barrier source/drain, HfAlO gate dielectric, HfN/TaN metal gate and strained-Si channel are demonstrated for the first time using a simplified low temperature process. Devices with the channel length of 4 μm have the drain current of 9.5 μA/μm and the transconductance of 14 μS/μm at V_gs − V_th = V_ds = −1 V. Compared to the cubic Si counterpart, the drain current and the transconductance are improved up to 2.7 and 3.1 times respectively. The improvement is believed to arising from the reduced barrier height of the PtSi/strained-Si contact and the enhanced hole mobility in the strained-Si channel.     

Role of Schottky barrier height at source/drain contact for electrical improvement in high carrier concentration amorphous InGaZnO thin film transistors

We report the fabrication of bottom-gate thin film transistors (TFTs) at various carrier concentrations of an amorphous InGaZnO (a-IGZO) active layer from ~10¹⁶ to ~10¹⁹ cm⁻³, which exceeds the limit of the concentration range for a conventional active layer in a TFT. Using the Schottky TFTs configuration yielded high TFT performance with saturation mobility (μ_sat), threshold voltage (V_TH), and on off current ratio (I_ON/I_OFF) of 16.1 cm²/V s, −1.22 V, and 1.3×10⁸, respectively, at the highest carrier concentration active layer of 10¹⁹ cm⁻³. Other carrier concentrations (<10¹⁹ cm⁻³) of IGZO resulted in a decrease of its work function and increase in activation energy, which changes the source/drain (S/D) contact with the active layer behavior from Schottky to quasi Ohmic, resulting in achieving conventional TFT. Hence, we successfully manipulate the barrier height between the active layer and the S/D contact by changing the carrier concentration of the active layer. Since the performance of this Schottky type TFT yielded favorable results, it is feasible to explore other high carrier concentration ternary and quaternary materials as active layers.