A novel low power UWB cascode SiGe BiCMOS LNA with current reuse and zero-pole cancellation

A low power cascode SiGe BiCMOS low noise amplifier (LNA) with current reuse and zero-pole cancellation is presented for ultra-wideband (UWB) application. The LNA is composed of cascode input stage and common emitter (CE) output stage with dual loop feedbacks. The novel cascode-CE current reuse topology replaces the traditional two stages topology so as to obtain low power consumption. The emitter degenerative inductor in input stage is adopted to achieve good input impedance matching and noise performance. The two poles are introduced by the emitter inductor, which will degrade the gain performance, are cancelled by the dual loop feedbacks of the resistance-inductor (RL) shunt–shunt feedback and resistance-capacitor (RC) series–series feedback in the output stage. Meanwhile, output impedance matching is also achieved. Based on TSMC 0.35 μm SiGe BiCMOS process, the topology and chip layout of the proposed LNA are designed and post-simulated. The LNA achieves the noise figure of 2.3–4.1 dB, gain of 18.9–20.2 dB, gain flatness of ±0.65 dB, input third order intercept point (IIP₃) of ?7 dBm at 6 GHz, exhibits less than 16 ps of group delay variation, good input and output impedances matching, and unconditionally stable over the whole band. The power consumption is only 18 mW.     

A novel wide band super transistor based voltage feedback current amplifier

This paper is assigned to the design of voltage feedback current amplifiers (VFCAs). Their operation and interesting characteristics are covered and a novel CMOS VFCA is presented. New ideas based on super transistors (STs) are devised and used to design a high performance VFCA. Benefiting from the interesting properties of STs, the proposed VFCA exhibits high linearity, high output impedance, very low input impedance and wide bandwidth. The proposed circuit is designed using TSMC 0.18 μm CMOS technology parameters and supply voltage of ±0.75 V. Simulation results with HSPICE show low THD of ?60 dB at the output signal, very low impedance of 0.6 Ω and 0.2 Ω at the input and feedback ports respectively and high output impedance of 10 MΩ. Moreover it can provide wide ?3 dB bandwidth of 15.5 MHz. The results prove the high capability of the VFCA in current mode signal processing and encourage strong motivation to develop commercially available VFCAs.     

A high performance differential input CMOS current buffer

In this paper, a high accuracy CMOS differential input current buffer (CB) is proposed which employs super source followers (SSF) as input stage and regulated cascode (RGC) current mirrors as output stage. High accuracy requires very high output resistance and low input resistance. Small signal analysis is performed and it is shown that the proposed CB circuit has very low input impedances at ports n and p due to SSF transistors and also very high output impedance at output port due to RGC current mirrors. The simulation results show 9.72 Ω input resistances at ports n and p, 454 MΩ output resistance at output port with only 625 μW power consumption under ±0.9 V power supplies. The simulations are performed with HSpice using TSMC 0.18 μm process parameters and it is shown that the simulation results are in very good agreement with the theoretical ones.     

Low power high output impedance high bandwidth QFGMOS current mirror

Current mirror is a basic block of any mixed-signal circuit for example in an analog-to-digital converter. Its precise performance is the key requirement for analog circuits where offset is a measure issue. The key parameter which defines the performance of current mirror is its input/output impedance, input swing, and bandwidth. In this paper, a low power design of current mirror using quasi-floating gate MOS transistor is presented. The proposed current mirror boosts its output impedance in range of giga-ohm through use of regulated cascode structure followed by super-cascode. Another improvement is done in reduced input compliance voltage limits with the help of level shifter. The proposed current mirror operates well for input current range 0–700 $\mathrm{\mu }A$ with an input and output impedance of 160 $\Omega$ and 8.55 $\mathrm{G}\Omega$ respectively and high bandwidth of 4.05 $\mathrm{GHz}$. The total power consumption of the proposed current mirror is about 0.84 mW. The low power consumption with enhanced output impedance and bandwidth suits proposed current mirror for various high-speed analog designs. Performance of the presented current mirror circuit is verified using HSpice simulations on 0.18 $\mathrm{\mu }m$ mixed-mode twill-well technology at a supply voltage of ±0.5 V.     

A 24-dB Ku-band low-power linearized 90-nm amplifier with a built-in output buffer

In this paper, we present a 90-nm high gain (24 dB) linearized CMOS amplifier suitable for applications requiring high degree of port isolation in the K_u-band (13.2–15.4 GHz). The two-stage design is composed of a low-noise common-gate stage and a gain-boosting cascode block with an integrated output buffer for measurement. Optimization of input stage and load-port buffer parameters improves the front-end's linear coverage, port return-loss, and overall gain without burdening its power demand and noise contribution. With low gate bias voltages (0.65–1.2 V) and an active current source, <?10 dB port reflection loss and 3.25–3.41 dB NF are achieved over the bandwidth. The input reflection loss of the overall amplifier lies between ?35 and ?10 dB and the circuit demonstrates a peak forward gain of 24 dB at 14.2 GHz. The output buffer improves the amplifier's forward gain by ～9 dB and pushes down the minimum output return loss to ?22.5 dB while raising the front-end NF by only 0.05 dB. The effect of layout parasites is considered in detail in the 90-nm process models for accurate RF analysis. Monte Carlo simulation predicts 9% and 8% variation in gain and noise figures resulting from a 10% mismatch in process. The K_u-band amplifier including the buffer block consumes 7.69 mA from a 1.2-V supply. The proposed circuit techniques achieve superior small signal gain, GHz-per-milliwatt, and range of linearity when compared with simulated results of reported microwave amplifiers.     

Quasi-floating gate MOSFET based low voltage current mirror

This paper demonstrates the use of quasi-floating gate MOSFET (QFGMOS) in the design of a low voltage current mirror and highlights its advantages over the floating gate MOSFET (FGMOS). The use of resistive compensation has been shown to enhance the bandwidth of QFGMOS current mirror. The proposed current mirror based on QFGMOS has a current range up to 500 μA with offset of 2.2 nA, input resistance of 235 Ω, output resistance of 117 kΩ, current transfer ratio of 0.98, dissipates 0.83 mW power and exhibits bandwidth of 656 MHz which increases to 1.52 GHz with resistive compensation. The theoretical and simulation results are in good agreement. The workability of the circuits has been verified using PSpice simulation for 0.13 μm technology with a supply voltage of ±0.5 V.     

A low power current controllable single-input three-output current-mode filter using MOS transistors only

A novel circuit configuration for the realization of low power single-input three-output (SITO) current mode (CM) filters employing only MOS transistors are presented. The proposed circuit can realize low-pass (LP), band-pass (BP) and high-pass (HP) filter functions simultaneously at three high impedance outputs without changing configuration. Despite the other previously reported works, the proposed circuit is free from resistors and passive capacitors. Instead of passive capacitors; the gate-source capacitor of MOS transistor is used making the proposed circuit ideally suitable for integration. Compared to other works, the proposed filter has also the lowest number of transistors and lowest power consumption. The proposed circuit exhibits low-input and high-output impedances, which is highly desirable for cascading in CM signal processing. Moreover, it is center frequency can be electronically adjusted using a control current without a significant effect on quality factor (Q) granting it the highly desirable capability of electronic tunability. Transfer functions of the LP, BP and HP outputs are derived and the performance of the proposed circuit is proved through pre layout and post layout simulations at supply voltage of 1.8 V and using 0.18 μm CMOS process parameters. The power consumption and the required chip area are only 0.5 mW and 77.4 μm × 70.2 μm, respectively.     

Realization of current-mode biquadratic filter employing multiple output OTAs and MO-CCII

This paper presents a low voltage low power operational transconductance amplifier circuit. By using a source degeneration technique, the proposed realization powered at ±0.9 V shows a high DC gain of 63 dB with a unity gain frequency at 3.5 MHz, a wide dynamic range and a total harmonic distortion of −60 dB at 1 MHz for an input of 1 Vpp. According to the connection of negative current terminal to positive voltage terminal of double output OTA circuit, a second generation current conveyor (CCII-) has been realized. This circuit offers a good linearity over the dynamic range, an excellent accuracy and wide current mode of 56 MHz and voltage mode of 16.78 MHz cut-off frequency f-3 dB.Thereafter, new SIMO current-mode biquadratic filter composed by OTA and CCII as active elements and two grounded capacitors is implemented. This filter is characterized by (i) independent adjusting of pole frequency and quality factor, (ii) it can realize all simulations results without changing the circuit topology, (iii) it shows low power consumption about 0.24 mW. All simulations are performed by Cadence (Cadence Design Systems) technology Tower Jazz 0.18 μm TS18SL.     

A low-voltage low-power CMOS transmitter front-end using current mode approach for 2.4 GHz wireless communications

This paper presents a low-voltage low-power transmitter front-end using current mode approach for 2.4 GHz wireless communication applications, which is fabricated in a chartered 0.18 μm CMOS technology. The direct up-conversion is implemented with a current mode mixer employing a novel input driver stage, which can significantly improve the linearity and consume a small amount of DC current. The driver amplifier utilizes a transimpedance amplifier as the first stage and employs an inter-stage capacitive cross-coupling technique, which enhances the power conversion gain as well as high linearity. The measured results show that at 2.4 GHz, the transmitter front-end provides 15.5 dB of power conversion gain, output P?1 dB of 3 dBm, and the output-referred third-order intercept point (OIP3) of 13.8 dBm, while drawing only 6 mA from the transmitter front-end under a supply voltage of 1.2 V. The chip area including the testing pads is only 0.9 mm×1.1 mm.     

Single-grain Si thin-film transistors SPICE model,analog and RF circuit applications

Single-grain thin-film transistors (SG-TFTs) fabricated inside location-controlled using μ-Czochralski process exhibit SOI-FETs like performance despite processing temperatures remaining below 350 °C. Thus, the SG-TFT is a potential technology for large-area highly-integrated electronic system and system-in-package, taking advantage of the system-on-flexible substrate and low manufacturing cost capabalities. The SG-TFT is modeled based on the BSIMSOI SPICE model where the mobility parameter is modified to fit the SG-TFT behavior. Therefore, analog and RF circuits can be designed and benchmarked. A two-stage telescopic cascode operational amplifier fabricated in a prototype 1.5 μm SG-TFT technology demonstrates DC gain of 55 dB and unity-gain bandwidth of 6.3 MHz. A prototype CMOS voltage reference demonstrates a power supply rejection ratio (PSRR) of 50 dB. With unity-gain frequency, f_T, in the GHz range, the SG-TFT can also enable RF circuits for wireless applications. A 12 dB gain RF cascode amplifier with integrated on-chip inductors operating in the 433 MHz ISM band is demonstrated.     

An inductorless wideband common-gate LNA with dual capacitor cross-coupled feedback and negative impedance techniques

A wideband common-gate (CG) low-noise amplifier (LNA) with dual capacitor cross-coupled (CCC) feedback and negative impedance techniques is presented for multimode multiband wireless communication applications. Double CCC technique boosts the input transconductance of the LNA, and low power consumption is obtained by using current-reuse technique. Negative impedance technique is employed to alleviate the correlation between the transconductance of the matching transistors and input impedance. Meanwhile, it also allows us to achieve a lower noise figure (NF). Moreover, current bleeding technique is adopted to allow the choice of a larger load resistor without sacrificing the voltage headroom. The proposed architecture achieves low noise, low power and high gain simultaneously without the use of bulky inductors. Simulation results of a 0.18-μm CMOS implementation show that the proposed LNA provides a maximum voltage gain of 25.02 dB and a minimum NF of 2.37 dB from 0.1 to 2.25 GHz. The input-referred third-order intercept point (IIP3) and input 1-dB compression point (IP_1dB) are better than –7.8 dBm and –19.2 dBm, respectively, across the operating bandwidth. The circuit dissipates 3.24 mW from 1.8 V DC supply with an active area of 0.03 mm².     

A UWB CMOS low-noise amplifier with noise reduction and linearity improvement techniques

In this paper, a highly linear CMOS low noise amplifier (LNA) for ultra-wideband applications is presented. The proposed LNA improves both input second- and third-order intercept points (IIP2 and IIP3) by canceling the common-mode part of all intermodulation components from the output current. The proposed LNA structure creates equal common-mode currents with the opposite sign by cascading two differential pairs with a cross-connected output. These currents eliminate each other at the output and improve the linearity. Also, the proposed LNA improves the noise performance by canceling the thermal noise of the input and auxiliary transistors at the output. Detailed analysis is provided to show the effectiveness of the proposed LNA structure. Post-layout circuit level simulation results using a 90 nm RF CMOS process with Spectre-RF reveal 9.5 dB power gain, -3 dB bandwidth (BW_−3dB) of 8 GHz from 2.4 GHz to 10.4 GHz, and mean IIP3 and IIP2 of +13.1 dBm and +42.8 dBm, respectively. The simulated S₁₁ is less than −11 dB in whole frequency range while the LNA consumes 14.8 mW from a single 1.2 V power supply.     

A RF front-end for DVB-SH based on current conveyors

Inductors are used extensively in Radio Frequency Integrated Circuits to design matching networks, load circuits of voltage controlled oscillators, filters, mixers and many other RF circuits. However, on-chip inductors are large and cannot be ported easily from one process to the next. Due to modern CMOS scaling, inductorless RF design is rapidly becoming possible. In this paper a new methodology for designing the RF frontend necessary for the DVB-SH in a 90 nm CMOS technology based on the use current conveyors (CC) is presented. The RF frontend scheme is composed of a second generation CC (CCII) LNA with asymmetric input and output, an asymmetric to differential converter, and a passive differential mixer followed by two CCII transimpedance amplifiers to obtain a high gain conversion. Measurements show a conversion gain of 20.8 dB, a 14.5 dB noise figure, an input return loss (S11) of −14.3 dB and an output compression point of −3.9 dBm. This combination draws 28.4 mW from a ±1.2 V supply.     

High birefringent rectangular-lattice photonic crystal fibers with low confinement loss employing different sizes of elliptical air holes in the cladding and the core

Based on the full-vector finite element method with anisotropic perfectly matched layers, modal birefringence and confinement loss for the fundamental mode in rectangular-lattice photonic crystal fibers with different sizes of elliptical air holes in the cladding and the core are investigated numerically. The results show that the modal birefringence in this proposed photonic crystal fibers can be up to 5.64 × 10^?2 at the wavelength of 1.55 μm. Moreover, when the birefringence is higher than 4 × 10^?2, the confinement loss of x-polarized mode can be kept less than 0.005 dB/km at 1.55 μm. It means that the tradeoff between the high birefringence and the low confinement loss is overcome.     

A high-performance 1.2 V–99 μW rail-to-rail CMOS class AB amplifier

This paper presents a compact, reliable 1.2 V low-power rail-to-rail class AB operational amplifier (OpAmp) suitable for integrated battery powered systems which require rail-to-rail input/output swing and high slew-rate while maintaining low power consumption. The OpAmp, fabricated in a standard 0.18 μm CMOS technology, exhibits 86 dB open loop gain and 97 dB CMRR. Experimental measurements prove its correct functionality operating with 1.2 V single supply, performing very competitive characteristics compared with other similar amplifiers reported in the literature. It has rail-to-rail input/output operation, 5 MHz unity gain frequency and a 3.15 V/μs slew-rate for a capacitive load of 100 pF, with a power consumption of 99 μW.     

Low power high gain CMOS LNA based on inverter cell and self-body bias for UWB receivers

A low-power low-noise amplifier (LNA) utilized a resistive inverter configuration feedback amplifier to achieve the broadband input matching purposes. To achieve low power consumption and high gain, the proposed LNA utilizes a current-reused technique and a splitting-load inductive peaking technique of a resistive-feedback inverter for input matching. Two wideband LNAs are implemented by TSMC 0.18 μm CMOS technology. The first LNA operates at 2–6 GHz. The minimum noise figure is 3.6 dB. The amplifier provides a maximum gain (S₂₁) of 18.5 dB while drawing 10.3 mW from a 1.5-V supply. This chip area is 1.028×0.921 mm². The second LNA operates at 3.1–10.6 GHz. By using self-forward body bias, it can reduce supply voltage as well as save bias current. The minimum noise figure is 4.8 dB. The amplifier provides a maximum gain (S₂₁) of 17.8 dB while drawing 9.67 mW from a 1.2-V supply. This chip area is 1.274×0.771 mm².     

Self-heating and destruction of high-voltage 4H-SiC rectifier diodes under a single short current surge pulse

Self-heating of high-voltage (6 kV class) 4H-SiC rectifier p⁺–n–n⁺ diodes under the action of a single 20 μs forward current surge pulse has been studied experimentally up to current densities j ≈ 100 kA/cm². The diode parameters are stable after a single surge pulse with current density j ≈ 60 kА/cm², although the estimated temperature of the diode at the end of this pulse is ～1650 K. After several pulses of this amplitude or after subjecting the diode to pulses with higher current density, the diode degrades. The degradation is manifested in an irreversible decrease of the differential resistance of the diode under a high forward bias. Even a single 20 μs pulse with peak current density j ≈ 100 kA/cm² leads to total destruction of the device.     

A novel ultra-high compliance, high output impedance low power very accurate high performance current mirror

In this paper a novel ultra-high compliance, low power, very accurate and high output impedance current mirror/source is proposed. Deliberately composed elements and a good combination (for a mutual auto control action) of negative and positive feedbacks in the proposed circuit made it unique in gathering ultra-high compliances, high output impedance and high accuracy ever demanded merits. The principle of operation of this unique structure is discussed, its most important formulas are derived and its outstanding performance is verified by HSPICE simulation in TSMC 0.18 μm CMOS, BSIM3 and Level49 technology. Simulation results with 1 V power supply and 8 μA input current show an input and output minimum voltages of 0.058 and 0.055 V, respectively, which interestingly provide the highest yet reported compliances for current mirrors implemented by regular CMOS technology. Besides an input resistance of 13.3 Ω, an extremely high output resistance of 34.3 GΩ and −3 dB cutoff frequency of 210 MHz are achieved for the proposed circuit while it consumes only 42.5 μW and its current transfer error (at bias point) is the excellent value of 0.02%.     

A real-time self-calibrated current mirror for wide range current reference generation,signal reproduction and delaying

Current Mirrors are widely used in current mode circuits like A/D Converters, current conveyors, filters etc. The most important features of a current mirror are its precision, its input and output, resistance and minimum voltage and its frequency response. Although several mirrors with extremely small current transfer error have been presented, this error is usually measured in the typical case. This error may significantly differ in real-time conditions depending on mismatches, process and temperature variations. Stimulated by the current reference generation required in an A/D Converter with novel binary tree architecture that has been recently presented, an appropriate current mirror architecture supported by real time calibration logic is described in this paper. This mirror can generate a high enough output current (up to 1 mA), with relatively low transfer error (<4%), in a descent frequency range of up to 1 GHz. It requires a 1–1.2 V voltage supply and dissipates a power that can be as low as 0.3 mW. The error is measured using mismatch and process variation Monte Carlo post-layout simulations in TSMC 90 nm process.     

Improving the light output power of GaN-based light-emitting diodes through the use of SiO2 cones

We introduced a simple wet-etching process to form SiO₂ cones and investigated the effect of the size and coverage of the SiO₂ cones on the output power of GaN-based light-emitting diodes (LEDs). The diameter of the cones varies from 2.8 to 17.1 μm and the height from 0.6 to 2.0 μm. It is shown that regardless of the sizes of the cones, all of the LEDs exhibit a same forward-bias voltage of 3.31 V at an injection current of 20 mA. As the size of the cones increases, the light output increases, reaches maximum at cone #3 (12.4 μm in diameter and 2.0 μm in height), and then decrease slightly. For example, the LEDs fabricated with different SiO₂ cones exhibit 11.4–35.9% higher light output power (at 20 mA) than do the LEDs without the cones. The electroluminescence (EL) intensity (at 20 mA) also exhibits cone size dependence similar to that of light output power. For example, the LEDs fabricated with different cones exhibit 7.7–36.3% higher EL intensity than the LEDs without the cones.