A 60-dB 246-MHz CMOS variable gain amplifier for subsampling GSM receivers

A variable gain amplifier (VGA) is designed for a GSM subsampling receiver. The VGA is implemented in a 0.35-/spl mu/m CMOS process and approximately occupies 0.64 mm/sup 2/. It operates at an IF frequency of 246 MHz. The VGA provides a 60-dB digitally controlled gain range in 2-dB steps. The overall gain accuracy is less than 0.3 dB. The current is 9 mA at 3 V supply. The noise figure at maximum gain is 8.7 dB. The IIP3 is -4 dBm at minimum gain, while the OIP3 is -1 dBm at maximum gain. The group delay is 1.5 ns across 5-MHz bandwidth.     

A 95-dB linear low-power variable gain amplifier

An all-CMOS variable gain amplifier (VGA) that adopts a new approximated exponential equation is presented. The proposed VGA is characterized by a wide range of gain variation, temperature-independence gain characteristic, low-power consumption, small chip size, and controllable dynamic gain range. The two-stage VGA is fabricated in 0.18-/spl mu/m CMOS technology and shows the maximum gain variation of more than 95 dB and a 90-dB linear range with linearity error of less than /spl plusmn/ 1 dB. The range of gain variation can be controlled from 68 to 95 dB. The P1dB varies from - 48 to - 17 dBm, and the 3-dB bandwidth is from 32 MHz (at maximum gain of 43 dB) to 1.05 GHz (at minimum gain of - 52 dB). The VGA dissipates less than 3.6 mA from 1.8-V supply while occupying 0.4 mm/sup 2/ of chip area excluding bondpads.     

CMOS linear-in-dB VGA with DC offset cancellation for direct-conversion receivers

A low-power high-linearity linear-in-dB variable gain amplifier (VGA) with novel DC offset calibration loop for direct-conversion receiver (DCR) is proposed in this paper. The proposed VGA uses the differential-ramp based technique, digitally programmable gain amplifier (PGA) can be converted to analog controlled dB-linear VGA. An operational amplifier (OPAMP) utilizing an improved Miller compensation approach is adopted in this VGA design. The proposed VGA shows a 57dB linear range. The DC offset cancellation (DCOC) loop is based on a continuous time feedback that includes Miller effect and linear rang operation MOS transistor to realize large value capacitor and resistor to solve the DC offset problem, respectively. The proposed approach requires no external components and demonstrates excellent DCOC capability in measurement. Fabricated in SMIC 0.13 m CMOS technology, this VGA dissipates 4.5 mW from a 1.2 V supply voltage while occupying 0.58mm2 of chip area including bondpads. In addition, the DCOC circuit shows 500Hz high pass cutoff frequency (HPCF) and the measured residual DC offset at the output of VGA is less than 2 mV.     

CMOS linear-in-dB VGA with DC offset cancellation for direct-conversion receivers

A low-power high-linearity linear-in-dB variable gain amplifier(VGA) with novel DC offset calibration loop for direct-conversion receiver(DCR) is proposed.The proposed VGA uses the differential-ramp based technique,a digitally programmable gain amplifier(PGA) can be converted to an analog controlled dB-linear VGA. An operational amplifier(OPAMP) utilizing an improved Miller compensation approach is adopted in this VGA design.The proposed VGA shows a 57 dB linear range.The DC offset cancellation(DCOC) loop is based on a continuous-time feedback that includes the Miller effect and a linear range operation MOS transistor to realize high-value capacitors and resistors to solve the DC offset problem,respectively.The proposed approach requires no external components and demonstrates excellent DCOC capability in measurement.Fabricated using SMIC 0.13μm CMOS technology,this VGA dissipates 4.5 mW from a 1.2 V supply voltage while occupying 0.58 mm~2 of chip area including bondpads.In addition,the DCOC circuit shows 500 Hz high pass cutoff frequency(HPCF) and the measured residual DC offset at the output of VGA is less than 2 mV.     

A 3-GHz 32-dB CMOS limiting amplifier for SONET OC-48 receivers

A CMOS limiting amplifier with a bandwidth of 3 GHz, a gain of 32 dB, and a noise figure of 16 dB is described. The amplifier is fabricated in a standard 2.5-V 0.25-μm CMOS technology and consumes 53 mW. Inversely scaled amplifier stages and active inductors with a low voltage drop are used to achieve this performance. The amplifier is targeted for use in 2.5-Gb/s (OC-48) SONET systems     

A 78-dB gain range low power CMOS RF digitally programmable gain amplifier for mobile terrestrial D-TV tuner IC

An RF digitally programmable gain amplifier for a terrestrial mobile digital-TV (terrestrial digital multimedia broadcasting, integrated services digital broadcasting-terrestrial, and digital video broadcasting-handheld) is implemented using 0.18-/spl mu/m CMOS technology. In order to attain a large gain range with fine step resolution, various new programmable gain amplifier architectures are proposed and verified by measurement. The fabricated integrated circuit shows 2.5-dB NF, -20-dBm IIP3, 45-dB voltage gain at highest gain mode in UHF band case, and 78-dB gain range with 0.4-dB resolution while consuming 15mA at 1.8-V supply voltage.     

A variable gain amplifier with 50-dB control range for 900-MHz applications

A variable gain amplifier for 900-MHz applications has been designed and fabricated in a BiCMOS process with f/sub T/ = 24 GHz. The amplifier has linear-in-dB gain control with a 50-dB control range. The maximum gain is 28 dB and the third-order output intercept point (OIP3) is 13.7 dBm. The gain is achieved in one gain stage with a cascoded output. The amplifier bias network and the gain-control circuitry are temperature compensated for temperature-independent gain at any gain setting. The bias network also uses a feedback loop to cancel out undesired low frequencies present at the radio-frequency input. The maximum output power is +10 dBm and the output 1-dB compression point is +8.7 dBm. Active chip area is 0.1 mm/sup 2/. The amplifier is packaged in a SOT-363 and consumes 30 mA from a 2.8-V supply.     

10 Gb/s 带有直流漂移校正的dB线性、无电感宽带可变增益放大器

本文介绍了一款带有直流漂移校正的dB线性、无电感宽带可变增益放大器。该可变增益放大器包含一个可变增益模块,一个带有共模电压调整的直流漂移校正模块,以及一个带宽拓展模块。为了放大器带宽同时节约芯片面积,本设计中带宽拓展模块采用了一种无电感设计的有源反馈技术,通过该模块在高频增益过冲来补偿可变增益模块和直流漂移校正模块在高频处的增益下降,从而达到拓展带宽、提高增益的效果。该可变增益放大器采用0.13mm SiGe BiCMOS工艺。测试结果表明,该款放大器3 dB带宽达到7.5 GHz,可变增益范围为40 dB (-10 dB-30 dB)。在10 Gb/s伪随机测试码输入的情况下,测试输出信号峰峰抖动小于30 ps_pp,功耗为50 mW。由于无电感设计,该芯片的面积仅为0.53*0.27 mm₂。     

A broadband linear-in-decibel variable gain amplifier with low gain error

A new circuit architecture for broadband digitally controlled variable gain amplifier (VGA) is introduced in this paper. The gain of the VGA is controlled precisely by using a resistor ladder attenuator and a closed-loop fine gain control block together. The bandwidth of the VGA is extended by applying a compensation technique in the fine gain control block. Implemented in 0.13-μm CMOS technology, the proposed VGA demonstrates a decibel-linear gain range of 24 dB (0–24 dB) with a gain step of 0.1 dB, a gain error <0.08 dB, a maximum input-referred third-order intercept point (IIP3) of 22.8 dBm, and a 3-dB bandwidth of 600 MHz.     

Wideband high dynamic range CMOS variable gain amplifier for low voltage and low power wireless applications

A high frequency CMOS variable gain amplifier (VGA) employing a new gain stage cell is proposed. A design technique based on the proposed VGA enables enhancement of its operating frequency up to about 350 MHz with a gain control range of 84 dB. The power consumption of the VGA implemented using a 0.18 /spl mu/m CMOS standard process is about 3 mA at 1.8 V supply voltage.     

A 2.4-GHz low power dual gain low noise amplifier for ZigBee

e figure (NF) is 2.3-3 dB in the whole 2.45-GHz ISM band. The measured 1-dB compression point, IIP3 and IIP2 is -9, 1 and 33 dBm, respectively. The DGLNA consumes 2 mA of current from a 1.8 V power supply.     

用于ZigBee的2.4GHz低功耗双增益低噪声放大器

This paper presents a fully differential dual gain low noise amplifier（DGLNA） for low power 2.45-GHz ZigBee/IEEE 802.15.4 applications.The effect of input parasitics on the inductively degenerated cascode LNA is analyzed.Circuit design details within the guidelines of the analysis are presented.The chip was implemented in SMIC 0.18-μm 1P6M RF/mixed signal CMOS process.The DGLNA achieves a maximum gain of 8 dB and a minimum gain of 1 dB with good input return loss.In high gain mode, the measured noise figure（NF） is 2.3-3 dB in the whole 2.45-GHz ISM band.The measured 1-dB compression point, IIP3 and IIP2 is-9, 1 and 33 dBm, respectively.The DGLNA consumes 2 mA of current from a 1.8 V power supply.     

A CMOS variable gain LNA for UWB receivers

A CMOS variable gain low noise amplifier(LNA) is presented for 4.2-4.8 GHz ultra-wideband application in accordance with Chinese standard.The design method for the wideband input matching is presented and the low noise performance of the LNA is illustrated.A three-bit digital programmable gain control circuit is exploited to achieve variable gain.The design was implemented in 0.13-μm RF CMOS process,and the die occupies an area of 0.9 mm~2 with ESD pads.Totally the circuit draws 18 mA DC current from 1.2 V DC supply,the LNA exhibits minimum noise figure of 2.3 dB,S(1,1) less than -9 dB and S(2,2) less than -10 dB.The maximum and the minimum power gains are 28.5 dB and 16 dB respectively.The tuning step of the gain is about 4 dB with four steps in all.Also the input 1 dB compression point is -10 dBm and input third order intercept point(IIP3) is -2 dBm.     

一种用于超宽带接收机的CMOS可变增益低噪声放大器

本文介绍一种符合中国超宽带应用标准的工作频率范围为4.2-4.8 GHz的CMOS可变增益低噪声放大器(LNA)。文章主要描述了LNA宽带输入匹配的设计方法和低噪声性能的实现方式,提出一种3位可编程增益控制电路实现可变增益控制。该设计采用0.13-μm RF CMOS工艺流片,带有ESD引脚的芯片总面积为0.9平方毫米。使用1.2 V直流供电,芯片共消耗18 mA电流。测试结果表明,LNA最小噪声系数为2.3 dB,S(1,1)小于-9 dB,S(2,2)小于-10 dB。最大和最小功率增益分别为28.5 dB和16 dB,共设有4档可变增益,每档幅度为4 dB。同时,输入1 dB压缩点是-10 dBm,输入三阶交调为-2 dBm。     

A 50-MHz dB-linear programmable-gain amplifier with 98-dB dynamic range and 2-dB gain steps for 3 V power supply

A programmable-gain amplifier (PGA) circuit introduced in this paper has a dynamic gain range of 98 dB with 2 dB gain steps and is controlled by 6-bit gain control bits for a 3 V power supply. It has been fabricated in a 0.5 /spl mu/m 15 GHz f/sub T/ Si BiCMOS process and draws 13 mA. The active die area taken up by the circuit is 400 /spl mu/m /spl times/ 1170 /spl mu/m. A noise figure (NF) of 4.9 dB was measured at the maximum gain setting. In addition, an analysis of the bias current generation to provide dB-linear gain control is presented.     

Low power high gain gain-controlled LNA and mixer for GNSS receivers Wei Binbin(魏斌斌)1, Jiang Jinguang(江金光)1,2,3*

A low power high gain gain-controlled LNA ＋ mixer for GNSS receivers is reported. The high gain LNA is realized with a current source load. Its gain-controlled ability is achieved using a programmable bias circuit. Taking advantage of the high gain LNA, a high noise figure passive mixer is adopted. With the passive mixer, low power consumption and high voltage gain of the LNA ＋ mixer are achieved. To fully investigate the performance of this circuit, comparisons between a conventional LNA ＋ mixer, a previous low power LNA ＋ mixer, and the proposed LNA ＋ mixer are presented. The circuit is implemented in 0.18 #m mixed-signal CMOS technology. A 3.8 dB noise figure, an overall 45 dB converge gain and a 10 dB controlled gain range of the two stages are measured. The chip occupies 0.24 mm2 and consumes 2 mA current under 1.8 V supply.     

Low power dissipation SiGe HBT dual-band variable gain amplifier

A dual-band variable gain amplifier operating at 0.9 GHz and 2.4 GHz was designed based on high performance RF SiGe HBT for large amount of signals transmission and analysis. Current steering was adopted in gain-control circuit to get variable trans-conductance and then variable gain. Emitter degeneration and current reuse were considered in amplifying stage for low noise figure and low power dissipation respectively. A single-path circuit resonating at two frequency points simultaneously was designed for input impedance matching. PCB layout parasitic effects, especially the via parasitic inductor, were analyzed theoretically and experimentally and accounted for using electro-magnetic (EM) simulation. The measurement results show that a dynamic gain control of 26 dB/16 dB in a control voltage range of 0.0–1.4 V has been achieved at 0.9/2.4 GHz respectively. Both S₁₁ and S₂₂ are below than –10 dB in all the control voltage range. Noise figures at both 0.9 GHz and 2.4 GHz are lower than 5 dB. Total power dissipation of the dual-band VGA is about 16.5 mW at 3 V supply.     

A 60-dB gain, 55-dB dynamic range, 10-Gb/s broad-band SiGe HBTlimiting amplifier

A limiting amplifier IC implemented in a silicon-germanium (SiGe) heterojunction bipolar transistor technology for low-cost 10-Gb/s applications is described. The IC employs 20 dB gain limiting cells, input overload protection, split analog-digital grounds, and on-chip isolation interface with transmission lines. A gain enhancement technique has been developed for a parallel-feedback limiting cell. The limiting amplifier sensitivity is less than 3.5 mV_pp at BER=10^-9 with 2-V_pp maximum input (55-dB dynamic range). The total gain is over 60 dB, and S₂₁ bandwidth exceeds 15 GHz at 10-mV_pp input. Parameters S₁₁ and S₂₂ are better than -10 dB in the 10-GHz frequency range. The AM to PM conversion is less than 5 ps across input dynamic range. The output differential voltage can be set from 0.2 to 2 V_pp with IC power dissipation from 250 mW to 1.1 W. The chip area is 1.2×2.6 mm². A 10-Gb/s optical receiver, built with the packaged limiting amplifier, demonstrated -19.6-dBm sensitivity. The IC can be used in 10-Gb/s fiber-optic receivers requiring high sensitivity and wide input dynamic range