Iterative optimization of tail breaking force of 1 mil wire thermosonic ball bonding processes and the influence of plasma cleaning

An online tail breaking force measurement method is developed with a proximity sensor between wire clamp and horn. The wire under the tensile load measures about 1.5 cm extending from the bond location to the wire clamp. To increase the sensitivity, the bondhead speed is reduced to 2 mm/s during breaking the tail bond. It takes roughly 10 ms to break the tail bond. The force resolution of the method is estimated to be better than 5.2 mN. An automatic wire bonder used to continuously bond up to 80-wire loops while recording the on-line proximity signals. All wires are directed perpendicular to the ultrasound direction. The tail breaking force for each bond is evaluated from the signal and shown automatically on the bonder within 2 min after bonding.Results are obtained for a typical Au wire and a typical Cu wire bonding process. Both wires are 25 mm in diameter and bonded on Ag plated diepads of standard leadframes at 220 °C. An average Cu tail breaking force of higher than 50 mN is obtained if the leadframe is plasma cleaned before the bonding with 100% Ar for 5 min. This result is comparable to that obtained with Au wire. The standard deviation of the Cu tail breaking force is about twice that obtained with Au wire. The tail breaking force depends on the bonding parameters, metallization variation, and cleanliness of the bond pad. The cleanliness of the bonding pad is more important with Cu wire than with Au wire.     

Solid-state interfacial reactions at the solder joints employing Au/Pd/Ni and Au/Ni as the surface finish metallizations

A tri-layer of nickel/palladium/gold (Au/Pd/Ni) is a promising candidate to replace the conventional Au/Ni bi-layer as the surface finish metallization for lead-free packaging. A surface finish metallization (Au/Pd/Ni or Au/Ni) and a Sn layer are sequentially deposited on a Cu substrate and then are subjected to thermal aging at 150 and 200 °C to investigate the interfacial reactions in the stacking multilayer structure made by low-temperature solid-state bonding. Because of the absence of the reflow process, the Pd and Au layers do not dissolve in the Sn matrix but remain at the interface and participate in the interfacial reaction to form the (Pd,Ni,Au)Sn₄ and (Au,Ni)Sn₄ phases at the Au/Pd/Ni- and Au/Ni-based interfaces, respectively. Though the Pd layer was only 0.4 μm, its resulting (Pd,Ni,Au)Sn₄ phase is much thicker than the (Au,Ni)Sn₄ phase. These two intermetallic compounds exhibit very different microstructural evolution which significantly affects the interfacial microstructures and growth rate of other intermetallic compound formed at the same interfaces.     

Capacitance–conductance–current–voltage characteristics of atomic layer deposited Au/Ti/Al2O3/n-GaAs MIS structures

We have studied the admittance and current–voltage characteristics of the Au/Ti/Al₂O₃/n-GaAs structure. The Al₂O₃ layer of about 5 nm was formed on the n-GaAs by atomic layer deposition. The barrier height (BH) and ideality factor values of 1.18 eV and 2.45 were obtained from the forward-bias ln I vs V plot at 300 K. The BH value of 1.18 eV is larger than the values reported for conventional Ti/n-GaAs or Au/Ti/n-GaAs diodes. The barrier modification is very important in metal semiconductor devices. The use of an increased barrier diode as the gate can provide an adequate barrier height for FET operation while the decreased barrier diodes also show promise as small signal zero-bias rectifiers and microwave. The experimental capacitance and conductance characteristics were corrected by taking into account the device series resistance R_s. It has been seen that the non-correction characteristics cause a serious error in the extraction of the interfacial properties. Furthermore, the device behaved more capacitive at the reverse bias voltage range rather than the forward bias voltage range because the phase angle in the reverse bias has remained unchanged as 90° independent of the measurement frequency.     

High temperature induced failure in Ti/Al/Ni/Au Ohmic contacts on AlGaN/GaN heterostructure

Ti/Al/Ni/Au (200/1200/500/2000 Å) Ohmic contact on AlGaN/GaN was prepared and it was subjected to thermal aging experiments. Thermal processing at 400 and 500 °C did not change the contact resistance significantly, while high temperature storage at 600 °C resulted in a surge in the contact resistance. The Al–Au alloy in the contact metal is believed to re-melt because its lowest melting temperature is 525 °C. The liquid of Al–Au alloy is observed to diffuse to the AlGaN surface and consume some AlGaN layer. In addition, voids are found to be produced during thermal process, which can reduce the effective contact area and thus lead to higher contact resistance. The TEM and EDX results of Ohmic contact’s cross sectional images provide evidence for this proposed mechanism.     

Low-temperature low-pressure die attach with hybrid silver particle paste

New types of die attach pastes comprising micron-sized Ag particles hybridized with submicron-sized Ag particles were considered as lead-free die attach materials for SiC power semiconductors. Micron-sized Ag particles in alcohol solvent were prepared by mixing the die attach paste with submicron-sized Ag particles. The alcohol vaporizes completely during sintering and no residue exists in the bonding layer. The Ag layer has a uniform porous structure. The electrical resistivity of the printed tracks decreases below 1 × 10^?5 Ω cm when sintered above 200 °C. When sintered at 200 °C for 30 min, the average resistivity reaches 5 × 10^?6 Ω cm, which is slightly higher than the value obtained by using Ag nanoparticle paste. A SiC die was successfully bonded to a direct bonded copper substrate and the die-shear strength gradually increases with the increase in bonding temperature up to 300 °C. The Ag die attach bond layer was stable against thermal cycles between ?40 °C and 300 °C.     

Microstructure and mechanical properties of Co/Sn-10Bi couple and Co/Sn-10Bi/Co joint

The growth behavior of interfacial intermetallic compounds (IMCs) layer of Co/Sn-10Bi and Co/Sn-10Bi/Co couple has been studied by scanning electron microscope. The critical temperature and shear strength of Co/Sn-10Bi/Co joints were tested by universal testing machine. The results showed that the thickness of CoSn₃ IMCs layer increased as the increase of aging time and temperature. The growth rate of CoSn₃ IMCs layer of Co/Sn-10Bi/Co couple was suppressed and was lower than that of Co/Sn-10Bi couple as the decline in Sn concentration of residual Sn-Bi layer. The critical temperature of Co/Sn-10Bi/Co joint that could hold a load of 1 N changed as the chemical composition of residual Sn-Bi layer changed. The shear strength of Co/Sn-10Bi/Co joints bonded at 240 °C for 20 min, 30 min, 40 min, and 50 min was between 58 MPa and 82 MPa. The shear strength of Co/Sn-10Bi/Co joint bonded at 240 °C for 60 min was only about 17 MPa. The damage in shear strength of Co/Sn-10Bi/Co joint bonded for 60 min was led by the crack in residual Bi layer.     

Effect of thermal annealing on the structural,morphological and super capacitor behavior of MnO2 nanocrystals

Precursors of nanosized manganese dioxide were prepared through a chemical precipitation method. The synthesized precursors of MnO₂ were subjected to thermo gravimetric analysis. The thermal analysis results showed the MnO₂ formation at 500 °C. To study the effect of thermal treatments on the capacitive behavior of MnO₂, the precursors were annealed at different temperatures (300, 400 and 500 °C). The annealed products were characterized by X-ray diffraction (XRD), Fourier transforms infra-red spectroscopy (FT-IR) and cyclic Voltammetry (CV) analysis. Among the annealed products, MnO₂ annealed at 400 °C exhibits high specific capacitance. The morphologies of the products annealed at 400 and 500 °C were analyzed by a scanning electron microscope (SEM) and atomic force microscopy (AFM). The sample annealed at 500 °C shows spherical morphology with the inclusion of nanorods. To confirm the morphology of the annealed products, field emission transmission electron microscope (FE-TEM) measurements were carried out.     

Studies on various chip-on-film (COF) packages using ultra fine pitch two-metal layer flexible printed circuits (two-metal layer FPCs)

Various fine pitch chip-on-film (COF) packages assembled by (1) anisotropic conductive film (ACF), (2) nonconductive film (NCF), and (3) AuSn metallurgical bonding methods using fine pitch flexible printed circuits (FPCs) with two-metal layers were investigated in terms of electrical characteristics, flip chip joint properties, peel adhesion strength, heat dissipation capability, and reliability. Two-metal layer FPCs and display driver IC (DDI) chips with 35 μm, 25 μm, and 20 μm pitch were prepared. All the COF packages using two-metal layer FPCs assembled by three bonding methods showed stable flip chip joint shapes, stable bump contact resistances below 5 mΩ, good adhesion strength of more than 600 gf/cm, and enhanced heat dissipation capability compared to a conventional COF package using one-metal layer FPCs. A high temperature/humidity test (85 °C/85% RH, 1000 h) and thermal cycling test (T/C test, ?40 °C to + 125 °C, 1000 cycles) were conducted to verify the reliability of the various COF packages using two-metal layer FPCs. All the COF packages showed excellent high temperature/humidity and T/C reliability, however, electrically shorted joints were observed during reliability tests only at the ACF joints with 20 μm pitch. Therefore, for less than 20 μm pitch COF packages, NCF adhesive bonding and AuSn metallurgical bonding methods are recommended, while all the ACF and NCF adhesives bonding and AuSn metallurgical bonding methods can be applied for over 25 μm pitch COF applications. Furthermore, we were also able to demonstrate double-side COF using two-metal layer FPCs.     

Comparison of WTi and WTi(N) as diffusion barriers for Al and Cu metallization on Si with respect to thermal stability and diffusion behavior of Ti

The thermal stability of WTi and WTi(N) as diffusion barriers for Al and Cu metallization on Si (1 0 0) was investigated by time of flight secondary ion mass spectrometry (ToF-SIMS) depth profiling, X-ray diffraction (XRD), electron microscopy (SEM and TEM) and X-ray photoelectron spectroscopy (XPS). For both, Al and Cu, Ti diffusion out of WTi into the metal was proved to occur at elevated temperatures (400 °C for Al and 600 °C for Cu) which further results in barrier film failure. Nitrogen incorporation into WTi leads to an elimination of the Ti diffusion and consequently to a better thermal stability of the barrier film. It is shown that besides crystal structure, Ti diffusion into the metallization is an essential factor of the barrier failure mechanism. The failure temperature for Al is lower than for Cu.     

Enhancement in electrical performance of indium gallium zinc oxide-based thin film transistors by low temperature thermal annealing

We have studied the characteristics of transparent bottom-gate thin film transistors (TFTs) using In–Ga–Zn–O (IGZO) as an active channel material. IGZO films were deposited on SiO₂/Si substrates by DC sputtering techniques. Thereafter, the bottom-gate TFT devices were fabricated by depositing Ti/Au metal pads on IGZO films, where the channel length and width were defined to be 200 and 1000 μm, respectively. Post-metallization thermal annealing of the devices was carried out at 260, 280 and 300 °C in nitrogen ambient for 1 h. The devices annealed at 280 °C have shown better characteristics with enhanced field-effect mobility and high on–off current ratio. The compositional variation of IGZO films was also observed with different annealing temperatures.     

Electrical characterization and reliability of submicron SOI CMOS technology in the extended temperature range (to 300 °C)

I-V characteristics and reliability parameters for the set of hardened SOI MOSFET's with special layouts and tungsten metallization to provide additional thermal tolerance for high-temperature SOI CMOS IC's are investigated in the temperature range up to 300 °C. The reliability aspects under test for MOSFET's are threshold voltage shift, subthreshold slope and mobility degradation, gate leakage current rise; for tungsten metallization (contacts, conductor lines and vias) I-T and R-T characteristics, failure time. The SOI MOSFET standard compact SPICE model BSIMSOI with traditional temperature limit of 150 °C is modified to be used for CMOS IC simulation in the extended temperature range up to 300 °C. The results indicate that the 0.5–0.18 μm SOI MOSFET's with tungsten metallization have stable electrical behavior that makes them possible to be used during implementation of HT CMOS IC's (to 300 °C).     

Development of chip-on-flex bonding using Sn-based bumps and non-conductive adhesive

We developed a reliable and low cost chip-on-flex (COF) bonding technique using Sn-based bumps and a non-conductive adhesive (NCA). Two types of bump materials were used for the bonding process: Sn bumps and Sn–Ag bumps. The bonding process was performed at 180 °C for 10 s using a thermo-compression bonder after dispensing the NCA. Sn-based bumps were easily deformed to contact Cu pads during the bonding process. A thin layer of Cu₆Sn₅ intermetallic compound was observed at the interface between Sn-based bumps and Cu pads. After bonding, electrical measurements showed that all COF joints had very low contact resistance, and there were no failed joints. To evaluate the reliability of COF joints, high temperature storage tests (150 °C, 1000 h), thermal cycling tests (−25 °C/+125 °C, 1000 cycles) and temperature and humidity tests (85 °C/85% RH, 1000 h) were performed. Although contact resistance was slightly increased after the reliability test, all COF joints passed failure criteria. Therefore, the metallurgical bond resulted in good contact and improved the reliability of the joints.     

Effects of thermal annealing on the morphology of the AlxGa(1−x)N films

Effects of thermal annealing on the morphology of the Al_xGa_(1−x)N films with two different high Al-contents (x=0.43 and 0.52) have been investigated by atomic force microscopy (AFM). The annealing treatments were performed in a nitrogen (N₂) gas ambient as short-time (4 min) and long-time (30 min). Firstly, the films were annealed as short-time in the range of 800–950 °C in steps of 50–100 °C. The surface root-mean-square (rms) roughness of the films reduced with increasing temperature at short-time annealing (up to 900 °C), while their surface morphologies were not changed. At the same time, the degradation appeared on the surface of the film with lower Al-content after 950 °C. Secondly, the Al_0.43Ga_0.57N film was annealed as long-time in the range of 1000–1200 °C in steps of 50 °C. The surface morphology and rms roughness of the film with increasing temperature up to 1150 °C did not significantly change. Above those temperatures, the surface morphology changed from step-flow to grain-like and the rms roughness significantly increased.     

Effects of substrate temperature on the degradation of RF sputtered NiO properties

Nickel oxide (NiO) film was grown on Si (100) substrate through RF sputtering of NiO target in Ar plasma at various temperatures ranging from room temperature (RT) to 300 °C. The structural study revealed (200) oriented NiO diffraction peak at RT and at 100 °C, however, by increasing the substrate temperature to 200 °C, intensity of (200) NiO diffraction peak was decreased. At higher temperature (300 °C), crystalline quality of NiO was significantly degraded and the film was decomposed into Ni. The EDS results confirmed an increase of Ni atomic percentage with increase of the substrate temperature. The surface morphology of NiO film at RT and at 100 °C displayed cubical like grains that were changed into elongated grains with further increase of the substrate temperature. The UV–vis reflectance measurements of NiO revealed a small decrease in its band gap by increasing the substrate temperature to 200 °C.     

Optimizing the fabrication process for high performance graphene field effect transistors

As an emerging material, graphene has attracted vast interest in solid-state physics, materials science, nanoelectronics and bioscience. Graphene has zero bandgap with its valence and conduction bands are cone-shaped and meet at the K points of the Brillouin zone. Due to its high intrinsic carrier mobility, large saturation velocity, and high on state current density, graphene is also considered as a promising candidate for high-frequency devices. To improve the reliability of graphene FETs, which include shifting the Dirac point voltage toward zero, increasing the channel mobility and decreasing the source/drain contact resistance, we optimized the device fabrication process. For CVD grown graphene, the film transfer and the device fabrication processes may produce interfacial states between graphene and the substrate and make graphene p or n-type, which shift the fermi level far away from the Dirac point. We have found that after graphene film transfer, an annealing process at 400 °C under N₂ ambient will shift Dirac point toward zero gate voltage. Ti/Au, Ni, and Ti/Pd/Au source/drain structures have been studied to minimize the contact resistance. According to the measured data, Ti/Pd/Au structure gives the lowest contact resistance (～500 ohm μm). By controlling the process of graphene growth, transfer and device fabrication, we have achieved graphene FETs with a field effective mobility of 16,000 cm²/V s after subtraction of contact resistance. The contact resistivity was estimated in the range of 1.1 × 10^?6 Ω cm² to 8.8 × 10^?6 Ω cm², which is close to state of the art III–V technology. The maximum transconductance was found to be 280 mS/mm at V_D = 0.5 V, which is the highest value among CVD graphene FETs published to date.     

Novel GaAs enhancement-mode/depletion-mode pHEMTs technology using high-k praseodymium oxide interlayer

In this study, a novel metal–semiconductor gate enhancement-mode (E-mode) and a metal–insulator-metal–semiconductor (MIMS) gate depletion-mode (D-mode) AlGaAs/InGaAs pseudomorphic high electron mobility transistor (pHEMT) on a single GaAs substrate have been developed by using high dielectric constant praseodymium insulator layer. The epitaxial layers were design for an enhancement-mode pHEMT after gate recess process. To achieve E/D-mode pHEMTs on single GaAs wafer, traditional Pt/Ti/Au metals were deposited as Schottky contact for E-mode pHEMTs and Pr/Pr₂O₃/Ti/Au were deposited as MIMS-gate for D-mode pHEMTs. This AlGaAs/InGaAs E-mode pHEMTs exhibit a gate turn-on voltage (V_ON) of +1 V and a gate-to-drain breakdown voltage of ?5.6 V, and these values were +7 V and ?34 V for MIMS-gate D-mode pHEMTs, respectively. Therefore, this high-k insulator in D-mode pHEMT is beneficial for suppressing the gate leakage current. Comparing to previous E/D-mode pHEMT technology, this E-mode pHEMTs and MIMS-gate D-mode pHEMTs exhibit a highly potential for high uniformity GaAs logic circuit applications due to its single recess process.     

Investigation of n-ohmic contact of vertical GaN-based light-emitting diodes on graphite substrate with Ag-In bonding

Vertical light-emitting diodes (VLEDs) were successfully transferred from a GaN-based sapphire substrate to a graphite substrate by using low-temperature and cost-effective Ag-In bonding, followed by the removal of the sapphire substrate using a laser lift-off (LLO) technique. One reason for the high thermal stability of the AgIn bonding compounds is that both the bonding metals and Cr/Au n-ohmic contact metal are capable of surviving annealing temperatures in excess of 600 °C. Therefore, the annealing of n-ohmic contact was performed at temperatures of 400 °C and 500 °C for 1 min in ambient air by using the rapid thermal annealing (RTA) process. The performance of the n-ohmic contact metal in VLEDs on a graphite substrate was investigated in this study. As a result, the final fabricated VLEDs (chip size: 1000 µm×1000 µm) demonstrated excellent performance with an average output power of 538.64 mW and a low operating voltage of 3.21 V at 350 mA, which corresponds to an enhancement of 9.3% in the light output power and a reduction of 1.8% in the forward voltage compared to that without any n-ohmic contact treatment. This points to a high level of thermal stability and cost-effective Ag-In bonding, which is promising for application to VLED fabrication.     

Mechanical reliability of Sn-rich Au–Sn/Ni flip chip solder joints fabricated by sequential electroplating method

In this study, we evaluated the mechanical reliability of Sn-rich, Au–Sn/Ni flip chip solder bumps by using a sequential electroplating method with Sn and Au. After reflowing, the average diameter of the solder bump was approximately 80 μm and only a (Ni,Au)₃Sn₄ intermetallic compound (IMC) layer was formed at the interface. Due to the preferential consumption of Sn atoms within the solder matrix during aging, the solder matrix was transformed sequentially in the following order: β-Sn and η-phase, η-phase, and η-phase and ε-phase. In the bump shear test, the shear force was not significantly changed despite aging at 150 °C for 1000 h and most of the fractures occurred at the interfaces. The interfacial fracture was significantly related to the formation of brittle IMCs at the interface. The Sn-rich, Au–Sn/Ni flip chip joint was mechanically much weaker than the Au-rich, Au–Sn/Ni flip chip joint. The study results demonstrated that the combination of Sn-rich, Au–Sn solder and Ni under bump metallization (UBM) is not a viable option for the replacement of the conventional, Au-rich, Au–20Sn solder.     

Iridium-based semi-transparent current spreading layer on short-period-superlattice (SPS) tunneling contact of InGaN/GaN LEDs

Iridium-containing and Ni(4 nm)/Au(6 nm) films were evaporated separately on the n⁺-InGaN–GaN short-period-superlattice (SPS) structure of light-emitting diodes (LEDs). The collective deposition of iridium and other metals as an ohmic contact induces the formation of highly transparent IrO₂, which helps to enhance the light output and decrease the series resistance of LEDs. By comparing different metal films used as current spreading contact layer, Ir/Ni film annealed at 500 °C for 20 min in O₂ ambient renders devices with lowest turn-on voltage at 20 mA and highest luminous intensity. Moreover, we also analyzed films using atomic force microscopy (AFM) with an emphasis on studying how the surface quality of Ir/Ni and Ni/Au films influences the current spreading and luminosity of LEDs.     

Growth and characterization of indium oxide diodes prepared by reactive magnetron sputtering

The electrical properties of Cr/Pt/Au and Ni/Au ohmic contacts with unintentionally doped In₂O₃ (U-In₂O₃) film and zinc-doped In₂O₃ (In₂O₃:Zn) prepared by reactive magnetron sputtering deposition are described. The lowest specific contact resistance of Cr/Pt/Au and Ni/Au is 2.94 × 10⁻⁶ and 1.49 × 10⁻² Ω-cm², respectively, as determined by the transmission line model (TLM) after heat treatment at 300 °C by thermal annealing for 10 min in nitrogen ambient. The indium oxide diodes have an ideality factor of 1.1 and a soft breakdown voltage of 5 V. The reverse leakage current prior to breakdown is around 10⁻⁵ A.