High performance sol–gel spin-coated titanium dioxide dielectric based MOS structures

High-κ TiO₂ thin films have been fabricated using cost effective sol–gel and spin-coating technique on p-Si (100) wafer. Plasma activation process was used for better adhesion between TiO₂ films and Si. The influence of annealing temperature on the structure-electrical properties of titania films were investigated in detail. Both XRD and Raman studies indicate that the anatase phase crystallizes at 400 °C, retaining its structural integrity up to 1000 °C. The thickness of the deposited films did not vary significantly with the annealing temperature, although the refractive index and the RMS roughness enhanced considerably, accompanied by a decrease in porosity. For electrical measurements, the films were integrated in metal-oxide-semiconductor (MOS) structure. The electrical measurements evoke a temperature dependent dielectric constant with low leakage current density. The Capacitance–voltage (C–V) characteristics of the films annealed at 400 °C exhibited a high value of dielectric constant (~34). Further, frequency dependent C–V measurements showed a huge dispersion in accumulation capacitance due to the presence of TiO₂/Si interface states and dielectric polarization, was found to follow power law dependence on frequency (with exponent ‘s’=0.85). A low leakage current density of 3.6×10⁻⁷ A/cm² at 1 V was observed for the films annealed at 600 °C. The results of structure-electrical properties suggest that the deposition of titania by wet chemical method is more attractive and cost-effective for production of high-κ materials compared to other advanced deposition techniques such as sputtering, MBE, MOCVD and ALD. The results also suggest that the high value of dielectric constant ‘κ‘ obtained at low processing temperature expands its scope as a potential dielectric layer in MOS device technology.     

Frequency and voltage dependency of interface states and series resistance in Al/SiO2/p-Si MOS structure

The capacitance–voltage (C–V) and conductance–voltage (G/ω–V) characteristics of Al/SiO₂/p-Si metal-oxide-semiconductor (MOS) Schottky diodes have been measured in the voltage range from ?3 to +3 V and frequency range from 5 KHz to 1 MHz at room temperature. It is found that both C and G/ω of the MOS capacitor are very sensitive to frequency. The fairly large frequency dispersion of C–V and G/ω–V characteristics can be interpreted in terms of the particular distribution of interface states at SiO₂/Si interface and the effect of series resistance. At relatively low frequencies, the interface states can follow an alternating current (AC) signal that contributes to excess capacitance and conductance. This leads to an anomalous peak of C–V curve in the depletion and accumulation regions. In addition, a peak at approximately ?0.2 V appears in the R_s–V profiles at low frequency. The peak values of the capacitance and conductance decrease with increasing frequency. The density distribution profile of interface state density (N_ss) obtained from C_HF–C_LF capacitance measurement also shows a peak in the depletion region.     

Phosphorous passivation of the SiO2/4H–SiC interface

We describe experimental and theoretical studies to determine the effects of phosphorous as a passivating agent for the SiO₂/4H–SiC interface. Annealing in a P₂O₅ ambient converts the SiO₂ layer to PSG (phosphosilicate glass) which is known to be a polar material. Higher mobility (approximately twice the value of 30–40 cm²/V s obtained using nitrogen introduced with an anneal in nitric oxide) and lower threshold voltage are compatible with a lower interface defect density. Trap density, current–voltage and bias-temperature stress (BTS) measurements for MOS capacitors are also discussed. The BTS measurements point to the possibility of an unstable MOSFET threshold voltage caused by PSG polarization charge at the O–S interface. Theoretical considerations suggest that threefold carbon atoms at the interface can be passivated by phosphorous which leads to a lower interface trap density and a higher effective mobility for electrons in the channel. The roles of phosphorous in the passivation of correlated carbon dangling bonds, for SiC counter-doping, for interface band-tail state suppression, for Na-like impurity band formation and for substrate trap passivation are also discussed briefly.     

Deposition of HfO2 on InAs by atomic-layer deposition

Metal–oxide–semiconductor (MOS) capacitors are formed on bulk InAs substrates by atomic-layer deposition (ALD) of HfO₂. Prior to film growth, InAs substrates receive a wet-chemical treatment of HCl, buffered HF (BHF), or (NH₄)₂S. Hafnium dioxide films are grown using 75 ALD cycles with substrate temperatures of 100, 200, and 300 °C. Substrate temperature is found to have a significant influence on the current–voltage (I–V) and capacitance–voltage (C–V) characteristics of the capacitors, while the influence of substrate pretreatment manifests itself in interface trap density, D_it, as measured by the Terman method.     

Time dependent breakdown characteristics of parylene dielectric in metal–insulator–metal capacitors

In this work, we present reliability results of MIM (Metal–Insulator–Metal) capacitors fabricated with parylene as the dielectric, deposited at room temperature. We have evaluated the time dependent dielectric breakdown (TDDB) of parylene-based MIM capacitors as a function of constant DC voltage stress, area and dielectric thickness of the capacitor. Mean-time-to-failure (MTTF) of parylene evaluated at different stress voltages shows a power law distribution over the applied voltage range and device area, with MTTF driven by the number of defects. Defect density in the parylene capacitors is also reported and is calculated to be ～1.2 × 10³ defects/cm².     

Temperature dependent dielectric studies of Ni/n-GaP Schottky diodes by capacitance and conductance measurements

The dielectric properties of Ni/n-GaP Schottky diode were investigated in the temperature range 140–300 K by capacitance–voltage (C–V) and conductance–voltage (G/ω–V) measurements. The effect of temperature on series resistance (R_s) and interface state density (N_ss) were investigated. The dependency of dielectric constant (ε′), dielectric loss (ε′′), loss tangent (tan δ), ac conductivity (σ_ac), real (M′) and imaginary (M′′) parts of the electric modulus over temperature were evaluated and analyzed at 1 MHz frequency. The temperature dependent characteristics of ε′ and ε′′ reveal the contribution of various polarization effects, which increases with temperature. The Arrhenius plot of σ_ac shows two activation energies revealing the presence of two distinct trap states in the chosen temperature range. Moreover, the capacitance–frequency (C–f) measurement over 1 kHz to 1 MHz was carried out to study the effect of localized interface states.     

Frequency and voltage dependence of negative capacitance in Au/SiO2/n-GaAs structures

The frequency (f) and bias voltage (V) dependence of electrical and dielectric properties of Au/SiO₂/n-GaAs structures have been investigated in the frequency range of 10 kHz–3 MHz at room temperature by considering the presence of series resistance (R_s). The values of R_s, dielectric constant (ε′), dielectric loss (ε″) and dielectric loss tangent (tan δ) of these structures were obtained from capacitance–voltage (C–V) and conductance–voltage (G/ω–V) measurements and these parameters were found to be strong functions of frequency and bias voltage. In the forward bias region, C–V plots show a negative capacitance (NC) behavior, hence ε′–V plots for each frequency value take negative values as well. Such negative values of C correspond to the maximum of the conductance (G/ω). The crosssection of the C–V plots appears as an abnormality when compared to the conventional behavior of ideal Schottky barrier diode (SBD), metal–insulator–semiconductor (MIS) and metal–oxide–semiconductor (MOS) structures. Such behavior of C and ε′ has been explained with the minority-carrier injection and relaxation theory. Experimental results show that the dielectric properties of these structures are quite sensitive to frequency and applied bias voltage especially at low frequencies because of continuous density distribution of interface states and their relaxation time.     

Resistive switching properties of a thin SiO2 layer with CeOx buffer layer on n+ and p+ Si bottom electrodes

Resistive switching properties of a 2-nm-thick SiO₂ with a CeO_x buffer layer on p⁺ and n⁺ Si bottom electrodes were characterized. The distribution of set voltage (V_set) with the p⁺ Si bottom electrode devices reveals a Gaussian distribution centered in 4.5 V, which reflects a stochastic nature of the breakdown of the thin SiO₂. Capacitance–voltage (C–V) measurements indicate the trapping of electrons by positively shifting the C–V curve by 0.2 V during the first switching cycle. On the other hand, devices with the n⁺ Si bottom electrodes showed a broad distribution in V_set with a mean value higher than that of p⁺ Si bottom electrode devices by 0.9 V. Although no charge trapping was observed with n⁺ Si bottom electrode devices, a degradation in interface states was confirmed, causing a tail in the lower side of the V_set distribution. Based on the above measurements, the difference in the V_set can be understood by the work function difference and the contribution of electron trapping.     

Improving the electrical and hysteresis performance of amorphous igzo thin-film transistors using co-sputtered zirconium silicon oxide gate dielectrics

The use of co-sputtered Zirconium Silicon Oxide (Zr_xSi_1−xO₂) gate dielectrics to improve the performance of α-IGZO TFT is demonstrated. Through modulating the sputtering power of the SiO₂ and ZrO₂ targets, the control of dielectric constant in a range of 6.9–31.6 is shown. Prevention of polycrystalline formation of the Zr_xSi_1−xO₂ film up to 600 °C annealing and its effectiveness in reducing leakage currents and interface trap density are presented. Moreover, it is revealed that the Zr_0.85Si_0.15O₂ dielectric could lead to significantly improved TFT performance in terms of subthreshold swing (SS=81 mV/dec), field-effect mobility (μ_FE=51.7 cm²/Vs), and threshold voltage shift (ΔV_TH=0.03 V).     

Electrical properties of low-dielectric-constant films prepared by PECVD in O2/CH4/HMDSO

Low-dielectric constant (low-k) films have been prepared by plasma-enhanced chemical vapor deposition (PECVD) from hexamethyldisiloxane (HMDSO) mixed with oxygen or methane. The films are analyzed by ellipsometry, infrared absorption spectroscopy while their electrical properties are deduced from C–V, I–V and R–f measurements performed on Al/insulator/Si structures. For an oxygen and methane fraction equal to 50% and 22%, respectively, the dielectric constant and losses are decreased compared with those of the film prepared in a pure HMDSO plasma. The effect of adding 22% of CH₄ in HMDSO plasma increases the Si–CH₃ bonds containing in the polymer film and as the constant of methyl groups in the film increased the dielectric constant of the film decreases. For this film, the dielectric constant is 2.8, the dielectric losses at 1 kHz are equal to 2×10⁻³, the leakage current density measured for an electric field of 1 MV/cm is 3×10⁻⁹ A/cm² and the breakdown field is close to 5 MV/cm.     

In-situ MBE Si as passivating interlayer on GaAs for HfO2 MOSCAP’s: effect of GaAs surface reconstruction

We report a study of MOS capacitors having a dielectric of HfO₂ and an interlayer of Si deposited in-situ, by MBE on GaAs surfaces prepared with various surface-reconstructions. Interface state densities of about 1 × 10¹² eV⁻¹cm⁻² have been obtained. Capacitors on the Ga-rich surface, measured with peripheral illumination, show signs of a possible inversion layer.     

Dielectric characteristics of gamma irradiated Au/SnO2/n-Si/Au (MOS) capacitor

The dielectric characteristics of gamma irradiated Au/SnO₂/n-Si/Au (MOS) capacitor were studied. The MOS capacitor was irradiated by a ⁶⁰Co gamma radiation source with a dose rate of 0.69 kGy/h. The dielectric parameters such as dielectric constant (ε′), dielectric loss (ε″), loss factor (tan δ) and ac electrical conductivity (σ_ac) were calculated from the capacitance–voltage (C–V) and conductance–voltage (G/ω–V) measurements. It is found that the C and G/ω values decrease with the increasing total dose due to the irradiation-induced defects at the interface. Also, the calculated values of ε′, ε″ and σ_ac are found to decrease with an increased radiation dose. This result indicates that the dielectric characteristics of the MOS capacitor are sensitive to gamma-ray dose.     

Reduced contact resistance and highly stable operation in polymer thin-film transistor with aqueous MoOx solution contact treatment

We report on a newly developed solution process using MoO₃ for reducing source and drain (S/D) electrodes in organic thin-film transistor (TFT). By taking advantage of the difference in surface wettability between the gate dielectric layer and the S/D electrodes, the electrode treatment using the MoO_x solution was applied to polymer TFT with short channel lengths less than 10 μm. The contact resistance was noticeably reduced at the interface of the S/D electrodes in a polymer TFT using a pBTTT-C16. Furthermore, the field effect mobility for this TFT was enhanced from 0.03 to 0.1 cm²/V s. Most notably, the threshold voltage (V_th) shift under gated bias stress was less than 0.2 V after 10⁵ s, which is comparable to that of conventional poly crystalline Si TFT.     

Electrical characterization of MFeOS gate stacks for ferroelectric FETs

We investigated the electrical characterization of metal–ferroelectric–oxide semiconductor (MFeOS) structures for nonvolatile memory applications. Al/PZT/Si and Al/PZT/SiO₂/Si capacitors were fabricated using lead zirconate titanate (PZT; 35:65) as the ferroelectric layer. The maximum C–V memory window was 6 V for metal–ferroelectric semiconductor (MFeS) structures and 2.95 and 6.25 V for MFeOS capacitors with a buffer layer of 2.5 and 5 nm, respectively. Comparative data reveal a higher dielectric strength and lower leakage characteristic for an MFeOS structure with a 5-nm SiO₂ buffer layer compared to an MFeS structure. We also observed that the leakage characteristic was influenced by the annealing conditions.     

Oxide and interface trap densities estimation in ultrathin W/La2O3/Si MOS capacitors

A novel interpretation for conductance spectra obtained by conductance method of La₂O₃ gated MOS capacitors has been proposed. Two distinct peaks, one with broad spectrum ranging from 10 k to 200 kHz and the other near 1 kHz with a single time constant spectrum, have been observed at depletion condition. The former spectrum can be assigned as the interface traps (D_it) located at the interface between La-silicate and the Si substrate by statistical surface potential fluctuation model. On the other hand, as the latter slow trap signal shows strong influence with the thickness of La-silicate layer, it can be assigned as the trappings (D_slow) at the interface between La₂O₃ and La-silicate. Finally, the D_it and D_slow trends on annealing temperature are summarized.     

The effect of oxide layer thickness on the quantification of 1.5 MeV γ–radiation induced interface traps in the Ag/SiO2/Si MOS devices

This work presents the effect of varied thickness of oxide layer and radiation dose on electrical characteristics of Ag/SiO₂/Si MOS devices irradiated by 1.5 MeV γ–radiations of varied doses. SiO₂ layers of 50, 100, 150 and 200 nm thickness were grown on Si substrates using dry oxidation and exposed to radiation doses of 1, 10 and 100 kGy. The exposure to radiation resulted in generation of fixed charge centers and interface traps in the SiO₂ and at the Si/SiO₂ interface. Capacitance-conductance-voltage (C-G-V) and capacitance-conductance-frequency (C-G-f) measurements were performed at room temperature for all MOS devices to quantify the active traps and their lifetimes. It is shown that accumulation and minimum capacitances decreased as the thickness of SiO₂ layer increased. For the unexposed MOS devices, the flat band voltage V_FB decreased at a rate of −0.12 V/nm, density of active traps increased by 4.5 times and depletion capacitance C_DP, increased by 2.5 times with the increase of oxide layer thickness from 50 to 200 nm. The density of active traps showed strong dependence on the frequency of the applied signal and the thickness of the oxide layer. The MOS device with 200 nm thick oxide layer irradiated with 100 kGy showed density of active interface traps was high at 50 kHz and was 3.6×10¹⁰ eV⁻¹ cm⁻². The relaxation time of the interface traps also increased with the exposure of γ–radiation and reached to 9.8 µs at 32 kHz in 200 nm thick oxide MOS device exposed with a dose of 100 kGy. It was inferred that this was due to formation of continuum energy states within the band gap and activation of these defects depended on the thickness of oxide layer, applied reverse bias and the working frequency. The present study highlighted the role of thickness of oxide layer in radiation hard environments and that only at high frequency, radiation induced traps remain passivated due to long relaxation times.     

Characteristics of RF reactive sputter-deposited Pt/SiO2/n-InGaN MOS Schottky diodes

All RF sputtering-deposited Pt/SiO₂/n-type indium gallium nitride (n-InGaN) metal–oxide–semiconductor (MOS) diodes were investigated before and after annealing at 400 °C. By scanning electron microscopy (SEM), the thickness of Pt, SiO_2, n-InGaN layer was measured to be ~250, 70, and 800 nm, respectively. AFM results also show that the grains become a little bigger after annealing, the surface topography of the as-deposited film was smoother with the rms roughness of 1.67 nm and had the slight increase of 1.92 nm for annealed sample. Electrical properties of MOS diodes have been determined by using the current–voltage (I–V) and capacitance–voltage (C–V) measurements. The results showed that Schottky barrier height (SBH) increased slightly to 0.69 eV (I–V) and 0.82 eV (C–V) after annealing at 400 °C for 15 min in N₂ ambient, compared to that of 0.67 eV (I–V) and 0.79 eV (C–V) for the as-deposited sample. There was the considerable improvement in the leakage current, dropped from 6.5×10⁻⁷ A for the as-deposited to 1.4×10⁻⁷ A for the 400 °C-annealed one. The annealed MOS Schottky diode had shown the higher SBH, lower leakage current, smaller ideality factor (n), and denser microstructure. In addition to the SBH, n, and series resistance (R_s) determined by Cheungs׳ and Norde methods, other parameters for MOS diodes tested at room temperature were also calculated by C–V measurement.     

Effect of the work function of gate electrode on hysteresis characteristics of organic thin-film transistors with Ta2O5/polymer as gate insulator

Organic thin-film transistors (OTFTs) using high dielectric constant material tantalum pentoxide (Ta₂O₅) and benzocyclobutenone (BCBO) derivatives as double-layer insulator were fabricated. Three metals with different work function, including Al (4.3 eV), Cr (4.5 eV) and Au (5.1 eV), were employed as gate electrodes to study the correlation between work function of gate metals and hysteresis characteristics of OTFTs. The devices with low work function metal Al or Cr as gate electrode exhibited high hysteresis (about 2.5 V threshold voltage shift). However, low hysteresis (about 0.7 V threshold voltage shift) OTFTs were attained based on high work function metal Au as gate electrode. The hysteresis characteristics were studied by the repetitive gate voltage sweep of OTFTs, and capacitance–voltage (C–V) and trap loss-voltage (G_p/ω?V) measurements of metal–insulator–semiconductor (MIS) devices. It is proved that the hysteresis characteristics of OTFTs are relative to the electron injection from gate metal to Ta₂O₅ insulator. The electron barrier height between gate metal and Ta₂O₅ is enhanced by using Au as gate electrode, and then the electron injection from gate metal to Ta₂O₅ is reduced. Finally, low hysteresis OTFTs were fabricated using Au as gate electrode.     

Optical and electrical characteristics of 17 keV X-rays exposed TiO2 films and Ag/TiO2/p-Si MOS device

This work presents the effect of varied doses of X-rays radiation on the Ag/TiO₂/p-Si MOS device. The device functionality was observed to depend strongly on the formation of an interfacial layer composed of SiO_x and TiO_y, which was confirmed by the spectroscopic ellipsometry. The XRD patterns showed that the as prepared TiO₂ films had an anatase phase and its exposure to varied doses of 17 keV X-rays resulted in the formation of minute rutile phase. In the X-rays exposed films, reduced Ti³⁺ state was not observed; however a fraction of Ti–O bonds disassociated and little oxygen vacancies were created. It was observed that the device performance was mainly influenced by the nature and composition of the interfacial layer formed at the TiO₂/Si interface. The spectroscopic ellipsometry was used to determine the refractive indices of the interfacial layer, which was 2.80 at λ=633 nm lying in between that of Si (3.87) and TiO₂ (2.11). The dc and frequency dependent electrical measurements showed that the interface defects (traps) were for both types of charge carriers. The presence of SiO_x was responsible for the creation of positive charge traps. The interface trap density and relaxation time (τ) were determined and analyzed by dc and frequency dependent (100 Hz–1 MHz) ac-electrical measurements. The appearance of peak in G/ω vs log (f) confirmed the presence of interface traps. The interface traps initially increased up to exposure of 10 kGy and then decreased at high dose due to compensation by the positive charge traps in SiO_x part of the interface layer. It was observed that large number of interface defects was active at low frequencies and reduced to a limiting value at high frequency. The values of relaxation time, τ ranged from 4.3±0.02×10⁻⁴ s at 0 V and 7.6±0.2×10⁻⁵ s at −1.0 V.     

Electrical characterization and TCAD simulations of multi-gate bulk nMOSFET

A multi-gate nMOSFET in bulk CMOS process has been fabricated by integration of polysilicon-filled trenches. We have simulated its electrical characteristics by using TCAD software and compared them with results obtained from electrical measurements. The threshold voltage and the subthreshold slope of the top gate have been extracted and we found a good accordance, for both parameters, between the measurements (V_TH=0.59 V, S=90 mV/dec) and simulations (V_TH=0.50 V, S=92 mV/dec). The surface channel effective mobility of this multi-gate MOSFET was extracted and evaluated with both effective length and surface. The studies revealed that mobility degraded towards smaller dimensions of the MOS channel. At last, the Si/SiO₂ interface quality studies were carried out. We noticed that the injected donor traps have a larger influence on the current–voltage characteristics than acceptor-like traps. With its good electrical performances, this low-cost multi-gate MOSFET technology presents interesting perspective in CMOS image sensors and more generally in analog application taking benefit of the multi-threshold for example.