Reliability impact due to high current,lattice and hot carriers temperatures on β(2×2) matrix ESD power devices for advanced CMOS technologies

The main purpose of this paper is to present the behavior of a β^(2×2) matrix ESD power device with the effects of high ESD current, lattice and hot carriers temperatures. The beta matrix is a candidate for ESD device network for advanced CMOS technologies. This demonstrator is done in C45 & C32 nm CMOS technologies. The high ESD current, lattice temperature and hot carriers temperature are study thanks to 3D TCAD simulations in ACS stimulus. Thus, it is possible to identify the potential weakness point and optimize the topology of this kind of power device. Moreover, the IV curves are measured in TLP condition to determine the ESD response.     

An efficient combinational approach for PAPR reduction in MIMO–OFDM system

The multiple input multiple output (MIMO) with orthogonal frequency division multiplexing (OFDM) has emerged as a promising solution to enhance the channel capacity and diversity of wireless communication system without any increase in bandwidth. In this paper, a parallel combinational scheme is proposed to reduce peak-to-average power ratio (PAPR) in MIMO–OFDM system under Rayleigh fading environment. The proposed method intelligently incorporates both active gradient project and partial transmit sequence schemes. The results show that the proposed method not only reduces the PAPR and computational complexity of the system but also maintains the bit error rate compared to other schemes.     

An in-situ numerical–experimental approach for fatigue delamination characterization in microelectronic packages

An in-situ and cost-effective numerical–experimental approach for fatigue characterization of bi-material interfaces in microelectronic packages is presented. In this method using a sample-centered approach, a miniaturized sub-critical bending (MSCB) test setup is designed and fabricated based on the samples that are acquired directly from the production-line. Sub-critical crack growth (SCCG) is captured along the surface between molding compound (MC) and copper lead-frame (LF) in the samples prepared from Thin Quad Flat Package (TQFP). The toughness values such as critical (G_c) and sub-critical strain energy release rate (G_th) are measured. It is shown that crack propagation along the MC/LF interface is highly fatigue sensitive. In addition, fatigue–fracture tests under different isothermal conditions reveal that, the toughness values are higher in lower temperatures. The fractographical study of samples shows that, although some of the molding compound particles are left on the LF surface, the interfacial fracture is the dominant failure mode.     

Analysis of mechanisms for electron scattering in GaAs/AlxGa1−x As superlattices with doped quantum wells for longitudinal resonant current flow in high electric fields and at low temperatures

Formulas are derived for, and a numerical analysis made of, the dependence of the transverse phase relaxation time on electron energy for resonant current flow through GaAs/Al_xGa_1−x As superlattices with doped quantum wells. The parameters are chosen to be close to those of superlattices used for creating photodiodes for operation at λ⋍10 μm. The analysis is limited to the interactions of electrons with neutral atoms and impurity ions at low temperatures. Resonant current flow is ensured by an electric field that brings the ground state and the first excited state of the “Stark ladder” into resonance with neighboring, weakly interacting quantum wells. Fiz. Tekh. Poluprovodn. 33, 438–444 (April 1999)     

Delay-dependent H ∞ control for 2-D discrete state delay systems in the second FM model

This paper is concerned with the problem of delay-dependent H _∞ control for two-dimensional (2-D) discrete state delay systems described by the second Fornasini and Marchesini (FM) state-space model. Based on a summation inequality, a sufficient condition to have a delay-dependent H _∞ noise attenuation for this 2-D system is given in terms of linear matrix inequalities (LMIs). A delay-dependent optimal state feedback H _∞ controller is obtained by solving an LMI optimization problem. Finally, a simulation example of thermal processes is given to illustrate the effectiveness of the proposed result.

An adaptive spatial–spectral total variation approach for Poisson noise removal in hyperspectral images

Poisson distributed noise, such as photon noise, is an important noise source in multi- and hyperspectral images. We propose a variational-based denoising approach that accounts the vectorial structure of a spectral image cube, as well as the Poisson distributed noise. For this aim, we extend an approach initially developed for monochromatic images, by a regularisation term, which is spectrally and spatially adaptive and preserves edges. In order to take the high computational complexity into account, we derive a split Bregman optimisation for the proposed model. The results show the advantages of the proposed approach compared with a marginal approach on synthetic and real data.     

Analog to digital converter for high density neural signal recording front-end in 90 nm

High-fidelity recording of neural signals requires varying levels of signal gain to capture low-amplitude single-unit activity in the presence of high-amplitude population activity. A floating-point approach has been used to widen the dynamic range of analog-to-digital converters (ADC) designed for this application. In this paper we present an ADC, designed for multi-channel, portable neural signal recording systems. To achieve low power consumption, small die area and wide dynamic range, an ADC based on a time-based algorithm, combined with a floating-point pipelined structure has been designed and simulated. A conventional variable-gain amplifier (VGA) stage has been eliminated in favor of a reference-current in a time-based ADC architecture. The 12-b pipelined time-based floating-point ADC has been designed with a 7-b mantissa and an exponent that provides an additional 5 bits of dynamic range. The mantissa is determined by a uniform 7-b pipelined time-based analog to digital converter. The ADC chip was designed and simulated in a 90 nm CMOS process, which occupies an active area of 360 μm × 550 μm, and consumes 7.8 μW at 1.2 V in full-scale conversion.     

Lifetime analysis of solder joints in high power IGBT modules for increasing the reliability for operation at 150 °C

The increased demand for higher operating junction temperatures in IGBT modules is a main challenge for future packaging technologies. Two critical design features regarding this aspect include the terminal solder joints and the large area solder joints. The main focus of this investigation is on the consequences of raising the maximum operating temperature of IGBT modules and the required design modifications of solder materials at a microstructure level for tackling the drawbacks of state-of-the-art technologies.     

Single-inductor dual-output (SIDO) DC–DC converters for minimized cross regulation and high efficiency in soc supplying systems

A compact size and high efficiency single-inductor dual-output (SIDO) DC–DC converter is proposed. The proposed SIDO DC–DC converter not only provides dual output sources (one buck and one boost outputs) but also has minimized cross regulation without using any external compensation components. Generally speaking, it is important to minimize the number of components and footprint area in the design of SIDO converters. However, usually large external compensation resistors and capacitors are required to stabilize DC–DC converters. Importantly, our proposed hysteresis mode operation can effectively avoid the oscillation problems that may exist in many SIMO designs. Furthermore, the dynamic dc current level like that in the continuous conduction mode (CCM) operation can make the proposed SIDO DC–DC converter achieve high conversion efficiency at light loads owing to small conduction loss. Experimental results show a high efficiency from 85% at light loads to 94% at heavy loads.     

Economics of “design for test” to remain competitive in the 90s

This article emphasizes the criticality of maximizing value adders and minimizing the costs of design for test (DFT) in order to remain competitive in ASIC manufacturing in the 90s.     

Correction to: An Enhanced Cooperative Communication Scheme for Physical Uplink Shared Channel in NB‑IoT

Wireless Personal Communications - There were errors in the first and fourth authors' names in the initial online publication. The original article has been corrected.     

Comments on “VLSI implementation of Reed-Solomon encoder algorithm for communication systems”

This comment points out the four inaccurate equations and incorrect output parity values computed using RS(255, 223) encoder algorithm. The four correct equations and correct output parity values for the given input are provided here.     

Photografting Coating: An Innovative Approach to “Non-Migratory” Active Packaging

The increasing trend of sustainability (single-use packaging), safety (fresh consumption), and convenience (processing and application) in packaging science has created a high demand for packaging materials with advanced functions. Thus, the challenges involved with conventional active packaging, for example, migration, low efficiency, upscaling difficulty, safety, and regulations should be addressed through an industrial scalable method, such as photografting coating. Photografting coating, which involves a strong surface covalent linkage, can be employed for preparing novel “non-migratory” active packaging systems with strong antimicrobial and self-cleaning, antifouling and self-defensive, metal chelating as antioxidant, free-radical scavenging as antioxidant, biocatalytic, and easy printing properties. Herein, profound insights into the technique of photografting coating are provided, with a focus on its application potential in non-migratory active packaging. The scientific explanation for the photografting coating technique and its application feasibility are illustrated to introduce its potential to confer new functions onto packaging materials. Furthermore, the recent progress, application functions, process, and safety challenges, as well as future directions of photografting coating in the preparation of non-migratory active packaging systems are explored in detail.     

On a “central inequality” in the theory of input-output systems

In the stability and sensitivity theory of general, nonlinear input-output systems we encounter a certain inequality concerning solely the nominal system that plays a central role in the whole theory. In particular, this central inequality, combined with other assumptions, implies (a) stability of the nominal system, (b) robustness, and (c) insensitivity of the input-output system. This paper presents conditions equivalent to this central inequality, and a further result on the stability-robustness problem.